KR930001312A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR930001312A
KR930001312A KR1019920009752A KR920009752A KR930001312A KR 930001312 A KR930001312 A KR 930001312A KR 1019920009752 A KR1019920009752 A KR 1019920009752A KR 920009752 A KR920009752 A KR 920009752A KR 930001312 A KR930001312 A KR 930001312A
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insulating film
semiconductor device
metal
forming
manufacturing
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KR1019920009752A
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Korean (ko)
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아다찌 히로시
아다찌 에쭈시
미나미 신다로
고다니 히데오
하가시데 요시오
쭈쭈미 도시아끼
이시이 아쭈시
마쭈우라 마사쭈미
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시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
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Publication of KR930001312A publication Critical patent/KR930001312A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

내용 없음No content

Description

반도체 장치 및 그의 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1의 실시예의 반도체장치 그의 제조 방법의 1예의 1공정을 표시하는 단면 모델도.1 is a cross-sectional model diagram showing one step of an example of a method of manufacturing the semiconductor device of the first embodiment of the present invention.

제2도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조 방법의 1예의 1공정을 표시하는 단면 모델도.FIG. 2 is a cross-sectional model diagram showing one step of one example of a method for manufacturing the semiconductor device of the first embodiment of the present invention. FIG.

제3도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조방법의 1예의 1공정을 표시하는 단면 모델도.3 is a cross-sectional model diagram showing one step of one example of a method for manufacturing the semiconductor device of the first embodiment of the present invention.

제4도는 본 발명의 제1의실시예의 반도체 장치 그의 제조 방법의 1예의 1공정을 표시하는 단면 모델도.4 is a cross-sectional model diagram showing one step of one example of a method for manufacturing the semiconductor device of the first embodiment of the present invention.

제5도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조 방법의 1예의 1공정을 표시하는 단면 모델도.FIG. 5 is a cross-sectional model diagram showing one step of one example of a method for manufacturing the semiconductor device of the first embodiment of the present invention. FIG.

제6도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조 방법의 1예의 1공정을 표시하는 단면 모델도.6 is a cross-sectional model diagram showing one step of one example of a method for manufacturing the semiconductor device of the first embodiment of the present invention.

제7도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조 방법의 타의 예의 1공정을 표시하는 단면 모델도.FIG. 7 is a cross-sectional model diagram showing one step of another example of the method for manufacturing the semiconductor device of the first embodiment of the present invention. FIG.

제8도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조 방법의 타의 예의 1공정을 표시하는 단면 모델도.8 is a cross-sectional model diagram showing one step of another example of the method for manufacturing the semiconductor device of the first embodiment of the present invention.

제9도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조방법의 타의 예의 1공정을 표시하는 단면 모델도.9 is a cross-sectional model diagram showing one step of another example of the method for manufacturing the semiconductor device of the first embodiment of the present invention.

제10도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조방법의 타의 예의 1공정을 표시하는 단면 모델도.10 is a cross-sectional model diagram showing one step of another example of the method for manufacturing the semiconductor device of the first embodiment of the present invention.

제11도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조방법의 타의 예의 1공정을 표시하는 단면 모델도.FIG. 11 is a cross-sectional model diagram showing one step of another example of the method for manufacturing the semiconductor device of the first embodiment of the present invention. FIG.

제12도는 본 발명의 제1의 실시예의 반도체 장치 그의 제조방법의 타의 예의 1공정을 표시하는 단면 모델도.12 is a cross-sectional model diagram showing one step of another example of the method for manufacturing the semiconductor device of the first embodiment of the present invention.

제13도는 본 발명의 제1의 실시예의 반도체 장치를 표시하는 단면 모델도.Fig. 13 is a cross-sectional model diagram showing a semiconductor device of a first embodiment of the present invention.

제14도는 본 발명의 제3의 실시예의 반도체 장치 그의 제조 방법을 공정순으로 표시하는 단면 모델도.Fig. 14 is a cross-sectional model diagram showing a method of manufacturing the semiconductor device of the third embodiment of the present invention in the order of process.

제15도는 본 발명의 일 실시예의 반도체 장치의 제조방법의 1공정을 표시하는 단면 모델도.FIG. 15 is a cross-sectional model view showing one step of the manufacturing method of the semiconductor device of one embodiment of the present invention. FIG.

제16도는 본 발명의 일 실시예의 반도체 장치의 제조방법의 1공정을 표시하는 단면 모델도.16 is a cross-sectional model diagram showing one step of the method of manufacturing a semiconductor device of one embodiment of the present invention.

제17도는 본 발명의 일 실시예의 반도체 장치의 제조방법의 1공정을 표시하는 단면 모델도.17 is a cross-sectional model view showing one step of the method of manufacturing a semiconductor device of one embodiment of the present invention.

제18도는 본 발명의 일 실시예의 반도체 장치의 제조방법의 1공정을 표시하는 단면 모델도.18 is a cross-sectional model view showing one step of the method of manufacturing a semiconductor device of one embodiment of the present invention.

제19도는 본 발명의 일 실시예의 반도체 장치의 제조방법의 1공정을 표시하는 단면 모델도.19 is a cross-sectional model view showing one step of the method of manufacturing a semiconductor device of one embodiment of the present invention.

제20도는 본 발명의 일 실시예의 반도체 장치의 제조방법의 1공정을 표시하는 단면 모델도.20 is a cross-sectional model diagram showing one step of the method of manufacturing a semiconductor device of one embodiment of the present invention.

제21도는 본 발명의 일 실시예의 반도체 장치의 제조방법의 1공정을 표시하는 단면 모델도.21 is a cross-sectional model view showing one step of the method of manufacturing a semiconductor device of one embodiment of the present invention.

제22도는 본 발명의 타의 실시예의 반도체 장치의 제조방법의 공정순으로 표시하는 단면 모델도.Fig. 22 is a cross-sectional model diagram shown in the order of steps of a method of manufacturing a semiconductor device of another embodiment of the present invention.

Claims (4)

소자가 형성된 반도체 기판, 이 반도체 기판상에 형성된 절연막, 이 절연막상에 형성된 제1, 제2의 금속배선이 제1, 제2의 금속배선간에 개재하여 형성되는 층간 절연막 및 CVD법에 의하여 상기 층간 절연막에 열려진 콘택트 구멍 중에 메꾸어 형성되어 상기 제1, 제2의 금속 배선 끼리를 전기적으로 접속하는 금속층을 대비하는 반도체 장치에 상기 층간 절연막의 적어도 최상층부가 수지막에서 되는 것을 특징으로 하는 반도체 장치.A semiconductor substrate on which an element is formed, an insulating film formed on the semiconductor substrate, an interlayer insulating film formed between the first and second metal wirings formed on the insulating film, and by the CVD method A semiconductor device, wherein at least the uppermost layer of the interlayer insulating film is formed of a resin film in a semiconductor device which is formed in a contact hole opened in the insulating film and contrasts with a metal layer electrically connecting the first and second metal wires. 제1항에 있어서, 수지막은 하기 화학식(1)으로 표시되는 실리콘 래더 폴리머 인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the resin film is a silicon ladder polymer represented by the following general formula (1). [화 1][Tue 1] 식증 R1, R3는 페닐기, 저급 알킬기 또는 감광기 R3, R4, R5, R6는 수소원자, 저급알킬기 또는 감광기 n는 20∼1000의 정수를 표시함.Expression R 1 , R 3 is a phenyl group, lower alkyl group or photosensitive group R 3 , R 4 , R 5 , R 6 is hydrogen atom, lower alkyl group or photosensitive group n represents an integer of 20-1000. 제1항 또는 제2항에 있어서, 실리콘 래더 폴리머는 광 중합성을 소유하는 것으로 있는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1 or 2, wherein the silicon ladder polymer possesses photopolymerizability. 소자가 형성된 반도체 기판에 절연막을 형성하는 공정, 이 절연막 상에 제1의 금속배선을 형성하는 공정, 이 제1의 금속 배선상에 층간 절연막을 형성하는 공정, 이 층간 절연막에 열려진 콘택트 구멍에 CVD법에 의해 금속을 메꾸어 상기 제1의 금속배선과 전기적으로 접속하는 금속층을 형성하는 공정 및 상기 금속층과 전기적으로 접속하는 제2의 금속배선을 형성하는 공정을 세우는 반도체 장치의 제조방법에 있어서 상기 화학식(1)으로 표시되는 실리콘 래더 폴리머 막을 마스크재로 하여 CVD법에 의하여 상기 금속을 상기 구멍에 메우도록 한 것을 특징으로 하는 반도체 장치의 제조방법.Forming an insulating film on the semiconductor substrate on which the element is formed; forming a first metal wiring on the insulating film; forming an interlayer insulating film on the first metal wiring; and CVD through a contact hole opened in the interlayer insulating film. A method of manufacturing a semiconductor device, comprising the steps of forming a metal layer electrically filling a metal by a method and electrically connecting said first metal wiring and forming a second metal wiring electrically connecting said metal layer. A method of manufacturing a semiconductor device, wherein the metal is filled in the hole by CVD using the silicon ladder polymer film represented by (1) as a mask material. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920009752A 1991-06-06 1992-06-05 Semiconductor device and manufacturing method thereof KR930001312A (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP91-163956 1991-06-06
JP16395691 1991-06-06
JP16563191 1991-07-05
JP91-165631 1991-07-05
JP17541791 1991-07-16
JP91-175417 1991-07-16
JP3245673A JPH0574963A (en) 1991-06-06 1991-09-25 Semiconductor device and manufacture thereof
JP91-245673 1991-09-25

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US6326318B1 (en) 1995-09-14 2001-12-04 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US6825132B1 (en) 1996-02-29 2004-11-30 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device including an insulation film on a conductive layer
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US6288438B1 (en) 1996-09-06 2001-09-11 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
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