KR910017611A - Wiring Formation Method of Integrated Circuit Using Metal Liquid Hole Filling - Google Patents

Wiring Formation Method of Integrated Circuit Using Metal Liquid Hole Filling Download PDF

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Publication number
KR910017611A
KR910017611A KR1019900002996A KR900002996A KR910017611A KR 910017611 A KR910017611 A KR 910017611A KR 1019900002996 A KR1019900002996 A KR 1019900002996A KR 900002996 A KR900002996 A KR 900002996A KR 910017611 A KR910017611 A KR 910017611A
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KR
South Korea
Prior art keywords
wiring layer
integrated circuit
hole filling
metal
formation method
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Application number
KR1019900002996A
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Korean (ko)
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KR930003841B1 (en
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전영권
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문정환
금성일렉트론 주식회사
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Priority to KR1019900002996A priority Critical patent/KR930003841B1/en
Publication of KR910017611A publication Critical patent/KR910017611A/en
Application granted granted Critical
Publication of KR930003841B1 publication Critical patent/KR930003841B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

메탈 리큐드의 홀 필링을 이용한 집적회로의 배선 형성방법Wiring Formation Method of Integrated Circuit Using Metal Liquid Hole Filling

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2도는 본 발명의 배선층 형성방법, 제 3도는 제 2도를 설명하기 위한 그래프.2 is a graph for explaining the wiring layer forming method of the present invention, and FIG.

Claims (2)

실리콘 혹은 1차 배선층(1)위에 콘택트 및 비어 피일드 산화막(2)이 형성된 것에 있어서, A1 이나 A1 합금(3)의 저저항 금속층을 하부 배선층으로 증착하고 상부 배선층으로서 열처리 혹은 급속 열처리 온도에서 하부 배선층의 금속재료와 상평형을 이루는 액상조성의 A1합금(4)을 증착하며, Si3N4(5)를 상부물질로 디포지션하고 열처리 혹은 금속 열처리하여 상부 배선층을 액상으로 만들어 하부배선층 사이로 흘러들어가게 한 후 Si3N4(5)를 제함을 특징으로 하는 메탈 리큐드의 홀 필링을 이용한 집적회로의 배선 형성방법.In the contact and via-film oxide film 2 formed on the silicon or primary wiring layer 1, a low resistance metal layer of A1 or A1 alloy 3 is deposited as the lower wiring layer and lowered at the heat treatment or rapid heat treatment temperature as the upper wiring layer. A1 alloy (4) of liquid composition forming a phase equilibrium with the metal material of the wiring layer is deposited, and Si 3 N 4 (5) is deposited as an upper material and heat-treated or metal heat-treated to make the upper wiring layer liquid and flow between the lower wiring layers. A method for forming an integrated circuit wiring using hole filling of a metal liquid, characterized in that after removing the Si 3 N 4 (5). 제 1항에 있어서, 하부 배선층과 상부 배선층의 합금조성을 각각 다르게 하여 열처리 온도에서 액상을 형성시킴을 특징으로 하는 메탈 리큐드의 홀 필링을 이용한 집적회로의 배선 형성방법.The method of claim 1, wherein the liquid phase is formed at a heat treatment temperature by different alloy compositions of the lower wiring layer and the upper wiring layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900002996A 1990-03-07 1990-03-07 Integrated wiring making method using hole filling of metal liquid KR930003841B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900002996A KR930003841B1 (en) 1990-03-07 1990-03-07 Integrated wiring making method using hole filling of metal liquid

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002996A KR930003841B1 (en) 1990-03-07 1990-03-07 Integrated wiring making method using hole filling of metal liquid

Publications (2)

Publication Number Publication Date
KR910017611A true KR910017611A (en) 1991-11-05
KR930003841B1 KR930003841B1 (en) 1993-05-13

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Application Number Title Priority Date Filing Date
KR1019900002996A KR930003841B1 (en) 1990-03-07 1990-03-07 Integrated wiring making method using hole filling of metal liquid

Country Status (1)

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KR (1) KR930003841B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100784106B1 (en) * 2006-09-08 2007-12-10 주식회사 하이닉스반도체 Method of forming a metal layer for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100784106B1 (en) * 2006-09-08 2007-12-10 주식회사 하이닉스반도체 Method of forming a metal layer for semiconductor device

Also Published As

Publication number Publication date
KR930003841B1 (en) 1993-05-13

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