KR20240161471A - Semiconductor devices and their manufacturing methods - Google Patents

Abstract

The present invention aims to provide stable electrical characteristics to a transistor using an oxide semiconductor film. Furthermore, a transistor using an oxide semiconductor film provides excellent electrical characteristics. Furthermore, a highly reliable semiconductor device having this transistor is provided.
For a transistor having a multilayer film in which an oxide semiconductor film and an oxide film are laminated, and a gate electrode and a gate insulating film, the multilayer film is formed by overlapping the gate electrode with the gate insulating film interposed therebetween, and the multilayer film has a shape having a first angle between a lower surface of the oxide semiconductor film and a side surface of the oxide semiconductor film, and a second angle between the lower surface of the oxide film and the side surface of the oxide film, the first angle being smaller than the second angle and being an acute angle. In addition, a semiconductor device is manufactured by using this transistor.

Description

Semiconductor devices and their manufacturing methods

The present invention relates to a semiconductor device and a method for manufacturing the same.

In addition, in this specification, a semiconductor device refers to a device in general that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

The technology of constructing a transistor using a semiconductor film formed on a substrate having an insulating surface is attracting attention. This transistor is widely used in semiconductor devices such as integrated circuits and display devices. A silicon film is known as a semiconductor film that can be applied to a transistor.

The silicon film used in the semiconductor film of the transistor is divided into amorphous silicon film and polycrystalline silicon film depending on the purpose. For example, in the case of application to a transistor constituting a large display device, it is very suitable to use an amorphous silicon film for which a film formation technology for a large-area substrate has been established. On the other hand, in the case of application to a transistor constituting a high-function display device in which a driving circuit is integrally formed, it is very suitable to use a polycrystalline silicon film that can produce a transistor having a high field-effect mobility. A method of forming a polycrystalline silicon film by performing a high-temperature heat treatment or laser light treatment on an amorphous silicon film is known.

In addition, oxide semiconductor films have recently attracted attention. For example, a transistor using an oxide semiconductor film containing indium, gallium, and zinc having a carrier density of less than 10 ¹⁸ /cm ³ has been disclosed (see Patent Document 1).

Since the oxide semiconductor film can be formed using the sputtering method, it can be applied to transistors that constitute large display devices. In addition, since the transistor using the oxide semiconductor film has high field-effect mobility, it is possible to realize a high-function display device that forms an integrated driving circuit. In addition, since it is possible to improve and utilize part of the production equipment for transistors using amorphous silicon films, there is also an advantage of reducing equipment investment.

However, it is known that transistors using oxide semiconductor films have very small leakage currents (also called off-state currents) in the off state. For example, a low-power CPU that utilizes the low leakage characteristics of transistors using oxide semiconductor films has been disclosed (see Patent Document 2).

Japanese Special Publication No. 2006-165528 Specification of United States Patent Application Publication No. 2012/0032730

Transistors using oxide semiconductor films have poor electrical characteristics due to defects occurring within the oxide semiconductor film and defects occurring at the interface with the insulating film in contact with the oxide semiconductor film. In addition, as the application of transistors using oxide semiconductor films expands, the requirements for reliability are diversifying.

Accordingly, one aspect of the present invention has as its object the task of imparting stable electrical characteristics to a transistor using an oxide semiconductor film. Furthermore, one aspect of the present invention has as its object the task of imparting excellent electrical characteristics to a transistor using an oxide semiconductor film. Furthermore, one aspect of the present invention has as its object the task of providing a highly reliable semiconductor device having this transistor.

One embodiment of the present invention is a semiconductor device having a multilayer film in which an oxide semiconductor film and an oxide film are laminated, a gate electrode, and a gate insulating film, wherein the multilayer film is formed to overlap the gate electrode with the gate insulating film interposed therebetween, and the multilayer film has a shape having a first angle between a lower surface of the oxide semiconductor film and a side surface of the oxide semiconductor film, and a second angle between the lower surface of the oxide film and the side surface of the oxide film, and the first angle is smaller than the second angle and is an acute angle.

In the above semiconductor device, the multilayer film has an upper portion of the oxide semiconductor film and a lower portion of the oxide film that are almost aligned. In addition, the multilayer film may have an oxide film laminated on top of the oxide semiconductor film, or may have oxide films laminated above and below the oxide semiconductor film.

In the above semiconductor device, the first angle and the second angle are preferably 10° or more and less than 90°.

In the semiconductor device, it is preferable that the oxide film contains elements common to the oxide semiconductor film, and furthermore, that the energy of the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor film. For example, the oxide semiconductor film and the oxide film are In-M-Zn oxide (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Nd), and it is preferable that the oxide film has a lower atomic ratio of In to M than that of the oxide semiconductor film.

In the above semiconductor device, it is preferable that the oxide film is amorphous, the oxide semiconductor film is crystalline, and the c-axis of the crystal part included in the oxide semiconductor film is parallel to the normal vector of the surface of the oxide semiconductor film.

In the above semiconductor device, the source electrode and the drain electrode are formed in contact with the multilayer film, and a low-resistance region is formed in a region near the interface where the source electrode and the drain electrode of the multilayer film are in contact.

In addition, the semiconductor device may have an oxide film having the same composition as or a different composition from the oxide film formed on the upper surface of the source electrode and the drain electrode and the multilayer film.

According to one embodiment of the present invention, stable electrical characteristics can be imparted to a transistor by using a multilayer film including an oxide film and an oxide semiconductor film.

In addition, by forming the shape of the multilayer film into a tapered shape having at least a first angle and a second angle greater than the first angle, the contact area between the oxide semiconductor film, which becomes the channel region, and the source electrode and the drain electrode can be increased, and the on-state current of the transistor can be increased.

In addition, by one embodiment of the present invention, a highly reliable semiconductor device having the transistor can be provided.

Figure 1 is a top view and cross-sectional view illustrating a transistor.
Figure 2 is a cross-sectional diagram illustrating a transistor.
Figure 3 is a drawing explaining the band structure of a multilayer film.
Figure 4 is a drawing explaining the band structure of a multilayer film.
Figure 5 is a cross-sectional view illustrating a method of manufacturing a transistor.
Figure 6 is a cross-sectional view illustrating a method of manufacturing a transistor.
Figure 7 is a top view and a cross-sectional view illustrating a transistor.
Figure 8 is a top view and a cross-sectional view illustrating a transistor.
Figure 9 is a cross-sectional diagram illustrating a transistor.
Figure 10 is a drawing explaining the band structure of a multilayer film.
Figure 11 is a cross-sectional view illustrating a method of manufacturing a transistor.
Figure 12 is a cross-sectional view illustrating a method of manufacturing a transistor.
Figure 13 is a top view and cross-sectional view illustrating a transistor.
Figure 14 is a top view and cross-sectional view illustrating a transistor.
Fig. 15 is a circuit diagram showing an example of an EL display device.
Fig. 16 is a top view and a cross-sectional view showing an example of an EL display device.
Fig. 17 is a cross-sectional view showing an example of an EL display device.
Fig. 18 is a circuit diagram showing an example of a liquid crystal display device.
Fig. 19 is a cross-sectional view showing an example of a liquid crystal display device.
Fig. 20 is a block diagram showing an example of a semiconductor device.
Fig. 21 is a cross-sectional view showing an example of a semiconductor device.
Figure 22 is a block diagram showing an example of a CPU.
Fig. 23 is a drawing showing an example of an electronic device.
Figure 24 is a drawing explaining the relationship between etching solution and etching rate.
Figure 25 is a drawing explaining the STEM image.
Figure 26 is a drawing explaining the STEM image.
Figure 27 is a drawing explaining the STEM image.
Figure 28 is a drawing explaining the STEM image.
Figure 29 is a drawing explaining the STEM image.
Figure 30 is a drawing explaining the STEM award.
Figure 31 is a drawing explaining the structure of a multilayer film.
Figure 32 is a drawing explaining the structure of a multilayer film.

Hereinafter, embodiments of the present invention will be described in detail using drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be changed in various ways. In addition, the present invention is not interpreted as being limited to the description of the embodiments shown below. In addition, when explaining the configuration of the invention using drawings, symbols indicating the same elements are used in common even among different drawings. In addition, when indicating the same elements, the hatch pattern is the same and there are cases where no symbols are specifically attached.

The ordinal numbers 1 and 2 are used for convenience and do not indicate the order of the process or the order of stacking. In addition, they do not indicate a unique name as a matter for specifying the invention in this specification.

Also, voltage often represents the difference in potential between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). Therefore, voltage can be rephrased as potential.

Also, even when it is expressed as "electrically connected," in real circuits, there are cases where there is no physical connection and only extended wiring.

In addition, the functions of the source and drain may change, for example, when the direction of the current changes in circuit operation. Accordingly, in this specification, the terms source and drain may be used interchangeably.

In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, a case of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, a case of 85° or more and 95° or less is also included.

Additionally, in this specification, if the crystal is a trigonal crystal or a rhombohedral crystal, it is expressed as a hexagonal crystal system.

In addition, in this specification and the like, the configurations and contents described in each embodiment and each example can be appropriately combined.

(Embodiment 1)

In this embodiment, a transistor, which is one form of the present invention, is described.

1-1. Transistor structure (1)

In Fig. 1, a top view and a cross-sectional view of a transistor having a BGTC structure are shown. Fig. 1(A) shows a top view of the transistor. In Fig. 1(A), a cross-sectional view corresponding to the dashed-dotted line A1-A2 is shown in Fig. 1(B). In addition, in Fig. 1(A), a cross-sectional view corresponding to the dashed-dotted line A3-A4 is shown in Fig. 1(C). In addition, in Fig. 1(A), some of the components of the transistor (such as a gate insulating film and a protective insulating film) are omitted for clarity of the drawing.

In this embodiment, a bottom-gate type transistor is described. Here, a transistor having a bottom-gate top contact structure (BGTC structure), which is a type of bottom-gate type transistor, is described using FIG. 1. The transistor shown in FIG. 1(B) has a multilayer film (106) including a gate electrode (104) formed on a substrate (100), a gate insulating film (112) formed on the gate electrode (104), an oxide semiconductor film (106a) formed on the gate insulating film (112), and an oxide film (106b) formed on the oxide semiconductor film (106a), a source electrode (116a) and a drain electrode (116b) formed on the gate insulating film (112) and the multilayer film (106), and a protective insulating film (118) formed on the multilayer film (106), the source electrode (116a), and the drain electrode (116b).

In addition, depending on the type of conductive film used for the source electrode (116a) and the drain electrode (116b), there are cases where oxygen is taken from a part of the multilayer film (106) or a mixed layer is formed to form a low-resistance region (106c) and a low-resistance region (106d) within the multilayer film (106). In Fig. 1(B), the low-resistance region (106c) and the low-resistance region (106d) are regions near the interface where the source electrode (116a) and the drain electrode (116b) are in contact with each other within the multilayer film (106) (regions between the broken lines of the multilayer film (106) and the source electrode (116a) and the drain electrode (116b)). Part or all of the low-resistance region (106c) and the low-resistance region (106d) function as the source region and the drain region.

In Fig. 1(A), the distance between the source electrode (116a) and the drain electrode (116b) in the region overlapping with the gate electrode (104) is referred to as the channel length. However, when the transistor includes a source region and a drain region, the distance between the low-resistance region (106c) and the low-resistance region (106d) in the region overlapping with the gate electrode (104) may also be referred to as the channel length.

In addition, the channel formation region refers to a region in the multilayer film (106) that overlaps with the gate electrode (104) or is sandwiched between the source electrode (116a) and the drain electrode (116b) (see Fig. 1(B)). In addition, the channel region refers to a region in the channel formation region through which current mainly flows. Here, the channel region is a part of the oxide semiconductor film (106a) within the channel formation region.

In addition, the gate electrode (104) is formed so that the multilayer film (106) is included on the inside in the top surface shape, as shown in Fig. 1(A). By doing so, when light is incident from the substrate (100) side, it is possible to suppress the generation of carriers by light within the multilayer film (106). That is, the gate electrode (104) has a function as a light-shielding film. However, the multilayer film (106) may be formed up to the outside of the gate electrode (104).

The lower surface of the oxide semiconductor film (106a) corresponds to the surface of the oxide semiconductor film (106a) on the substrate (100) side, or the surface of the oxide semiconductor film (106a) that contacts the gate insulating film (112). The lower surface of the oxide film (106b) corresponds to the surface of the oxide film (106b) on the substrate (100) side, or the boundary surface of the oxide film (106b) with the oxide semiconductor film (106a). In addition, the boundary of the stacked structure of the multilayer film (106) can be confirmed by observing it using STEM (Scanning Transmission Electron Microscopy). However, depending on the materials used for the oxide semiconductor film (106a) and the oxide film (106b), there are cases where this boundary cannot be clearly confirmed.

1-1-1. About multilayer films

Below, the multilayer film (106) and the oxide semiconductor film (106a) and oxide film (106b) constituting the multilayer film (106) will be described using FIG. 1 and FIG. 2.

Figure 2 is an enlarged view of the area surrounded by the dashed line in Figure 1(B).

In the multilayer film (106), at least the oxide semiconductor film (106a) has a tapered shape. Preferably, the oxide film (106b) also has a tapered shape. In addition, the tapered shape of the oxide semiconductor film (106a) is different from the tapered shape of the oxide film (106b).

Specifically, in the oxide semiconductor film (106a), when the angle between the lower surface of the oxide semiconductor film (106a) and the side surface of the oxide semiconductor film (106a) is set as the first angle (θ1), and in the oxide film (106b), when the angle between the lower surface of the oxide film (106b) and the side surface of the oxide film (106b) is set as the second angle (θ2), the first angle (θ1) can be an acute angle, and the second angle (θ2) can be an acute angle or a vertical angle.

In particular, both the first angle (θ1) and the second angle (θ2) are acute angles, and it is preferable that the first angle (θ1) is smaller than the second angle (θ2).

In addition, it is preferable that the first angle (θ1) is 10° or more and less than 90°, and 30° or more and 70° or less. It is preferable that the second angle (θ2) is 10° or more and less than 90°, and 30° or more and 70° or less.

In this way, by forming the multilayer film (106) into a tapered shape having a different taper angle, the following effects can be obtained. For the multilayer film (106), by forming it into a tapered shape having a different taper angle compared to a tapered shape having a constant taper angle, the contact area with the source electrode (116a) and the drain electrode (116b) can be expanded. Accordingly, the contact resistance between the multilayer film (106) and the source electrode (116a) and the drain electrode (116b) is reduced, so that the on current of the transistor can be increased.

In addition, by making the second angle (θ2) larger than the first angle (θ1), the contact area between the oxide film (106b) and the source electrode (116a) and the drain electrode (116b) can be reduced, and the low-resistance region formed in the oxide film (106b) can be reduced. As a result, while suppressing the low resistance of the oxide film (106b) and suppressing the occurrence of a leak path between the source electrode (116a) and the drain electrode (116b), a low-resistance region can be effectively formed in the oxide semiconductor film (106a) functioning as a channel region, and both an increase in the on-current of the transistor and a decrease in the off-current of the transistor can be achieved.

In addition, the upper end of the oxide semiconductor film (106a) almost coincides with the lower end of the oxide film (106b) (see FIG. 2). That is, the multilayer film (106) does not have a large step (113) formed by the oxide semiconductor film (106a) and the oxide film (106b) (see FIG. 31(A) and FIG. 31(B)). Therefore, it is possible to suppress the breakup of the end of the film formed on the multilayer film (106) (for example, the conductive film processed into the source electrode (116a) and the drain electrode (116b)), and it is possible to manufacture a transistor having good electrical characteristics. In addition, the fact that the upper part of the oxide semiconductor film (106a) and the lower part of the oxide semiconductor film (106b) almost coincide with each other means that the distance (L1) between the lower part of the oxide film (106b) and the upper part of the oxide semiconductor film (106a) is 30 nm or less, preferably 10 nm or less (see FIG. 31(A) and FIG. 31(B)).

The above-mentioned tapered shape can be formed by utilizing the fact that the etching rates of the oxide semiconductor film (106a) and the oxide film (106b) are different when forming the multilayer film (106) by etching. In particular, the above-mentioned tapered shape can be formed by making the etching rate of the oxide semiconductor film (106a) slower than the etching rate of the oxide film (106b).

The above tapered shape can be formed, for example, by wet etching using a solution containing phosphoric acid as an etchant.

The advantages of forming the multilayer film (106) by wet etching include the following. For example, if the oxide semiconductor film and oxide film processed into the multilayer film (106) have defects such as pinholes, when the oxide semiconductor film and oxide film are processed by dry etching, the insulating film (such as a gate insulating film) formed under the oxide semiconductor film and oxide film may also be etched through the pinholes. As a result, an opening may be formed in the insulating film that leads to the electrode (such as a gate electrode) formed under the insulating film. When a transistor is manufactured under such circumstances, there are cases where a transistor with poor characteristics is manufactured, such as a short circuit between the electrode and the electrode (such as a source electrode and a drain electrode) formed on the multilayer film (106). In other words, forming the multilayer film (106) by dry etching leads to a decrease in the yield of the transistor. Therefore, by forming a multilayer film (106) by wet etching, a transistor with good electrical characteristics can be manufactured with high productivity.

In addition, since the etching speed of wet etching varies depending on the concentration of the corrosive solution, the temperature of the corrosive solution, etc., it is preferable to appropriately adjust the etching speed of the oxide semiconductor film (106a) to be slower than the etching speed of the oxide film (106b). In addition, by making the second angle (θ2) larger than the first angle (θ1), the area exposed to the corrosive solution in this wet etching can be made as small as possible. In addition, by making the second angle (θ2) larger than the first angle (θ1), the low-resistance region formed in the oxide film (106b) due to contamination by the corrosive solution or the creation of defects can be made small.

For example, a phosphoric acid aqueous solution adjusted to about 85% as the above-mentioned etchant, or a mixed solution (also called mixed aluminum acid solution) of phosphoric acid (72%), nitric acid (2%), and acetic acid (9.8%) can be mentioned. In addition, the temperature of the etchant is preferably room temperature or ambient temperature of about 20℃ to 35℃. In addition, the etchant may be a solution other than the above-mentioned.

The oxide semiconductor film (106a) is an oxide semiconductor film that contains at least indium. For example, it may contain zinc in addition to indium. In addition, it is preferable that the oxide semiconductor film (106a) contains, in addition to indium, an element M (M is Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Nd).

The oxide film (106b) is composed of one or more elements constituting the oxide semiconductor film (106a), and is an oxide film close to a vacuum level whose energy at the bottom of the conduction band is 0.05 eV or higher, 0.07 eV or higher, 0.1 eV or higher, or 0.15 eV or higher, or 2 eV or lower, 1 eV or lower, 0.5 eV or lower, or 0.4 eV or lower than that of the oxide semiconductor film (106a). At this time, when an electric field is applied to the gate electrode (104), a channel is formed in the oxide semiconductor film (106a) among the multilayer films (106) having a lower energy at the bottom of the conduction band. That is, by having the oxide film (106b) between the oxide semiconductor film (106a) and the protective insulating film (118), the channel of the transistor can be formed in the oxide semiconductor film (106a) that is not in contact with the protective insulating film (118). In addition, since the oxide film (106b) is composed of one or more elements constituting the oxide semiconductor film (106a), it is difficult for interfacial scattering to occur between the oxide semiconductor film (106a) and the oxide film (106b). Therefore, since the movement of carriers is not impeded between the oxide semiconductor film (106a) and the oxide film (106b), the field effect mobility of the transistor is increased. In addition, it is difficult to form an interfacial state between the oxide semiconductor film (106a) and the oxide film (106b). If an interfacial state exists between the oxide semiconductor film (106a) and the oxide film (106b), a second transistor having a different threshold voltage using this interface as a channel is formed, and there are cases where the apparent threshold voltage of the transistor fluctuates. Therefore, by forming the oxide film (106b), it is possible to reduce variation in electrical characteristics such as the threshold voltage of the transistor.

The oxide film (106b) may be an oxide film containing, for example, Al, Ga, Ge, Y, Zr, Sn, La, Ce, Nd or Hf (particularly Al or Ga) at a higher atomic ratio than the oxide semiconductor film (106a). Specifically, an oxide film containing the above-described elements at a higher atomic ratio of 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more than the oxide semiconductor film (106a) is used as the oxide film (106b). Since the above-described elements strongly bind to oxygen, they have a function of suppressing the occurrence of oxygen vacancies in the oxide film. In other words, the oxide film (106b) is an oxide film in which oxygen vacancies are less likely to occur than the oxide semiconductor film (106a).

For example, when the oxide semiconductor film (106a) is an In-M-Zn oxide and the oxide film (106b) is also an In-M-Zn oxide, and when the oxide film (106b) has an In:M:Zn=x ₂ :y ₂ :z ₂ [atomic ratio] and the oxide semiconductor film (106a) has an In:M:Zn=x ₁ :y ₁ :z ₁ [atomic ratio], the oxide film (106b) and the oxide semiconductor film (106a) in which y ₁ /x ₁ becomes larger than y ₂ /x ₂ are selected. In addition, the element M is a metal element having a stronger bonding force with oxygen than In, and examples thereof include Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Nd (especially Al or Ga). Preferably, an oxide film (106b) and an oxide semiconductor film (106a) in which y ₁ /x ₁ becomes 1.5 times or more larger than y ₂ /x ₂ are selected. More preferably, an oxide film (106b) and an oxide semiconductor film (106a) in which y ₁ /x ₁ becomes 2 times or more larger than y 2 /x 2 are selected. More preferably, an oxide film (106b) and an oxide semiconductor film (106a) in which y ₁ / _{x 1} becomes 3 times or _more larger than y ₂ /x ₂ are selected. At this time, in the oxide film (106b), it is preferable that y ₂ be x ₂ or more because this can provide stable electrical characteristics to the transistor. However, if y ₂ is 3 times or more larger than x ₂ , the field effect mobility of the transistor deteriorates, so it is preferable that y ₂ be less than 3 times x ₂ .

In addition, if the oxide film (106b) is dense, it is difficult for it to be damaged by plasma or the like used in the transistor manufacturing process, and it is preferable because it can be made into a transistor with stable electrical characteristics.

The thickness of the oxide film (106b) is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. In addition, the thickness of the oxide semiconductor film (106a) is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

Hereinafter, the silicon concentration of the oxide semiconductor film (106a) and the oxide film (106b) will be described. In addition, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor film (106a) and make the oxide semiconductor film intrinsic or substantially intrinsic. Specifically, the carrier density of the oxide semiconductor film may be less than 1×10 ¹⁷ /cm ³ , less than 1×10 ¹⁵ /cm ³ , or less than 1×10 ¹³ /cm ³ . In addition, in the oxide semiconductor film, light elements, semimetal elements, metal elements, etc. other than the main component (less than 1 atomic%) become impurities. For example, hydrogen, nitrogen, carbon, silicon, germanium, titanium, and hafnium become impurities in the oxide semiconductor film. In order to reduce the impurity concentration in the oxide semiconductor film, it is preferable to also reduce the impurity concentrations in the adjacent gate insulating film (112) and the oxide film (106b).

For example, when silicon is included in the oxide semiconductor film (106a), an impurity level is formed. In particular, when silicon exists between the oxide semiconductor film (106a) and the oxide film (106b), this impurity level becomes a trap. Therefore, the silicon concentration between the oxide semiconductor film (106a) and the oxide film (106b) is set to less than 1×10 ¹⁹ atoms/cm ³ , preferably less than 5×10 ¹⁸ atoms/cm ³ , and more preferably less than 2×10 ¹⁸ atoms/cm ³ .

In addition, hydrogen and nitrogen form donor levels in the oxide semiconductor film (106a), thereby increasing the carrier density. The hydrogen concentration of the oxide semiconductor film (106a) is set to 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, and even more preferably 5×10 ¹⁸ atoms/cm ³ or less in secondary ion mass spectrometry (SIMS). In addition, the nitrogen concentration is set to less than 5×10 ¹⁹ atoms/cm ³ in SIMS, preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and even more preferably 5×10 ¹⁷ atoms/cm ³ or less.

In addition, in order to reduce the hydrogen concentration and nitrogen concentration of the oxide semiconductor film (106a), it is preferable to reduce the hydrogen concentration and nitrogen concentration of the oxide film (106b). The hydrogen concentration of the oxide film (106b) is set to 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, and even more preferably 5×10 ¹⁸ atoms/cm ³ or less in SIMS. In addition, the nitrogen concentration is set to less than 5×10 ¹⁹ atoms/cm ³ in SIMS, preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and even more preferably 5×10 ¹⁷ atoms/cm ³ or less.

The oxide semiconductor film (106a) and the oxide film (106b) are amorphous or crystalline. Examples of the crystalline structure include a polycrystalline structure, a single crystal structure, and a microcrystalline structure. In addition, the oxide semiconductor film (106a) and the oxide film (106b) may have a mixed structure in which crystal grains are dispersed in an amorphous region. In addition, the microcrystalline structure means that the plane orientation of each crystal grain is random, and the grain size of the crystal grains included in the microcrystalline structure or the mixed structure is 0.1 nm or more and 10 nm or less, preferably 1 nm or more and 10 nm or less, and more preferably 2 nm or more and 4 nm or less.

Regarding the oxide semiconductor film (106a) and the oxide film (106b), preferably, the oxide semiconductor film (106a) is crystalline and the oxide film (106b) is amorphous or crystalline. Since the oxide semiconductor film (106a) in which the channel is formed is crystalline, stable electrical characteristics can be provided to the transistor. In addition, the crystalline oxide semiconductor film (106a) is preferably CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor).

In addition, it is preferable that the oxide semiconductor film (106a) be formed on an amorphous film. For example, on the surface of an amorphous insulating film, or on the surface of an amorphous semiconductor film, etc. By using the film formation method described below, the oxide semiconductor film (106a) which is a CAAC-OS can be formed on the amorphous film.

A CAAC-OS film is a type of oxide semiconductor film having multiple crystal portions, and most of the crystal portions are sized to fit within a cube with a side of less than 100 nm. Therefore, crystal portions included in the CAAC-OS film also include cases where they fit within a cube with a side of less than 10 nm, less than 5 nm, or less than 3 nm. The CAAC-OS film has the characteristic of having a low defect state density. Hereinafter, the CAAC-OS film will be described in detail.

When a CAAC-OS film is observed by TEM, a clear boundary between crystal parts, that is, a grain boundary (also called a grain boundary) cannot be confirmed. Therefore, it can be said that a CAAC-OS film is unlikely to experience a decrease in electron mobility due to grain boundaries.

When a CAAC-OS film is observed by TEM in a direction roughly parallel to the sample plane (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape that reflects the unevenness of the plane forming the CAAC-OS film (also called the formation plane) or the upper surface, and is arranged parallel to the formation plane or the upper surface of the CAAC-OS film.

Meanwhile, when the CAAC-OS film is observed by TEM in a direction roughly perpendicular to the sample plane (planar TEM observation), it can be confirmed that the metal atoms are arranged in a triangular or hexagonal shape in the crystal parts. However, there is no regularity in the arrangement of the metal atoms between different crystal parts.

From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has an orientation.

When a structural analysis of a CAAC-OS film is performed using an X-ray diffraction (XRD) device, for example, in the out-of-plane analysis of a CAAC-OS film having an InGaZnO ₄ crystal, a peak may appear at a diffraction angle (2θ) of around 31°. Since this peak is assigned to the (009) plane of the InGaZnO ₄ crystal, it can be confirmed that the crystal of the CAAC-OS film has a c-axis orientation, and that the c-axis is directed in a direction approximately perpendicular to the formation plane or the upper surface.

Meanwhile, in the analysis by the in-plane method in which X-rays are incident in a direction approximately perpendicular to the c-axis for the CAAC-OS film, a peak may appear at around 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed at around 56° and the sample is rotated with the normal vector of the sample plane as the axis (φ-axis) while performing analysis (φ-scan), six peaks attributed to a crystal plane equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no clear peak appears even when φ-scan is performed while fixing 2θ at around 56°.

From the above, it can be seen that in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has a c-axis orientation, and further, the c-axis points in a direction parallel to the normal vector of the formation plane or the upper surface. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the cross-sectional TEM observation described above is a plane parallel to the ab-plane of the crystal.

In addition, the crystal portion is formed when the CAAC-OS film is deposited or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation plane or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation plane or the upper surface of the CAAC-OS film.

In addition, the crystallinity within the CAAC-OS film need not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the top surface of the CAAC-OS film, the region near the top surface may have a higher crystallinity than the region near the formation surface. In addition, when an impurity is added to the CAAC-OS film, the crystallinity of the region to which the impurity is added may change, and a region having a different crystallinity may be formed partially.

In addition, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by the out-of-plane method, in addition to the peak at around 2θ of 31°, there are cases where a peak appears at around 2θ of 36°. The peak at around 2θ of 36° indicates that some parts of the CAAC-OS film contain crystals that do not have c-axis alignment. It is preferable that the CAAC-OS film exhibit a peak at around 2θ of 31° and not exhibit a peak at around 2θ of 36°.

Transistors using CAAC-OS have small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, these transistors have stable electrical characteristics.

In addition, since silicon and carbon are included in a high concentration in the oxide semiconductor film (106a), there are cases where the crystallinity of the oxide semiconductor film (106a) is lowered. In order not to lower the crystallinity of the oxide semiconductor film (106a), the silicon concentration of the oxide semiconductor film (106a) is preferably less than 1×10 ¹⁹ atoms/cm ³ , preferably less than 5×10 ¹⁸ atoms/cm ³ , more preferably less than 2×10 ¹⁸ atoms/cm ³ . In addition, in order not to lower the crystallinity of the oxide semiconductor film (106a), the carbon concentration of the oxide semiconductor film (106a) is preferably less than 1×10 ¹⁹ atoms/cm ³ , preferably less than 5×10 ¹⁸ atoms/cm ³ , more preferably less than 2×10 ¹⁸ atoms/cm ³ .

In this way, when the oxide semiconductor film (106a) in which the channel is formed has high crystallinity or has few levels caused by impurities or defects, a transistor using the multilayer film (106) has stable electrical characteristics.

Hereinafter, the local state level within the multilayer film (106) will be described. By reducing the local state level within the multilayer film (106), stable electrical characteristics can be provided to a transistor using the multilayer film (106). The local state level of the multilayer film (106) can be evaluated by the constant photocurrent measurement method (CPM: Constant Photocurrent Method).

In order to provide stable electrical characteristics to the transistor, it is preferable that the absorption coefficient due to the local level obtained by the CPM measurement within the multilayer film (106) be less than 1×10 ^-3 cm ^-1 , preferably less than 3×10 ^-4 cm ^-1 . In addition, by setting the absorption coefficient due to the local level obtained by the CPM measurement within the multilayer film (106) to less than 1×10 ^-3 cm ^-1 , preferably less than 3×10 ^-4 cm ^-1 , the field effect mobility of the transistor can be increased. In addition, in order to make the absorption coefficient by the local level that can be obtained by the CPM measurement in the multilayer film (106) less than 1×10 ^-3 cm ^-1 , preferably less than 3×10 ^-4 cm ^-1 , the concentration of elements forming the local level in the oxide semiconductor film (106a), such as silicon, germanium, carbon, hafnium, and titanium, is preferably made less than 2×10 ¹⁸ atoms/cm ³ , preferably less than 2×10 ¹⁷ atoms/cm ³ .

In addition, in the CPM measurement, the amount of light irradiated on the sample surface between the terminals is adjusted so that the photocurrent value becomes constant while applying voltage between the electrodes formed in contact with the multilayer film (106) as the sample, and the absorption coefficient is derived from the amount of irradiated light at each wavelength. In the CPM measurement, when there is a defect in the sample, the absorption coefficient increases in energy (converted from wavelength) according to the level at which the defect exists. By multiplying the increase in this absorption coefficient by an integer, the defect density of the sample can be derived.

It is thought that the local level obtained by CPM measurement is a level caused by impurities or defects. That is, it can be seen that a transistor using a multilayer film (106) having a small absorption coefficient by the local level obtained by CPM measurement has stable electrical characteristics.

Below, the band structure of the multilayer film (106) is explained using Fig. 3.

As an example, In-Ga-Zn oxide having an energy gap of 3.15 eV is used as the oxide semiconductor film (106a), and In-Ga-Zn oxide having an energy gap of 3.5 eV is used as the oxide film (106b). The energy gaps were measured using a spectroscopic ellipsometer (UT-300, manufactured by HORIBA JOBIN YVON).

The energy differences (also called ionization potentials) between the vacuum level and the top of the valence band of the oxide semiconductor film (106a) and the oxide film (106b) were 8 eV and 8.2 eV, respectively. In addition, the energy differences between the vacuum level and the top of the valence band were measured using an ultraviolet photoelectron spectroscopy (UPS) device (PHI VersaProbe).

Therefore, the energy difference (also called electron affinity) between the vacuum level and the bottom of the conduction band of the oxide semiconductor film (106a) and the oxide film (106b) was 4.85 eV and 4.7 eV, respectively.

In Fig. 3, a part of the band structure of the multilayer film (106) is schematically illustrated. Fig. 3 is a band structure corresponding to the dashed-dotted line A5-A6 of Fig. 2. Specifically, a case will be described where an oxide semiconductor film (106a) and an oxide film (106b) are each formed by contacting a silicon oxide film (gate insulating film (112) and a protective insulating film (118)). Here, EcI1 represents the energy of the bottom of the conduction band of the silicon oxide film, EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor film (106a), EcS2 represents the energy of the bottom of the conduction band of the oxide film (106b), and EcI2 represents the energy of the bottom of the conduction band of the silicon oxide film.

As illustrated in Fig. 3, in the oxide semiconductor film (106a) and the oxide film (106b), the energy at the bottom of the conduction band changes gradually without a barrier. In other words, it can be said that it changes continuously. This can be said to be because the oxide film (106b) contains elements common to the oxide semiconductor film (106a), and a mixed layer is formed between the oxide semiconductor film (106a) and the oxide film (106b) as oxygen moves to each other.

By Fig. 3, it can be seen that the oxide semiconductor film (106a) of the multilayer film (106) becomes a well, and in a transistor using the multilayer film (106), a channel region is formed in the oxide semiconductor film (106a). In addition, since the energy at the bottom of the conduction band of the multilayer film (106) is continuously changing, it can also be said that the oxide semiconductor film (106a) and the oxide film (106b) are continuously connected.

In addition, as illustrated in Fig. 4, a trap level due to an impurity or defect may be formed near the interface between the oxide film (106b) and the protective insulating film (118), but by forming the oxide film (106b), the oxide semiconductor film (106a) can be separated from this trap level. However, when the energy difference between EcS1 and EcS2 is small, there are cases where electrons in the oxide semiconductor film (106a) exceed this energy difference and reach the trap level. By capturing electrons at the trap level, negative fixed charges are generated at the insulating film interface, and the threshold voltage of the transistor shifts in the positive direction.

Therefore, it is desirable to make the energy difference between EcS1 and EcS2 0.1 eV or more, preferably 0.15 eV or more, because this reduces fluctuations in the threshold voltage of the transistor and stabilizes electrical characteristics.

1-1-2. Source electrode and drain electrode

The source electrode (116a) and the drain electrode (116b) can use a conductive film containing one or more kinds of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten, as a single layer or as a laminate. Preferably, the source electrode (116a) and the drain electrode (116b) are formed as a multilayer film having a layer containing copper. By using a multilayer film having a layer containing copper as the source electrode (116a) and the drain electrode (116b), when forming wiring in the same layer as the source electrode (116a) and the drain electrode (116b), the wiring resistance can be reduced. In addition, the source electrode (116a) and the drain electrode (116b) may have the same composition or different compositions.

However, in the case where a multilayer film having a layer containing copper is used as the source electrode (116a) and the drain electrode (116b), there are cases where a trap level as shown in Fig. 4 is formed at the interface between the oxide film (106b) and the protective insulating film (118) due to the influence of copper. In this case as well, by having the oxide film (106b), it is possible to suppress electrons from being captured at this trap level. Accordingly, it is possible to provide the transistor with stable electrical characteristics and also to reduce the wiring resistance.

1-1-3. Protective insulation film

The protective insulating film (118) may be formed as a single layer or in a laminated manner and may include one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.

The protective insulating film (118) may be a multilayer film, for example, in which the first layer is a silicon oxide film and the second layer is a silicon nitride film. In this case, the silicon oxide film may be a silicon oxynitride film. Furthermore, the silicon nitride film may be a silicon nitride oxide film. It is preferable to use a silicon oxide film having a small defect density as the silicon oxide film. Specifically, a silicon oxide film having a spin density derived from a signal having a g value of 2.001 in electron spin resonance (ESR) of 3×10 ¹⁷ spins/cm ³ or less, preferably 5×10 ¹⁶ spins/cm ³ or less, is used. The silicon nitride film uses a silicon nitride film having a small amount of hydrogen gas and ammonia gas released. The amount of hydrogen gas and ammonia gas released may be measured by thermal desorption spectroscopy (TDS) analysis. In addition, a silicon nitride film is used that is impermeable or nearly impermeable to hydrogen, water, and oxygen.

In addition, the protective insulating film (118) may be a multilayer film, for example, in which the first layer is a first silicon oxide film (118a), the second layer is a second silicon oxide film (118b), and the third layer is a silicon nitride film (118c) (see Fig. 1(D)). In this case, one or both of the first silicon oxide film (118a) and the second silicon oxide film (118b) may be silicon oxynitride films. In addition, the silicon nitride film may be a silicon nitride oxide film. It is preferable to use a silicon oxide film having a small defect density as the first silicon oxide film (118a). Specifically, a silicon oxide film having a spin density derived from a signal having a g value of 2.001 in ESR is used, of 3×10 ¹⁷ spins/cm ³ or less, preferably 5×10 ¹⁶ spins/cm ³ or less. The second silicon oxide film (118b) uses a silicon oxide film containing excess oxygen. The silicon nitride film (118c) uses a silicon nitride film that emits little hydrogen gas and ammonia gas. In addition, the silicon nitride film uses a silicon nitride film that does not permeate hydrogen, water, and oxygen, or that hardly permeates hydrogen, water, and oxygen.

A silicon oxide film containing excess oxygen refers to a silicon oxide film that can release oxygen through heat treatment, etc. In addition, an insulating film containing excess oxygen is an insulating film that has the function of releasing oxygen through heat treatment.

An insulating film containing excess oxygen can reduce oxygen vacancies in the oxide semiconductor film (106a). Oxygen vacancies in the oxide semiconductor film (106a) form defect levels, some of which become donor levels. Therefore, by reducing oxygen vacancies in the oxide semiconductor film (106a) (particularly oxygen vacancies in the channel region), the carrier density of the oxide semiconductor film (106a) (particularly in the channel region) can be reduced, and stable electrical characteristics can be provided to the transistor.

Here, the film that releases oxygen by heat treatment may release oxygen (converted to the number of oxygen atoms) of 1×10 ¹⁸ atoms/cm ³ or more, 1×10 ¹⁹ atoms/cm ³ or more, or 1×10 ²⁰ atoms/cm ³ or more, as measured by TDS analysis.

In addition, a film that releases oxygen by heat treatment may contain peroxide radicals. Specifically, it refers to a film having a spin density of 5×10 ¹⁷ spins/cm ³ or more due to peroxide radicals. In addition, a film containing peroxide radicals may have an asymmetric signal in the ESR at a g value of around 2.01.

In addition, the insulating film containing excess oxygen may be oxygen-excess silicon oxide (SiO _X (X>2)). Oxygen-excess silicon oxide (SiO _X (X>2)) contains oxygen atoms more than twice the number of silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by Rutherford Backscattering Spectrometry (RBS).

1-1-4. Gate Insulator

The gate insulating film (112) may be formed as a single layer or in a laminated manner using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.

The gate insulating film may be a multilayer film, for example, in which the first layer is a silicon nitride film and the second layer is a silicon oxide film. In this case, the silicon oxide film may be a silicon oxynitride film. Furthermore, the silicon nitride film may be a silicon nitride oxide film. It is preferable to use a silicon oxide film having a small defect density as the silicon oxide film. Specifically, a silicon oxide film having a spin density derived from a signal having a g value of 2.001 in ESR of 3×10 ¹⁷ spins/cm ³ or less, preferably 5×10 ¹⁶ spins/cm ³ or less, is used. It is preferable to use a silicon oxide film containing excess oxygen as the silicon oxide film. The silicon nitride film uses a silicon nitride film that emits little hydrogen gas and ammonia gas. The emission amounts of hydrogen gas and ammonia gas can be measured by TDS analysis.

When at least one of the gate insulating film (112) and the protective insulating film (118) includes an insulating film containing excess oxygen, oxygen vacancies in the oxide semiconductor film (106a) are reduced, and stable electrical characteristics can be provided to the transistor.

1-1-5. Gate electrode

The gate electrode (104) may be formed using a conductive film containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten, either as a single layer or in a laminated form.

1-1-6. Substrate

There is no major limitation on the substrate (100). For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate (100). In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI (Silicon On Insulator) substrate, etc. may be applied, and a substrate on which a semiconductor element is formed may be used as the substrate (100).

In addition, when a large glass substrate such as a 5th generation (1000 mm x 1200 mm or 1300 mm x 1500 mm), 6th generation (1500 mm x 1800 mm), 7th generation (1870 mm x 2200 mm), 8th generation (2200 mm x 2500 mm), 9th generation (2400 mm x 2800 mm), or 10th generation (2880 mm x 3130 mm) is used as the substrate (100), fine processing may become difficult due to shrinkage of the substrate (100) caused by heat treatment, etc. in the manufacturing process of the semiconductor device. Therefore, when a large glass substrate such as the one described above is used as the substrate (100), it is preferable to use one whose shrinkage due to heat treatment is small. For example, it is preferable to use a large glass substrate (100) having a shrinkage of 10 ppm or less, preferably 5 ppm or less, more preferably 3 ppm or less after heat treatment at a temperature of 400°C, preferably 450°C, more preferably 500°C for 1 hour.

In addition, it is also acceptable to use a flexible substrate as the substrate (100). In addition, as a method of forming a transistor on a flexible substrate, there is also a method of manufacturing a transistor on a non-flexible substrate, then peeling off the transistor and transferring it to the substrate (100), which is a flexible substrate. In that case, it is preferable to form a peeling layer between the non-flexible substrate and the transistor.

The transistor configured as described above has stable electrical characteristics and high field-effect mobility because a channel is formed in the oxide semiconductor film (106a). In addition, even if a multilayer film having a layer containing copper is used for the source electrode (116a) and the drain electrode (116b), stable electrical characteristics can be obtained.

1-2. Manufacturing method of transistor structure (1)

Here, the method of manufacturing a transistor is explained using Figs. 5 and 6.

First, prepare the substrate (100).

Next, a conductive film to be the gate electrode (104) is formed. The conductive film to be the gate electrode (104) may be formed by using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, an atomic layer deposition (ALD) method, or a pulse laser deposition (PLD) method, as indicated by the gate electrode (104).

Next, a portion of the conductive film that becomes the gate electrode (104) is etched, and the gate electrode (104) is formed (see Fig. 5(A)).

Next, a gate insulating film (112) is formed (see Fig. 5(B)). The gate insulating film (112) may be formed using any of the insulating films listed above, such as a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, an oxide semiconductor film (126a) processed into an oxide semiconductor film (106a) is formed (see Fig. 5(C)). The oxide semiconductor film (126a) may be formed as an oxide semiconductor film (106a) using a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, an oxide film (126b) processed into an oxide film (106b) is formed. The oxide film (126b) may be formed as an oxide film (106b) using the above-listed oxide films by sputtering, CVD, MBE, ALD or PLD.

When forming an oxide semiconductor film (126a) and an oxide film (126b) by a sputtering method, a power supply for generating plasma can be appropriately used, such as an RF power supply, an AC power supply, or a DC power supply.

Sputtering gas is appropriately used in a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixture of noble gas and oxygen. In addition, in the case of a mixture of noble gas and oxygen, it is desirable to increase the gas ratio of oxygen to the noble gas.

In addition, the target may be appropriately selected according to the composition of the oxide semiconductor film (126a) and the oxide film (126b).

When using a sputtering method, CAAC-OS can be formed by forming at least an oxide semiconductor film (126a) as follows. Specifically, the oxide semiconductor film (126a) is formed while heating the substrate at a temperature of 150° C. or higher and 500° C. or lower, preferably 150° C. or higher and 450° C. or lower, and more preferably 200° C. or higher and 350° C. or lower. In addition, the oxide film (126b) may also be formed while heating in the same manner.

In addition, in order to continuously bond the oxide semiconductor film (106a) and the oxide film (106b), it is preferable to continuously form the oxide semiconductor film (126a) and the oxide film (126b) without exposing them to the atmosphere. In addition, the oxide semiconductor film (126a) and the oxide film (126b) can suppress impurities from entering between each layer.

Specifically, in order to form a continuous bond, it is preferable to continuously laminate each film without exposing it to the atmosphere by using a multi-chamber type film forming device (sputtering device) equipped with a load lock room. It is preferable to perform high-vacuum evacuation (about 1×10 ^-4 Pa to 5×10 -7 Pa) of each chamber in the sputtering device using an adsorption-type vacuum exhaust pump such as a cryopump in order to remove water and the like, which are impurities in the oxide semiconductor film, as ^much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas from flowing back into the chamber from the exhaust system.

In order to obtain an oxide semiconductor film with reduced impurity and carrier density, not only is the chamber evacuated to a high vacuum, but also the sputtering gas needs to be highly purified. The oxygen gas or argon gas used as the sputtering gas can be purified to a dew point of -40°C or lower, preferably -80°C or lower, and more preferably -100°C or lower, thereby preventing moisture and the like from being taken in by the oxide semiconductor film as much as possible.

In addition, when forming an oxide film (126b) by sputtering, it is preferable to use a target containing indium from the viewpoint of reducing the number of particles generated during film formation. In addition, it is preferable to use an oxide target having a relatively small atomic ratio of gallium. This is because by using a target containing indium, the conductivity of the target can be increased, and DC discharge and AC discharge become easy, making it easy to respond to a large-area substrate. Accordingly, the productivity of semiconductor devices can be increased.

In addition, after forming the oxide semiconductor film (126a) and the oxide film (126b), plasma treatment may be performed in an oxygen atmosphere or a nitrogen and oxygen atmosphere. Accordingly, at least the oxygen vacancy of the oxide semiconductor film (126a) can be reduced.

Next, a resist mask is formed over the oxide semiconductor film (126a) and the oxide film (126b), and a part of the oxide semiconductor film (126a) and the oxide film (126b) is etched using the resist mask, thereby forming a multilayer film (106) including the oxide semiconductor film (106a) and the oxide film (106b) (see Fig. 6(A)). This etching is performed by wet etching as described above. By performing this wet etching, the multilayer film (106) can be made into a tapered shape having two different taper angles.

Next, it is preferable to perform the first heat treatment. The first heat treatment may be performed at 250°C or more and 650°C or less, preferably 300°C or more and 500°C or less. The atmosphere of the first heat treatment may be an inert gas atmosphere, an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, or a reduced pressure state. Alternatively, the atmosphere of the first heat treatment may be an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to replenish the released oxygen after the heat treatment in an inert gas atmosphere. By the first heat treatment, the crystallinity of the oxide semiconductor film (106a) can be increased, and impurities such as water, hydrogen, nitrogen, and carbon can be removed from the gate insulating film (112) and the multilayer film (106).

Additionally, the first heat treatment can be performed on at least one side before or after the etching process for forming the multilayer film (106).

Next, conductive films that become the source electrode (116a) and the drain electrode (116b) are formed. The conductive films that become the source electrode (116a) and the drain electrode (116b) may be formed by using the sputtering method, the CVD method, the MBE method, the ALD method, or the PLD method, as indicated by the conductive films for the source electrode (116a) and the drain electrode (116b).

For example, it is preferable to form a multilayer film including a tungsten layer and a copper layer formed on the tungsten layer as a conductive film to be the source electrode (116a) and the drain electrode (116b).

Next, a part of the conductive film that becomes the source electrode (116a) and the drain electrode (116b) is etched, and the source electrode (116a) and the drain electrode (116b) are formed (see Fig. 6(B)). When a multilayer film including a tungsten layer and a copper layer formed on the tungsten layer is used as the conductive film that becomes the source electrode (116a) and the drain electrode (116b), the multilayer film can be etched using the same photomask. Even if the tungsten layer and the copper layer are etched at the same time, since an oxide film (106b) is formed on the oxide semiconductor film (106a), the copper concentration between the oxide semiconductor film (106a) and the oxide film (106b) can be set to less than 1×10 ¹⁹ atoms/cm ³ , less than 2×10 ¹⁸ atoms/cm ³ , or less than 2×10 ¹⁷ atoms/cm ³ , so that the electrical characteristics of the transistor are not deteriorated by copper. Therefore, the degree of freedom of the process is increased, and the productivity of the transistor can be improved.

Next, it is preferable to perform a second heat treatment. The second heat treatment may be performed with reference to the description of the first heat treatment. By the second heat treatment, impurities such as hydrogen and water can be removed from the multilayer film (106). Since hydrogen is particularly easy to move within the multilayer film (106), if it is reduced by the second heat treatment, stable electrical characteristics can be imparted to the transistor. In addition, since water is also a compound containing hydrogen, it can become an impurity within the oxide semiconductor film (106a).

In addition, by the second heat treatment, a low-resistance region (106c) and a low-resistance region (106d) can be formed in the multilayer film (106) in contact with the source electrode (116a) and the drain electrode (116b).

As described above, by forming a multilayer film (106), the crystallinity of the oxide semiconductor film (106a) can be increased, and the impurity concentration at the interface between the oxide semiconductor film (106a), the oxide film (106b), and the oxide semiconductor film (106a) and the oxide film (106b) can be reduced.

Next, a protective insulating film (118) is formed (see Fig. 1(B)). The protective insulating film (118) may be formed using any of the insulating films listed above, such as a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Here, a description will be given of a case where the protective insulating film (118) has a three-layer structure as illustrated in Fig. 1(D). First, a first silicon oxide film (118a) is formed. Next, a second silicon oxide film (118b) is formed. Next, a treatment for adding oxygen ions to the second silicon oxide film (118b) may be performed. The treatment for adding oxygen ions may be performed using an ion doping device or a plasma treatment device. As the ion doping device, an ion doping device having a mass separation function may be used. As a raw material for the oxygen ions, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, ozone gas, or the like may be used. Next, a silicon nitride film (118c) may be formed to form the protective insulating film (118).

It is preferable that the first silicon oxide film (118a) be formed by a plasma CVD method, which is a type of CVD method. Specifically, the substrate temperature is set to 180°C or more and 400°C or less, preferably 200°C or more and 370°C or less, and a deposition gas and an oxidizing gas containing silicon are used at a pressure of 20 Pa or more and 250 Pa or less, preferably 40 Pa or more and 200 Pa or less, thereby supplying high-frequency power to the electrodes to form the film. In addition, representative examples of the deposition gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

In addition, by increasing the flow rate of the oxidizing gas to 100 times or more for the sedimentary gas including silicon, the hydrogen content in the first silicon oxide film (118a) can be reduced, and dangling bonds can also be reduced.

In this manner, a first silicon oxide film (118a) having a low defect density is formed. That is, the first silicon oxide film (118a) can have a spin density derived from a signal having a g value of 2.001 in ESR of 3×10 ¹⁷ spins/cm ³ or less, or 5×10 ¹⁶ spins/cm ³ or less.

The second silicon oxide film (118b) is preferably formed by a plasma CVD method. Specifically, the film is formed by setting the substrate temperature to 160°C or more and 350°C or less, preferably 180°C or more and 260° ^C or less, using a deposition gas and an oxidizing gas containing silicon at a pressure of 100 Pa or more and 250 Pa or less, preferably 100 Pa or more and 200 Pa or less, and supplying high-frequency power of 0.17 W/cm ² or more and 0.5 W/cm 2 or less, preferably 0.25 W/cm ² or more and 0.35 W/cm ² or less to the electrode.

By the method described above, the decomposition efficiency of gas in the plasma is increased, oxygen radicals increase, and oxidation of gas progresses, so that a second silicon oxide film (118b) containing excess oxygen can be formed.

The silicon nitride film (118c) is preferably formed by a plasma CVD method. Specifically, the film is formed by supplying high-frequency power while setting the substrate temperature to 180°C or higher and 400°C or lower, preferably 200°C or higher and 370°C or lower, using a deposition gas containing silicon, nitrogen gas, and ammonia gas at a pressure of 20 Pa or higher and 250 Pa or lower, preferably 40 Pa or higher and 200 Pa or lower.

In addition, the amount of nitrogen gas is 5 to 50 times greater than the amount of ammonia gas, preferably 10 to 50 times greater than the amount of ammonia gas. In addition, by using ammonia gas, the decomposition of the sedimentary gas containing silicon and the nitrogen gas can be promoted. This is because the ammonia gas dissociates by plasma energy and thermal energy, and the energy generated by the dissociation contributes to the decomposition of the bonds of the sedimentary gas containing silicon and the bonds of the nitrogen gas.

Therefore, by the method described above, a silicon nitride film (118c) with a small amount of hydrogen gas and ammonia gas emissions can be formed. In addition, since the hydrogen content is small, a silicon nitride film (118c) that becomes dense and does not permeate or hardly permeate hydrogen, water, and oxygen can be formed.

Next, it is preferable to perform a third heat treatment. The third heat treatment may be performed with reference to the description of the first heat treatment. By the third heat treatment, excess oxygen is released from the gate insulating film (112) or/and the protective insulating film (118), and oxygen vacancies in the multilayer film (106) can be reduced. In addition, within the multilayer film (106), oxygen vacancies apparently move by capturing adjacent oxygen atoms.

In this manner, a transistor having the BGTC structure shown in Fig. 1 can be manufactured.

1-3. Transistor structure (2)

Here, a transistor which is a modified example of the transistor illustrated in Fig. 1 is explained using Fig. 7.

In Fig. 7, a top view and a cross-sectional view of a transistor of this modified example are shown. Fig. 7(A) shows a top view of the transistor. In Fig. 7(A), a cross-sectional view corresponding to the dashed-dotted line A1-A2 is shown in Fig. 7(B). In addition, in Fig. 7(A), a cross-sectional view corresponding to the dashed-dotted line A3-A4 is shown in Fig. 7(C). In addition, in Fig. 7(A), some of the components of the transistor (such as a gate insulating film and a protective insulating film) are omitted for clarity of the drawing.

The transistor illustrated in Fig. 7 differs from the transistor illustrated in Fig. 1 in that an oxide film (107) is formed in contact with the upper surfaces of the source electrode (116a) and the drain electrode (116b) and the upper surface of the multilayer film (106).

The oxide film (117) can utilize an oxide film applicable to the oxide film (106b) of the multilayer film (106), and can be formed using a method applicable to the oxide film (106b). In addition, other components of the transistor illustrated in Fig. 7 are the same as those of the transistor illustrated in Fig. 1, and reference can be made thereto as appropriate.

Since the structure of the transistor illustrated in Fig. 7 is a structure in which an oxide film (106b) and an oxide film (107) are formed between an oxide semiconductor film (106a) and a protective insulating film (118), a trap level caused by an impurity or defect formed near the interface with the protective insulating film (118) can be further moved away from the oxide semiconductor film (106a). That is, even when the energy difference between EcS1 and EcS2 is small, electrons in the oxide semiconductor film (106a) can be suppressed from reaching the trap level beyond this energy difference. Therefore, the transistor illustrated in Fig. 7 is a transistor having stable electrical characteristics with further reduced fluctuations in the threshold voltage of the transistor.

In addition, the method for manufacturing the transistor illustrated in Fig. 7 can appropriately refer to the description of the transistor illustrated in Fig. 1.

As described above, the transistors illustrated in FIG. 1 and FIG. 7 have stable electrical characteristics because the impurity and carrier density are reduced in the oxide semiconductor film (106a) (particularly in the channel region) of the multilayer film (106).

(Embodiment 2)

In this embodiment, as one form of the present invention, a transistor having a structure that is somewhat different from that of Embodiment 1 is described.

2-1. Transistor structure (3)

In this embodiment, a top gate type transistor is described. Here, a transistor having a top gate top contact structure (TGTC structure), which is a type of top gate type transistor, is described using Fig. 8.

In Fig. 8, a top view and a cross-sectional view of a transistor having a TGTC structure are shown. Fig. 8(A) shows a top view of the transistor. In Fig. 8(A), a cross-sectional view corresponding to the dashed-dotted line B1-B2 is shown in Fig. 8(B). In addition, in Fig. 8(A), a cross-sectional view corresponding to the dashed-dotted line B3-B4 is shown in Fig. 8(C).

The transistor illustrated in Fig. 8(B) has a multilayer film (206) including a base insulating film (202) formed on a substrate (200), an oxide film (206c) formed on the base insulating film (202), an oxide semiconductor film (206a) formed on the oxide film (206c), and an oxide film (206b) formed on the oxide semiconductor film (206a), a source electrode (216a) and a drain electrode (216b) formed on the base insulating film (202) and the multilayer film (206), a gate insulating film (212) formed on the multilayer film (206), the source electrode (216a) and the drain electrode (216b), a gate electrode (204) formed on the gate insulating film (212), and a protective insulating film (218) formed on the gate insulating film (212) and the gate electrode (204). Additionally, the transistor may not have one or both of the insulating film (202) and the protective insulating film (218).

In addition, depending on the type of conductive film used for the source electrode (216a) and the drain electrode (216b), there are cases where oxygen is taken from a part of the multilayer film (206) or a mixed layer is formed to form a low-resistance region (206d) and a low-resistance region (206e) within the multilayer film (206). In Fig. 8(B), the low-resistance region (206d) and the low-resistance region (206e) are regions near the interface where the source electrode (216a) and the drain electrode (216b) are in contact with the multilayer film (206) (regions between the broken line of the multilayer film (206) and the source electrode (216a) and the drain electrode (216b)). Part or all of the low-resistance region (206d) and the low-resistance region (206e) function as the source region and the drain region.

In Fig. 8(A), the spacing between the source electrode (216a) and the drain electrode (216b) in the region overlapping with the gate electrode (204) is referred to as the channel length. However, when the transistor includes a source region and a drain region, the spacing between the source region and the drain region in the region overlapping with the gate electrode (204) may also be referred to as the channel length.

In addition, the channel formation region refers to a region in the multilayer film (206) that overlaps the gate electrode (204) and is also sandwiched between the source electrode (216a) and the drain electrode (216b). In addition, the channel region refers to a region in the channel formation region where current mainly flows. Here, the channel region is a part of the oxide semiconductor film (206a) within the channel formation region.

2-1-1. About multilayer films

The multilayer film (206) has a structure in which an oxide film (206b) and an oxide film (206c) are laminated on top and bottom of an oxide semiconductor film (206a). The lower surface of the oxide semiconductor film (206a) corresponds to the surface of the oxide semiconductor film (206a) on the substrate (200) side, or the boundary surface with the oxide film (206c). The lower surface of the oxide film (206b) corresponds to the surface of the oxide film (206b) on the substrate (200) side, or the boundary surface with the oxide semiconductor film (206a). The lower surface of the oxide film (206c) corresponds to the surface of the oxide film (206c) on the substrate (200) side, or the surface of the oxide film (206c) that contacts the gate insulating film (112). In addition, the laminated structure of the multilayer film (206) can be confirmed by observing it using STEM (Scanning Transmission Electron Microscopy). However, depending on the materials used for the oxide semiconductor film (206a), oxide film (206b), and oxide film (206c), there are cases where this boundary cannot be clearly identified.

The oxide semiconductor film (206a) can use an oxide semiconductor film applicable to the oxide semiconductor film (106a) of embodiment 1. The oxide film (206b) can use an oxide film applicable to the oxide film (106b) of embodiment 1. The oxide film (206c) can use an oxide film applicable to the oxide film (106b) of embodiment 1.

In the multilayer film (206), at least the oxide semiconductor film (206a) has a tapered shape. Preferably, the oxide film (206b) and the oxide film (206c) also have tapered shapes. In addition, it is preferable that at least the tapered shape of the oxide semiconductor film (206a) is different from the tapered shape of the oxide film (206b) and the tapered shape of the oxide film (206c). The tapered shapes of the oxide film (206b) and the oxide film (206c) may be the same or different.

Specifically, in the case where the angle between the lower surface of the oxide semiconductor film (206a) and the side surface of the oxide semiconductor film (206a) is set as the first angle (θ1), in the case where the angle between the lower surface of the oxide film (206b) and the side surface of the oxide film (206b) is set as the second angle (θ2), and in the case where the angle between the lower surface of the oxide film (206c) and the side surface of the oxide film (206c) is set as the third angle (θ3), the first angle (θ1) can be set as an acute angle, and the second angle (θ2) and the third angle (θ3) can be set as acute angles or vertical angles.

In particular, the first angle (θ1), the second angle (θ2), and the third angle (θ3) are all acute angles, and it is preferable that at least the first angle (θ1) is smaller than the second angle (θ2) and the third angle (θ3) (see FIG. 9).

In addition, the second angle (θ2) and the third angle (θ3) may be the same angle or may be different angles. For example, by making the oxide film (206b) and the oxide film (206c) the same type of oxide film, the second angle (θ2) and the third angle (θ3) can be the same angle.

In addition, it is preferable that the first angle (θ1) is 10° or more and less than 90°, and 30° or more and 70° or less. It is preferable that the second angle (θ2) and the third angle (θ3) are 10° or more and less than 90°, and 30° or more and 70° or less.

In this way, by forming the multilayer film (206) into a tapered shape having a different taper angle, the following effects can be obtained. For the multilayer film (206), by forming it into a tapered shape having a different taper angle compared to a tapered shape having a constant taper angle, the contact area with the source electrode (216a) and the drain electrode (216b) can be expanded. Accordingly, the contact resistance between the multilayer film (206) and the source electrode (216a) and the drain electrode (216b) is reduced, and the on-state current of the transistor can be increased.

In addition, by making the second angle (θ2) and the third angle (θ3) larger than the first angle (θ1), the contact area between the oxide film (206b), the oxide film (206c) and the source electrode (216a) and the drain electrode (216b) can be reduced, and the low-resistance region formed in the oxide film (206b) and the oxide film (206c) can be reduced. As a result, while suppressing the low resistance of one or both of the oxide film (206b) and the oxide film (206c) and suppressing the occurrence of a leak path between the source electrode (216a) and the drain electrode (216b), it is possible to effectively form a low-resistance region in the oxide semiconductor film (206a) that functions as a channel region, thereby achieving both an increase in the on-current of the transistor and a decrease in the off-current of the transistor.

In addition, the upper part of the oxide semiconductor film (206a) and the lower part of the oxide film (206b), and the upper part of the oxide film (206c) and the lower part of the oxide semiconductor film (206a) are approximately aligned (see Fig. 9). That is, the multilayer film (206) does not have a large step (213) and a large step (214) formed by two or more films among the oxide semiconductor film (206a), the oxide film (206b), and the oxide film (206c) (see Figs. 32(A) and 32(B)). Therefore, it is possible to suppress the disconnection of the ends of films formed on the multilayer film (206) (for example, conductive films processed into the source electrode (216a) and the drain electrode (216b)), and it is possible to manufacture a transistor having good electrical characteristics. In addition, the fact that the upper part of the oxide semiconductor film (206a) and the lower part of the oxide film (206b), and the upper part of the oxide film (206c) and the lower part of the oxide semiconductor film (206a) are almost aligned means that the distance (L1) from the upper part of the oxide semiconductor film (206a) at the lower part of the oxide film (206b) and the distance (L2) from the lower part of the oxide semiconductor film (206a) at the upper part of the oxide film (206c) are 30 nm or less, preferably 10 nm or less (see FIG. 32(A) and FIG. 32(B)).

The above tapered shape can be formed by utilizing the fact that the etching rates of each film are different when forming the multilayer film (206) by etching. In particular, the above tapered shape can be formed by making the etching rate of the oxide semiconductor film (206a) slower than the etching rate of the oxide film (206b) and the etching rate of the oxide film (206c).

When the second angle (θ2) is smaller than the third angle (θ3), it is preferable to make the etching speed of the oxide film (206b) slower than the etching speed of the oxide film (206c). Also, when the second angle (θ2) is larger than the third angle (θ3), it is preferable to make the etching speed of the oxide film (206b) faster than the etching speed of the oxide film (206c).

The above-mentioned tapered shape can be formed by wet etching using a solution containing phosphoric acid as a corrosive liquid, similarly to Embodiment 1. In addition, details of this wet etching can be referred to Embodiment 1. In addition, by making the second angle (θ2) and the third angle (θ3) larger than the first angle (θ1), the area exposed to the corrosive liquid in this wet etching can be made as small as possible. In addition, by making the second angle (θ2) and the third angle (θ3) larger than the first angle (θ1), the low-resistance region formed in the oxide film (206b) and the oxide film (206c) due to contamination by the corrosive liquid or generation of defects can be made small.

By forming a multilayer film (206) by wet etching, as described in embodiment 1, it is possible to suppress a decrease in the yield of the transistor and produce a transistor with good electrical characteristics with high productivity.

Below, the band structure of the multilayer film (206) is explained using Fig. 10.

As an example, In-Ga-Zn oxide having an energy gap of 3.15 eV is used as the oxide semiconductor film (206a), and In-Ga-Zn oxide having an energy gap of 3.5 eV is used as the oxide film (206b) and the oxide film (206c). The energy gap was measured using a spectroscopic ellipsometer (UT-300, manufactured by HORIBA JOBIN YVON).

The energy difference (also called ionization potential) between the vacuum level and the top of the valence band of the oxide semiconductor film (206a) was 8 eV. In addition, the ionization potentials of the oxide film (206b) and the oxide film (206c) were 8.2 eV. In addition, the energy difference between the vacuum level and the top of the valence band was measured using an ultraviolet photoelectron spectroscopy (UPS) device (PHI VersaProbe).

Therefore, the energy of the vacuum level and the bottom of the conduction band (also called electron affinity) of the oxide semiconductor film (206a) was 4.85 eV. The electron affinities of the oxide film (206b) and the oxide film (206c) were 4.7 eV.

In Fig. 10(A), a part of the band structure of the multilayer film (206) is schematically illustrated. In Fig. 10(A), a case is described where a silicon oxide film (the base insulating film (202) and the gate insulating film (212)) is formed by contacting each of the oxide film (206b) and the oxide film (206c). Here, EcI1 represents the energy of the bottom of the conduction band of the silicon oxide film, EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor film (206a), EcS2 represents the energy of the bottom of the conduction band of the oxide film (206b), EcS3 represents the energy of the bottom of the conduction band of the oxide film (206c), and EcI2 represents the energy of the bottom of the conduction band of the silicon oxide film.

As illustrated in Fig. 10(A), in the oxide semiconductor film (206a), the oxide film (206b), and the oxide film (206c), the energy at the bottom of the conduction band changes gradually without a barrier. In other words, it can be said that it changes continuously. This can be said to be because the oxide film (206b) and the oxide film (206c) contain elements in common with the oxide semiconductor film (206a), and a mixed layer is formed as oxygen moves between the oxide semiconductor film (206a) and the oxide film (206b), and between the oxide semiconductor film (206a) and the oxide film (206c).

By Fig. 10(A), it can be seen that the oxide semiconductor film (206a) of the multilayer film (206) becomes a well, and in the transistor using the multilayer film (206), a channel region is formed in the oxide semiconductor film (206a). In addition, since the energy at the bottom of the conduction band of the multilayer film (206) is continuously changing, it can also be said that the oxide semiconductor film (206a) and the oxide film (206b) and the oxide semiconductor film (206a) and the oxide film (206c) are continuously connected.

In addition, by making the oxide film (206b) and the oxide film (206c) into oxide films having different energies at the bottom of the conduction band, the band structure of the multilayer film (206) can be changed according to the relationship between the magnitudes of the energies at the bottom of the conduction band.

By using an oxide film (206c) that has an energy higher than the lower end of the conduction band of the oxide film (206b), a multilayer film (206) having the band structure shown in Fig. 10(B) can be formed.

By using an oxide film (206b) that has an energy lower than the lower end of the conduction band of the oxide film (206c), a multilayer film (206) having the band structure shown in Fig. 10(C) can be formed.

Additionally, in the multilayer film (206) having the band structure shown in FIG. 10(B) and FIG. 10(C), the channel region is formed in the oxide semiconductor film (206a).

In addition, a trap level due to an impurity or defect may be formed near the interface between the oxide film (206b) and the gate insulating film (212), but by forming the oxide film (206b), the oxide semiconductor film (206a) can be separated from this trap level. However, when the energy difference between EcS1 and EcS2 is small, there are cases where electrons in the oxide semiconductor film (206a) exceed this energy difference and reach the trap level. By capturing electrons at the trap level, negative fixed charges are generated at the insulating film interface, and the threshold voltage of the transistor shifts in the positive direction.

In addition, a trap level due to an impurity or defect may be formed near the interface between the oxide film (206c) and the base insulating film (202), but the oxide semiconductor film (206a) can be distant from this trap level. However, when the energy difference between EcS1 and EcS3 is small, there are cases where electrons in the oxide semiconductor film (206a) exceed this energy difference and reach the trap level. When electrons are captured at the trap level, a negative fixed charge is generated at the insulating film interface, and the threshold voltage of the transistor shifts in the positive direction.

Therefore, it is preferable that the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 be 0.1 eV or more, preferably 0.15 eV or more, because this reduces fluctuations in the threshold voltage of the transistor and stabilizes the electrical characteristics.

2-1-2. About other configurations

The substrate (200) may refer to the description for the substrate (100). In addition, the source electrode (216a) and the drain electrode (216b) may refer to the description for the source electrode (116a) and the drain electrode (116b). In addition, the gate insulating film (212) may refer to the description for the gate insulating film (112). In addition, the gate electrode (204) may refer to the description for the gate electrode (104). In addition, the protective insulating film (218) may refer to the description for the protective insulating film (118).

In addition, in Fig. 8(A), the multilayer film (206) is formed to the outside from the gate electrode (204) in the top surface shape, but in order to suppress the generation of carriers within the multilayer film (206) by light from above, the width of the gate electrode (204) may be formed to be larger than the width of the multilayer film (206).

The insulating film (202) may be an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and may be used as a single layer or in a laminated form.

The insulating film (202) may have a laminated structure in which, for example, the first layer is a silicon nitride film and the second layer is a silicon oxide film. In this case, the silicon oxide film may be a silicon nitride oxide film. In addition, the silicon nitride film may be a silicon nitride oxide film. It is preferable to use a silicon oxide film having a small defect density as the silicon oxide film. Specifically, a silicon oxide film having a spin density derived from a signal having a g value of 2.001 in ESR of 3×10 ¹⁷ spins/cm ³ or less, preferably 5×10 ¹⁶ spins/cm ³ or less, is used. The silicon nitride film uses a silicon nitride film having a small amount of hydrogen and ammonia released. The amount of hydrogen and ammonia released can be measured by TDS analysis. In addition, the silicon nitride film uses a silicon nitride film that does not transmit, or hardly transmits, hydrogen, water, and oxygen.

In addition, the insulating film (202) may have a laminated structure in which, for example, the first layer is a first silicon nitride film, the second layer is a first silicon oxide film, and the third layer is a second silicon oxide film. In this case, the first silicon oxide film and/or the second silicon oxide film may be a silicon oxynitride film. In addition, the silicon nitride film may be a silicon oxynitride film. It is preferable that the first silicon oxide film use a silicon oxide film having a small defect density. Specifically, a silicon oxide film having a spin density derived from a signal having a g value of 2.001 in ESR is used of 3×10 ¹⁷ spins/cm ³ or less, preferably 5×10 ¹⁶ spins/cm ³ or less. The second silicon oxide film uses a silicon oxide film containing excess oxygen. The silicon nitride film uses a silicon nitride film having a small amount of hydrogen and ammonia released. In addition, a silicon nitride film is used that is impermeable to hydrogen, water, and oxygen, or is substantially impermeable to them.

When one or both of the gate insulating film (212) and the base insulating film (202) have insulating films containing excess oxygen, oxygen vacancies in the oxide semiconductor film (206a) can be reduced.

As described above, the transistor shown in the present embodiment has stable electrical characteristics and high field-effect mobility because the impurity and carrier density of the oxide semiconductor film (206a) (particularly, the channel region) of the multilayer film (206) is reduced.

2-2. Manufacturing method of transistor structure (3)

Here, the method of manufacturing a transistor is explained using Figs. 11 and 12.

First, prepare the substrate (200).

A base insulating film (202) is formed on the substrate (200). The base insulating film (202) may be formed using the above-listed insulating films by sputtering, CVD, MBE, ALD or PLD.

Next, an oxide film (226c) processed into an oxide film (206c) is formed. The method for forming the oxide film (206c) can refer to the description of the oxide film (106b) of Embodiment 1. In addition, the oxide film (206c) is formed so as to be CAAC-OS or amorphous. If the oxide film (206c) is CAAC-OS or amorphous, the oxide semiconductor film (226a) that becomes the oxide semiconductor film (206a) is likely to be CAAC-OS.

Next, an oxide semiconductor film (226a) processed into an oxide semiconductor film (206a) is formed. The method for forming the oxide semiconductor film (226a) can refer to the description of the oxide semiconductor film (106a) of Embodiment 1.

Next, an oxide film (226b) processed into an oxide film (206b) is formed. For the method for forming the oxide film (226b), reference can be made to the description of the oxide film (106b) of embodiment 1 (see Fig. 11(A)).

As described in Embodiment 1, in order to continuously bond the oxide film (206c), the oxide semiconductor film (206a), and the oxide film (206b), it is preferable that the oxide film (226c), the oxide semiconductor film (226a), and the oxide film (226b) be continuously laminated without exposing each film to the atmosphere.

Next, a portion of the oxide film (226c), the oxide semiconductor film (226a), and the oxide film (226b) is etched, and a multilayer film (206) including the oxide film (206c), the oxide semiconductor film (206a), and the oxide film (206b) is formed (see Fig. 11(B)). In addition, this etching can be referred to above.

Next, it is preferable to perform the first heat treatment. The first heat treatment may be performed at 250°C or more and 650°C or less, preferably 300°C or more and 500°C or less. The atmosphere of the first heat treatment may be an inert gas atmosphere, an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, or a reduced pressure state. Alternatively, the atmosphere of the first heat treatment may be an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to replenish the oxygen that has escaped after the heat treatment in an inert gas atmosphere. By the first heat treatment, the crystallinity of the oxide semiconductor film (226a) can be increased, and impurities such as water, hydrogen, nitrogen, and carbon can be removed from the base insulating film (202) and the multilayer film (206).

Additionally, the first heat treatment can be performed on at least one side before or after the etching process for forming the multilayer film (206).

Next, conductive films that become the source electrode (216a) and the drain electrode (216b) are formed. For the method of forming the conductive films that become the source electrode (216a) and the drain electrode (216b), reference can be made to the description of the source electrode (116a) and the drain electrode (116b) of Embodiment 1.

Next, a portion of the conductive film that becomes the source electrode (216a) and the drain electrode (216b) is etched, and the source electrode (216a) and the drain electrode (216b) are formed (see Fig. 11(C)).

Next, it is preferable to perform a second heat treatment. The second heat treatment may be performed with reference to the description of the first heat treatment. By the second heat treatment, impurities such as water, hydrogen, nitrogen, and carbon can be removed from the multilayer film (206).

In addition, by the second heat treatment, a low-resistance region (206d) and a low-resistance region (206e) can be formed in the multilayer film (206) in contact with the source electrode (216a) and the drain electrode (216b).

Next, a gate insulating film (212) is formed (see Fig. 12(A)). The method for forming the gate insulating film (212) refers to the description of the gate insulating film (112) of Embodiment 1.

Next, a conductive film to become the gate electrode (204) is formed. Next, a part of the conductive film to become the gate electrode (204) is etched, and the gate electrode (204) is formed (see Fig. 12(B)). The method for forming the gate electrode (204) and the etching process can refer to the description of the gate electrode (104) of Embodiment 1.

Next, a protective insulating film (218) is formed (see Fig. 8(B)). The method for forming the protective insulating film (218) refers to the description of the protective insulating film (118).

In this manner, the transistor shown in Fig. 8 can be manufactured.

2-3. Transistor structure (4)

Here, a transistor which is a modified example of the transistor illustrated in Fig. 8 is explained using Fig. 13.

In Fig. 13, a top view and a cross-sectional view of a transistor of this modified example are shown. Fig. 13(A) shows a top view of the transistor. In Fig. 13(A), a cross-sectional view corresponding to the dashed-dotted line B1-B2 is shown in Fig. 13(B). In addition, in Fig. 13(A), a cross-sectional view corresponding to the dashed-dotted line B3-B4 is shown in Fig. 13(C). In addition, in Fig. 13(A), some of the components of the transistor (such as a gate insulating film and a protective insulating film) are omitted for clarity of the drawing.

The transistor illustrated in Fig. 13 is different from the transistor illustrated in Fig. 8 in that it does not have an oxide film (206c) in the multilayer film (206). That is, the multilayer film (206) in the transistor illustrated in Fig. 13 is an oxide semiconductor film (206a) and an oxide film (206b). In addition, other components of the transistor illustrated in Fig. 13 are the same as those of the transistor illustrated in Fig. 8, and reference can be made thereto as appropriate.

In the transistor illustrated in Fig. 13, a trap level due to an impurity or defect may be formed near the interface between the oxide film (206b) and the gate insulating film (212), but by forming the oxide film (206b), the oxide semiconductor film (206a) and this trap level can be distanced. Therefore, the transistor illustrated in Fig. 13 is a transistor having stable electrical characteristics with reduced fluctuations in the threshold voltage of the transistor.

In addition, the method for manufacturing the transistor illustrated in Fig. 13 can appropriately refer to the description of the transistor illustrated in Embodiment 1 and Fig. 8.

2-4. Transistor structure (5)

Here, a transistor which is a modified example of the transistor shown in Fig. 8 is explained using Fig. 14.

In Fig. 14, a top view and a cross-sectional view of a transistor of this modified example are shown. Fig. 14(A) shows a top view of the transistor. In Fig. 14(A), a cross-sectional view corresponding to the dashed-dotted line B1-B2 is shown in Fig. 14(B). In addition, in Fig. 14(A), a cross-sectional view corresponding to the dashed-dotted line B3-B4 is shown in Fig. 14(C). In addition, in Fig. 14(A), some of the components of the transistor (such as a gate insulating film and a protective insulating film) are omitted for clarity of the drawing.

The transistor illustrated in Fig. 14 is different from the transistor illustrated in Fig. 8 in that it does not have an oxide film (206b) in the multilayer film (206). That is, the multilayer film (206) in the transistor illustrated in Fig. 14 is an oxide film (206c) and an oxide semiconductor film (206a). In addition, it is different in that an oxide film (207) is formed in contact with the upper surfaces of the source electrode (216a) and the drain electrode (216b), and the upper surface of the multilayer film (206).

The oxide film (207) can utilize an oxide film applicable to the oxide film (106b) of the multilayer film (106) of Example 1, and can be formed using a method applicable to the oxide film (106b). In addition, other components of the transistor illustrated in Fig. 14 are the same as those of the transistor illustrated in Fig. 8, and reference can be made thereto as appropriate.

Since the structure of the transistor illustrated in Fig. 14 is a structure in which an oxide film (207) is formed between an oxide semiconductor film (206a) and a gate insulating film (212), trap levels caused by impurities or defects formed near the interface between the oxide film (207) and the gate insulating film (212) can be kept away from the oxide semiconductor film (106a). Therefore, the transistor illustrated in Fig. 14 is a transistor having stable electrical characteristics with reduced fluctuations in the threshold voltage of the transistor.

In addition, the method for manufacturing the transistor illustrated in Fig. 14 can appropriately refer to the description of the transistor illustrated in Embodiment 1 and Fig. 8.

2-5. Other transistor structures

For example, in the transistor illustrated in Fig. 8, a transistor having a structure in which an oxide film (207) of the transistor illustrated in Fig. 14 is formed between the upper surface of the source electrode (212a) and the drain electrode (212b), and the upper surface of the multilayer film (206) and the gate insulating film (212) is also included in one embodiment of the present invention.

By forming a transistor with this structure, since the oxide film (206b) and the oxide film (207) can be formed between the oxide semiconductor film (206a) and the gate insulating film (212), the trap level caused by the impurity or defect formed near the interface between the oxide film (207) and the gate insulating film (212) can be moved further away from the oxide semiconductor film (206a). That is, even when the energy difference between EcS1 and EcS2 is small, the electrons of the oxide semiconductor film (206a) can be suppressed from reaching the trap level beyond this energy difference. Therefore, a transistor having stable electrical characteristics and further reduced fluctuation in the threshold voltage of the transistor can be obtained.

In addition, a transistor in which the multilayer film (106) of the bottom gate structure transistor described in Embodiment 1 is replaced with a multilayer film (206) having an oxide semiconductor film (206a), an oxide film (206b), and an oxide film (206c) is also included in one embodiment of the present invention.

By the above, the transistors illustrated in FIG. 8, FIG. 13, and FIG. 14 have stable electrical characteristics because the impurity and carrier density are reduced in the oxide semiconductor film (106) and the oxide semiconductor film (206a) (particularly in the channel region) of the multilayer film (106), the multilayer film (206).

(Embodiment 3)

In this embodiment, a semiconductor device using the transistor described in the above embodiment is described.

3-1. Display device

Here, a display device, which is one of the semiconductor devices using the transistor described in the above embodiment, is described.

As display elements formed in the display device, liquid crystal elements (also called liquid crystal display elements), light-emitting elements (also called light-emitting display elements), etc. can be used. Light-emitting elements include elements whose brightness is controlled by current or voltage in their category, and specifically include inorganic EL (Electro Luminescence), organic EL, etc. In addition, display media whose contrast changes by electrical action, such as electronic ink, can also be applied as display elements. Hereinafter, as examples of display devices, a display device using an EL element and a display device using a liquid crystal element will be described.

In addition, the display device shown below includes a panel in which the display element is sealed and a module in which an IC including a controller is mounted on the panel.

In addition, the display device shown below refers to an image display device or a light source (including a lighting device). In addition, a module equipped with a connector, such as an FPC or TCP, a module in which a printed wiring board is formed at the end of the TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by the COG method are all included in the display device.

In addition, the display device shown below can form an input means that is performed by contact or non-contact sensing (not shown). For example, as an input means that is performed by contact sensing, various types of touch sensors such as a resistive film method, an electrostatic capacitance method, an infrared method, an electromagnetic induction method, a surface acoustic wave method, etc. can be used. In addition, as an input means that is performed by non-contact sensing, it can be implemented by using an infrared camera or the like.

This input means may be formed separately on the display device shown below, in the so-called on-cell manner, or may be formed integrally with the display device shown below, in the so-called in-cell manner.

3-1-1. EL display device

Here, we describe a display device using an EL element (also called an EL display device).

Fig. 15 is an example of a circuit diagram of a pixel of an EL display device.

The EL display device illustrated in Fig. 15 has a switching element (743), a transistor (741), a capacitor (742), and a light-emitting element (719).

The gate of the transistor (741) is electrically connected to one end of the switch element (743) and one end of the capacitor (742). The source of the transistor (741) is electrically connected to one end of the light-emitting element (719). The drain of the transistor (741) is electrically connected to the other end of the capacitor (742), and a power supply potential (VDD) is provided. The other end of the switch element (743) is electrically connected to the signal line (744). The other end of the light-emitting element (719) is provided with a positive potential. In addition, the positive potential is set to a ground potential (GND) or a potential lower than that.

In addition, the transistor (741) uses the transistor described in the above embodiment. This transistor has stable electrical characteristics. Therefore, it can be made into an EL display device with high display quality.

As the switching element (743), it is preferable to use a transistor. By using a transistor, the pixel area can be made small, and an EL display device with high resolution can be made. In addition, the transistor described in the above embodiment may be used as the switching element (743). By using this transistor as the switching element (743), the switching element (743) can be manufactured by the same process as the transistor (741), and the productivity of the EL display device can be increased.

Fig. 16(A) is a top view of an EL display device. The EL display device has a substrate (100), a substrate (700), a sealant (734), a driving circuit (735), a driving circuit (736), a pixel (737), and an FPC (732). The sealant (734) is formed between the substrate (100) and the substrate (700) so as to surround the pixel (737), the driving circuit (735), and the driving circuit (736). In addition, one or both of the driving circuit (735) and the driving circuit (736) may be formed on the outside of the sealant (734).

Fig. 16(B) is a cross-sectional view of an EL display device corresponding to the dashed-dotted line M-N of Fig. 16(A). The FPC (732) is connected to a wiring (733a) via a terminal (731). In addition, the wiring (733a) is on the same layer as the gate electrode (104).

In addition, Fig. 16(B) shows an example in which the transistor (741) and the capacitor (742) are formed on the same plane. By forming the structure in this way, the capacitor (742) can be formed on the same plane as the gate electrode, the gate insulating film, and the source electrode (drain electrode) of the transistor (741). In this way, by forming the transistor (741) and the capacitor (742) on the same plane, the manufacturing process of the EL display device can be shortened and the productivity can be increased.

In Fig. 16(B), an example is shown in which the transistor illustrated in Fig. 1 is applied as a transistor (741). Therefore, for each configuration of the transistor (741) that is not specifically described below, refer to the description of Fig. 1.

An insulating film (720) is formed over the transistor (741) and capacitor (742).

Here, an opening is formed in the insulating film (720) and the protective insulating film (118) that leads to the source electrode (116a) of the transistor (741).

An electrode (781) is formed on the insulating film (720). The electrode (781) comes into contact with the source electrode (116a) of the transistor (741) through an opening formed in the insulating film (720) and the protective insulating film (118).

A partition (784) having an opening leading to the electrode (781) is formed above the electrode (781).

On the partition wall (784), a light-emitting layer (782) is formed that comes into contact with the electrode (781) through an opening formed in the partition wall (784).

An electrode (783) is formed on the light-emitting layer (782).

The area where the electrode (781), the light-emitting layer (782), and the electrode (783) overlap becomes the light-emitting element (719).

In addition, the insulating film (720) refers to the description of the protective insulating film (118). Alternatively, a resin film such as polyimide resin, acrylic resin, epoxy resin, or silicone resin may be used.

The light-emitting layer (782) is not limited to a single layer, and may be formed by laminating multiple types of light-emitting layers. For example, a structure as illustrated in Fig. 16(C) may be used. Fig. 16(C) shows a structure in which an intermediate layer (785a), a light-emitting layer (786a), an intermediate layer (785b), a light-emitting layer (786b), an intermediate layer (785c), a light-emitting layer (786c), and an intermediate layer (785d) are sequentially laminated. At this time, if a light-emitting layer having an appropriate light-emitting color is used for the light-emitting layer (786a), the light-emitting layer (786b), and the light-emitting layer (786c), a light-emitting element (719) having high color rendering properties or high light-emitting efficiency can be formed.

By forming a plurality of light-emitting layers by laminating them, white light can be obtained. Although not shown in Fig. 16(B), a structure that extracts white light through a coloring layer may also be used.

Here, a structure is shown in which the light-emitting layer is formed in three layers and the intermediate layer is formed in four layers, but this is not limited thereto, and the number of light-emitting layers and the number of intermediate layers can be appropriately changed. For example, it can be configured with only the intermediate layer (785a), the light-emitting layer (786a), the intermediate layer (785b), the light-emitting layer (786b), and the intermediate layer (785c). In addition, it is also possible to have a structure in which the intermediate layer (785a), the light-emitting layer (786a), the intermediate layer (785b), the light-emitting layer (786b), the light-emitting layer (786c), and the intermediate layer (785d) are configured, and the intermediate layer (785c) is omitted.

In addition, the intermediate layer may utilize a layered structure of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In addition, the intermediate layer does not have to have all of these layers. These layers may be formed by appropriately selecting them. In addition, layers having the same function may be formed in duplicate. In addition to the carrier generation layer, an electron relay layer, etc. may be appropriately added as the intermediate layer.

It is preferable for the electrode (781) to use a conductive film having visible light transparency. Having visible light transparency means that the average transmittance in the visible light range (e.g., wavelength range of 400 nm to 800 nm) is 70% or more, particularly 80% or more.

As the electrode (781), for example, an oxide film such as an In-Zn-W oxide film, an In-Sn oxide film, an In-Zn oxide film, an indium oxide film, a zinc oxide film, and a tin oxide film may be used. In addition, the oxide film described above may have trace amounts of Al, Ga, Sb, F, etc. added to it. In addition, a metal thin film (preferably about 5 nm to 30 nm) that transmits light may be used. For example, an Ag film, a Mg film, or an Ag-Mg alloy film having a film thickness of 5 nm may be used.

Alternatively, the electrode (781) is preferably a film that efficiently reflects visible light. The electrode (781) may be a film including, for example, lithium, aluminum, titanium, magnesium, lanthanum, silver, silicon, or nickel.

Electrode (783) can be selected and used from the film shown as electrode (781). However, in the case where electrode (781) has visible light transparency, it is preferable that electrode (783) efficiently reflects visible light. In addition, in the case where electrode (781) efficiently reflects visible light, it is preferable that electrode (783) has visible light transparency.

In addition, although the electrode (781) and the electrode (783) are formed in the structure illustrated in Fig. 16(B), the electrode (781) and the electrode (783) may be interchanged. For the electrode functioning as the anode, it is preferable to use a conductive film having a large work function, and for the electrode functioning as the cathode, it is preferable to use a conductive film having a small work function. However, when forming a carrier generation layer by contacting the anode, various conductive films can be used as the anode without considering the work function.

The bulkhead (784) refers to the description of the protective insulating film (118). Alternatively, a resin film such as polyimide resin, acrylic resin, epoxy resin, or silicone resin may be used.

In addition, in the display device, optical members (optical substrates) such as a black matrix (shielding film), a polarizing member, a phase difference member, an anti-reflection member, etc. are appropriately formed. For example, circular polarization by a polarizing substrate and a phase difference substrate may be utilized.

The transistor (741) connected to the light-emitting element (719) has stable electrical characteristics. Therefore, an EL display device with high display quality can be provided.

Fig. 17(A) and Fig. 17(B) are examples of cross-sectional views of an EL display device that are partially different from Fig. 16(B). Specifically, the wiring connected to the FPC (732) is different. In Fig. 17(A), the FPC (732) and the wiring (733b) are connected via the terminal (731). The wiring (733b) is on the same layer as the source electrode (116a) and the drain electrode (116b). In Fig. 17(B), the FPC (732) and the wiring (733c) are connected via the terminal (731). The wiring (733c) is on the same layer as the electrode (781).

3-1-2. Liquid crystal display device

Next, we will explain a display device using a liquid crystal element (also called a liquid crystal display device).

Fig. 18 is a circuit diagram showing an example of a pixel configuration of a liquid crystal display device. The pixel (750) shown in Fig. 18 has a transistor (751), a capacitor (752), and an element (hereinafter also referred to as a liquid crystal element) (753) in which liquid crystal is charged between a pair of electrodes.

In the transistor (751), one side of the source and drain is electrically connected to the signal line (755), and the gate is electrically connected to the scan line (754).

In the capacitor (752), one electrode is electrically connected to the other of the source and drain of the transistor (751), and the other electrode is electrically connected to a wiring that supplies a common potential.

In the liquid crystal element (753), one electrode is electrically connected to the other side of the source and drain of the transistor (751), and the other electrode is electrically connected to a wiring that supplies a common potential. In addition, the common potential given to the wiring to which the other electrode of the capacitor (752) described above is electrically connected and the common potential given to the other electrode of the liquid crystal element (753) may be different potentials.

Also, the liquid crystal display device has a top view that is roughly the same as the EL display device. A cross-sectional view of the liquid crystal display device corresponding to the dashed-dotted line M-N in Fig. 16(A) is shown in Fig. 19(A). In Fig. 19(A), the FPC (732) is connected to the wiring (733a) via the terminal (731). Also, the wiring (733a) is on the same layer as the gate electrode (104).

Fig. 19(A) shows an example in which a transistor (751) and a capacitor (752) are formed on the same plane. By forming the structure in this way, the capacitor (752) can be manufactured on the same plane as the gate electrode, gate insulating film, and source electrode (drain electrode) of the transistor (751). In this way, by forming the transistor (751) and the capacitor (752) on the same plane, the manufacturing process of the liquid crystal display device can be shortened and productivity can be increased.

As the transistor (751), the transistor described above can be applied. Fig. 19(A) shows an example in which the transistor illustrated in Fig. 1 is applied. Therefore, for each configuration of the transistor (751) that is not specifically described below, refer to the description of Fig. 1.

In addition, the transistor (751) can be a transistor having a very small off-state current. Therefore, the charge held in the capacitor (752) is unlikely to leak, and the voltage applied to the liquid crystal element (753) can be maintained for a long period of time. Therefore, when displaying a moving picture or still image with little movement, by turning the transistor (751) off, power for the operation of the transistor (751) becomes unnecessary, and a liquid crystal display device with low power consumption can be achieved.

The size of the capacitor (752) formed in the liquid crystal display device is set so that it can hold a charge for a predetermined period of time, taking into consideration the leakage current of the transistor (751) arranged in the pixel portion, etc. By using the transistor (751), it is sufficient to form a capacitor having a size of 1/3 or less, preferably 1/5 or less, of the liquid crystal capacity in each pixel, so that the aperture ratio in the pixel can be increased.

An insulating film (721) is formed over the transistor (751) and capacitor (752).

Here, an opening is formed in the insulating film (721) and the protective insulating film (118) that reaches the drain electrode (116b) of the transistor (751).

An electrode (791) is formed on the insulating film (721). The electrode (791) comes into contact with the drain electrode (116b) of the transistor (751) through an opening formed in the insulating film (721) and the protective insulating film (118).

An insulating film (792) that functions as an alignment film is formed on the electrode (791).

A liquid crystal layer (793) is formed on the insulating film (792).

An insulating film (794) that functions as an alignment film is formed on the liquid crystal layer (793).

A spacer (795) is formed on the insulating film (794).

An electrode (796) is formed on the spacer (795) and the insulating film (794).

A substrate (797) is formed on the electrode (796).

In addition, the insulating film (721) refers to the description of the protective insulating film (118). Alternatively, a resin film such as polyimide resin, acrylic resin, epoxy resin, or silicone resin may be used.

The liquid crystal layer (793) may be formed using a thermotropic liquid crystal, a low-molecular liquid crystal, a polymer liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. Depending on the conditions, these liquid crystals exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc.

In addition, a liquid crystal that exhibits a blue phase may be used as the liquid crystal layer (793). In that case, it is preferable to use a configuration in which the insulating film (792) and the insulating film (794) that function as the alignment film are not formed.

It is preferable to use a conductive film having visible light transparency as the electrode (791).

When the liquid crystal display device is a transmissive type, as the electrode (791), an oxide film such as an In-Zn-W oxide film, an In-Sn oxide film, an In-Zn oxide film, an indium oxide film, a zinc oxide film, and a tin oxide film may be used, for example. In addition, the oxide film described above may have trace amounts of Al, Ga, Sb, F, etc. added to it. In addition, a metal thin film (preferably, about 5 nm to 30 nm) that transmits light may be used.

If the liquid crystal display device is a reflective type, the electrode (791) is preferably a film that efficiently reflects visible light. The electrode (791) may be a film containing, for example, aluminum, titanium, chromium, copper, molybdenum, silver, tantalum, or tungsten.

In the case where the liquid crystal display device is a transmissive type, the electrode (796) can be selected and used from a conductive film having visible light transparency, as indicated by the electrode (791). On the other hand, in the case where the liquid crystal display device is a reflective type, if the electrode (791) has visible light transparency, it is preferable that the electrode (796) efficiently reflects visible light. In addition, in the case where the electrode (791) efficiently reflects visible light, it is preferable that the electrode (796) has visible light transparency.

In addition, although the electrode (791) and the electrode (796) are formed in the structure shown in Fig. 19(A), the electrode (791) and the electrode (796) may be interchanged.

It is preferable to use an insulating film (792) and an insulating film (794) selected from organic compounds or inorganic compounds.

The spacer (795) may be selected and used from organic compounds or inorganic compounds. In addition, the shape of the spacer (795) may be taken in various forms, such as a columnar shape or a spherical shape.

The area where the electrode (791), the insulating film (792), the liquid crystal layer (793), the insulating film (794), and the electrode (796) overlap becomes the liquid crystal element (753).

The substrate (797) may be made of glass, resin, metal, or the like. The substrate (797) may be flexible.

Fig. 19(B) and Fig. 19(C) are examples of cross-sectional views of a liquid crystal display device that are partially different from Fig. 19(A). Specifically, the wiring connecting to the FPC (732) is different. In Fig. 19(B), the FPC (732) and the wiring (733b) are connected via the terminal (731). The wiring (733b) is on the same layer as the source electrode (116a) and the drain electrode (116b). In Fig. 19(C), the FPC (732) and the wiring (733c) are connected via the terminal (731). The wiring (733c) is on the same layer as the electrode (791).

The transistor (751) connected to the liquid crystal element (753) has stable electrical characteristics. Therefore, a liquid crystal display device with high display quality can be provided. In addition, since the transistor (751) can make the off current very small, a liquid crystal display device with low power consumption can be provided.

In the liquid crystal display, the operating mode can be appropriately selected. For example, there is a vertical field mode in which voltage is applied orthogonally to the substrate, and a horizontal field mode in which voltage is applied parallel to the substrate. Specifically, TN mode, VA mode, MVA mode, PVA mode, ASM mode, TBA mode, OCB mode, FLC mode, AFLC mode, or FFS mode can be mentioned.

In the liquid crystal display device, optical members (optical substrates) such as a black matrix (shielding layer), polarizing member, phase difference member, anti-reflection member, etc. are appropriately formed. For example, circular polarization by a polarizing substrate and a phase difference substrate may be used. In addition, a backlight, a side light, etc. may be used as a light source.

In addition, a time-division display method (field-sequential driving method) can be performed by using multiple light-emitting diodes (LEDs) as backlights. By applying the field-sequential driving method, color display can be performed without using a coloring layer.

As described above, the display method in the pixel portion uses a progressive method or an interlace method, etc. In addition, the color elements controlled by the pixels when displaying colors are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, there is RGBW (W represents white), or one or more colors such as yellow, cyan, and magenta added to RGB. In addition, the size of the display area for each dot of the color element may be different. However, the present invention is not limited to a liquid crystal display device for color display, and can be applied to a liquid crystal display device for black and white display.

3-2. Microcomputer

The transistor described above can be applied to microcomputers mounted in various electronic devices.

Hereinafter, the configuration and operation of a fire alarm as an example of an electronic device equipped with a microcomputer will be described using FIGS. 20, 21, 22, and 23(A).

In addition, in this specification, a fire alarm refers to a device that immediately reports the occurrence of a fire, and for example, a fire alarm for a home, an automatic fire notification device, or a fire detector used in the automatic fire notification device are also included in the fire alarm.

The alarm device illustrated in Fig. 20 has at least a microcomputer (500). Here, the microcomputer (500) is formed inside the alarm device. The microcomputer (500) is formed with a power gate controller (503) electrically connected to a high-potential power line (VDD), a power gate (504) electrically connected to the high-potential power line (VDD) and the power gate controller (503), a CPU (Central Processing Unit) (505) electrically connected to the power gate (504), and a detection unit (509) electrically connected to the power gate (504) and the CPU (505). In addition, the CPU (505) includes a volatile memory unit (506) and a nonvolatile memory unit (507).

In addition, the CPU (505) is electrically connected to the bus line (502) via the interface (508). The interface (508) is also electrically connected to the power gate (504) like the CPU (505). As a bus standard of the interface (508), for example, an I ² C bus can be used. In addition, a light-emitting element (530) electrically connected to the power gate (504) via the interface (508) is formed in the alarm device.

It is preferable that the light-emitting element (530) emits light with strong directionality, and for example, an organic EL element, an inorganic EL element, an LED, etc. can be used.

The power gate controller (503) has a timer and controls the power gate (504) according to the timer. The power gate (504) supplies or cuts off power supplied from a high-potential power line (VDD) to the CPU (505), the detection unit (509), and the interface (508) according to the control of the power gate controller (503). Here, as the power gate (504), a switching element such as a transistor can be used, for example.

By using the power gate controller (503) and power gate (504) as described above, power can be supplied to the detection unit (509), CPU (505), and interface (508) during the period of measuring the amount of light, and power supply to the detection unit (509), CPU (505), and interface (508) can be cut off between the measurement periods. By operating the alarm device in this way, power consumption can be reduced compared to the case where power is constantly supplied to each of the above components.

In addition, when using a transistor as a power gate (504), it is preferable to use a transistor having a very low off-state current, such as the transistor described in the above embodiment, used in the nonvolatile memory (507). By using such a transistor, when power is cut off by the power gate (504), the leakage current can be reduced, and power consumption can be reduced.

A DC power supply (501) may be formed in the alarm device, and power may be supplied from the DC power supply (501) to a high-potential power line (VDD). An electrode on the high-potential side of the DC power supply (501) is electrically connected to the high-potential power line (VDD), and an electrode on the low-potential side of the DC power supply (501) is electrically connected to a low-potential power line (VSS). The low-potential power line (VSS) is electrically connected to a microcomputer (500). Here, the high-potential power line (VDD) is given a high potential (H). In addition, the low-potential power line (VSS) is given a low potential (L), such as a ground potential (GND).

In the case where a battery is used as a DC power source (501), for example, a battery case having an electrode electrically connected to a high-potential power line (VDD), an electrode electrically connected to a low-potential power line (VSS), and a housing capable of holding the battery may be formed in a housing. In addition, the alarm device does not necessarily have to form a DC power source (501), and for example, a configuration may be used in which power is supplied through wiring from an AC power source formed outside the alarm device.

In addition, a secondary battery, for example, a lithium ion secondary battery (also called a lithium ion accumulator, a lithium ion battery, or a lithium ion battery) may be used as the battery. In addition, it is preferable to form a solar cell so as to be able to charge the secondary battery.

The detection unit (509) measures an abnormally related physical quantity and transmits the measured value to the CPU (505). The abnormally related physical quantity varies depending on the purpose of the alarm device, and in an alarm device that functions as a fire alarm, a physical quantity related to fire is measured. Accordingly, the detection unit (509) measures the amount of light as a physical quantity related to fire and detects the presence of smoke.

The detection unit (509) has a light sensor (511) electrically connected to the power gate (504), an amplifier (512) electrically connected to the power gate (504), and an AD converter (513) electrically connected to the power gate (504) and the CPU (505). The light emitting element (530), the light sensor (511), the amplifier (512), and the AD converter (513) operate when the power gate (504) supplies power to the detection unit (509).

A part of a cross-section of an alarm device is illustrated in Fig. 21. An n-type transistor (519) having an element isolation region (403) on a p-type semiconductor substrate (401), a gate insulating film (407), a gate electrode (409), an n-type impurity region (411a), and an n-type impurity region (411b) is formed. The n-type transistor (519) is formed using a semiconductor such as single crystal silicon, and is capable of high-speed operation. Therefore, a volatile memory section of a CPU capable of high-speed access can be formed. In addition, an insulating film (415) and an insulating film (417) are formed over the n-type transistor (519).

In addition, a contact plug (419a) and a contact plug (419b) are formed in an opening portion by selectively etching a portion of an insulating film (415) and an insulating film (417), and an insulating film (421) having a groove portion is formed on the insulating film (417) and the contact plug (419a) and the contact plug (419b). In addition, a wiring (423a) and a wiring (423b) are formed in the groove portion of the insulating film (421). In addition, an insulating film (420) is formed on the insulating film (421), the wiring (423a) and the wiring (423b) by a sputtering method, a CVD method, or the like, and an insulating film (422) having a groove portion is formed on the insulating film (420). An electrode (424) is formed in the groove portion of the insulating film (422). Electrode (424) is an electrode that functions as a back gate electrode of the second transistor (517). By forming such electrode (424), the threshold voltage of the second transistor (517) can be controlled.

Additionally, an insulating film (425) is formed on the insulating film (422) and the electrode (424) by a sputtering method, a CVD method, or the like.

On the insulating film (425), a second transistor (517) and a photoelectric conversion element (514) are formed. The second transistor (517) includes a multilayer film (206) including an oxide semiconductor film (206a) and an oxide film (206b), a source electrode (216a), a drain electrode (216b) in contact with the multilayer film (206), a gate insulating film (212), a gate electrode (204), and a protective insulating film (218). In addition, an insulating film (445) covering the photoelectric conversion element (514) and the second transistor (517) is formed, and a wiring (449) is formed in contact with the drain electrode (216b) on the insulating film (445). Wiring (449) functions as a node that electrically connects the drain electrode of the second transistor (517) and the gate electrode (409) of the n-type transistor (519).

The light sensor (511) includes a photoelectric conversion element (514), a capacitive element, a first transistor, a second transistor (517), a third transistor, and an n-type transistor (519). Here, as the photoelectric conversion element (514), a photodiode or the like can be used, for example.

One end of a terminal of a photoelectric conversion element (514) is electrically connected to a low-potential power line (VSS), and the other end of the terminal is electrically connected to one end of a source electrode and a drain electrode of a second transistor (517). A charge accumulation control signal (Tx) is supplied to a gate electrode of the second transistor (517), and the other end of the source electrode and the drain electrode is electrically connected to one end of a pair of electrodes of a capacitor element, one end of the source electrode and the drain electrode of the first transistor, and the gate electrode of an n-type transistor (519) (hereinafter, this node may be referred to as a node (FD)). The other end of the pair of electrodes of the capacitor element is electrically connected to a low-potential power line (VSS). A reset signal (Res) is supplied to a gate electrode of the first transistor, and the other end of the source electrode and the drain electrode is electrically connected to a high-potential power line (VDD). One side of the source electrode and the drain electrode of the n-type transistor (519) is electrically connected to one side of the source electrode and the drain electrode of the third transistor and to the amplifier (512). In addition, the other side of the source electrode and the drain electrode of the n-type transistor (519) is electrically connected to a high-potential power line (VDD). A bias signal (Bias) is supplied to the gate electrode of the third transistor, and the other side of the source electrode and the drain electrode is electrically connected to a low-potential power line (VSS).

In addition, it is not necessary to form a capacitive element, and for example, in the case where the parasitic capacitance of an n-type transistor (519) or the like is sufficiently large, a configuration in which a capacitive element is not formed may be used.

In addition, it is preferable to use transistors having a very low off-state current for the first transistor and the second transistor (517). In addition, as a transistor having a very low off-state current, it is preferable to use a transistor using a multilayer film including the oxide semiconductor film described above. By using such a configuration, it is possible to maintain the potential of the node (FD) for a long period of time.

In addition, the configuration illustrated in Fig. 21 is electrically connected to a second transistor (517), and a photoelectric conversion element (514) is formed on an insulating film (425).

The photoelectric conversion element (514) has a semiconductor film (260) formed on an insulating film (425) and a source electrode (216a) and an electrode (216c) of a second transistor (517) formed in contact with the semiconductor film (260). The source electrode (216a) is an electrode that functions as a source electrode or drain electrode of the second transistor (517) and electrically connects the photoelectric conversion element (514) and the second transistor (517).

A gate insulating film (212), a protective insulating film (218), and an insulating film (445) are formed on the semiconductor film (260), the source electrode (216a) and the electrode (216c) of the second transistor (517). In addition, a wiring (456) is formed on the insulating film (445), and is in contact with the electrode (216c) through an opening formed in the gate insulating film (212), the protective insulating film (218), and the insulating film (445).

The electrode (216c) can be formed in the same process as the source electrode (216a) and drain electrode (216b) of the second transistor (517) and the wiring (456) can be formed in the same process as the wiring (449).

As the semiconductor film (260), it is preferable to form a semiconductor film capable of performing photoelectric conversion, and for example, silicon or germanium can be used. If silicon is used for the semiconductor film (260), it functions as a light sensor that detects visible light. In addition, since the wavelengths of electromagnetic waves that can be absorbed by silicon and germanium are different, if germanium is used for the semiconductor film (260), it can be used as a sensor that detects infrared rays.

As described above, since the detection unit (509) including the light sensor (511) can be built into the microcomputer (500), the number of parts can be reduced and the housing of the alarm device can be reduced.

In a fire alarm including the IC chip described above, a CPU (505) is used that combines multiple circuits using the transistors described above and mounts them on a single IC chip.

3-3. CPU

Figure 22 is a block diagram showing a specific configuration of a CPU that uses at least some of the transistors described above.

The CPU illustrated in Fig. 22(A) has, on a substrate (1190), an ALU (1191) (ALU: Arithmetic logic unit, logic operation circuit), an ALU controller (1192), an instruction decoder (1193), an interrupt controller (1194), a timing controller (1195), a register (1196), a register controller (1197), a bus interface (1198) (Bus I/F), a rewritable ROM (1199), and a ROM interface (1189) (ROM I/F). The substrate (1190) uses a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM (1199) and the ROM interface (1189) may be formed on different chips. Of course, the CPU illustrated in Fig. 22(A) is merely an example that illustrates the configuration in a simplified manner, and an actual CPU has various configurations depending on its purpose.

A command input to the CPU through the bus interface (1198) is input to the instruction decoder (1193), decoded, and then input to the ALU controller (1192), interrupt controller (1194), register controller (1197), and timing controller (1195).

The ALU controller (1192), the interrupt controller (1194), the register controller (1197), and the timing controller (1195) perform various controls based on the decoded instructions. Specifically, the ALU controller (1192) generates a signal for controlling the operation of the ALU (1191). In addition, the interrupt controller (1194) judges and processes an interrupt request from an external input/output device or a peripheral circuit based on its priority or mask status during program execution of the CPU. The register controller (1197) generates an address of the register (1196) and reads or writes the register (1196) according to the CPU status.

In addition, the timing controller (1195) generates signals that control the timing of operations of the ALU (1191), the ALU controller (1192), the instruction decoder (1193), the interrupt controller (1194), and the register controller (1197). For example, the timing controller (1195) has an internal clock generation unit that generates an internal clock signal (CLK2) based on a reference clock signal (CLK1), and supplies the internal clock signal (CLK2) to the various circuits described above.

In the CPU shown in Fig. 22(A), a memory cell is formed in a register (1196). The transistor described above can be used as the memory cell of the register (1196).

In the CPU shown in Fig. 22(A), the register controller (1197) selects a retention operation in the register (1196) according to an instruction from the ALU (1191). That is, it selects whether to retain data by a flip-flop or by a capacitive element in the memory cell that the register (1196) has. If retention of data by a flip-flop is selected, power voltage is supplied to the memory cell in the register (1196). If retention of data in the capacitive element is selected, data is rewritten to the capacitive element, and the supply of power voltage to the memory cell in the register (1196) can be stopped.

As for power outage, it can be performed by forming a switching element between the memory cell group and the node to which the power potential (VDD) or the power potential (VSS) is supplied, as shown in Fig. 22(B) or Fig. 22(C). The circuits of Fig. 22(B) and Fig. 22(C) are described below.

Figures 22(B) and 22(C) are memory devices using the transistor described above as a switching element that controls the supply of power potential to the memory cell.

The memory device illustrated in Fig. 22(B) has a memory cell group (1143) having a plurality of switching elements (1141) and memory cells (1142). Specifically, the transistor described above can be used for each memory cell (1142). A high-level power supply potential (VDD) is supplied to each memory cell (1142) included in the memory cell group (1143) through the switching element (1141). In addition, a signal (IN) potential and a low-level power supply potential (VSS) potential are provided to each memory cell (1142) included in the memory cell group (1143).

In Fig. 22(B), the transistor described above is used as a switching element (1141), and the switching of this transistor is controlled by a signal (SigA) given to its gate electrode layer.

In addition, in Fig. 22(B), a configuration in which the switching element (1141) has only one transistor is illustrated, but it is not particularly limited and may have multiple transistors. When the switching element (1141) has multiple transistors that function as switching elements, the multiple transistors may be connected in parallel, in series, or in a combination of series and parallel.

In addition, in Fig. 22(B), the supply of a high-level power supply potential (VDD) to each memory cell (1142) of a memory cell group (1143) is controlled by the switching element (1141), but the supply of a low-level power supply potential (VSS) may be controlled by the switching element (1141).

In addition, Fig. 22(C) illustrates an example of a memory device in which a low-level power supply potential (VSS) is supplied to each memory cell (1142) of a memory cell group (1143) through a switching element (1141). The supply of a low-level power supply potential (VSS) to each memory cell (1142) of a memory cell group (1143) can be controlled by the switching element (1141).

By forming a switching element between a memory cell group and a node to which a power potential (VDD) or a power potential (VSS) is supplied, the operation of the CPU can be temporarily stopped, and data can be retained even when the supply of the power voltage is stopped, and power consumption can be reduced. Specifically, for example, even while a user of a personal computer stops inputting information with an input device such as a keyboard, the operation of the CPU can be stopped, and power consumption can be reduced.

Here, the CPU is used as an example, but it can also be applied to LSIs such as DSP (Digital Signal Processor), custom LSI, and FPGA (Field Programmable Gate Array).

3-4. Installation example

In Fig. 23(A), the alarm device (8100) is a residential fire alarm and has a detection unit and a microcomputer (8101). The microcomputer (8101) includes a CPU using the transistor described above.

In Fig. 23(A), an air conditioner having an indoor unit (8200) and an outdoor unit (8204) includes a CPU using the transistor described above. Specifically, the indoor unit (8200) has a housing (8201), an air vent (8202), a CPU (8203), etc. In Fig. 23(A), the case where the CPU (8203) is formed in the indoor unit (8200) is exemplified, but the CPU (8203) may be formed in the outdoor unit (8204). Alternatively, the CPU (8203) may be formed on both the indoor unit (8200) and the outdoor unit (8204). By including the CPU using the transistor described above, the power of the air conditioner can be saved.

In Fig. 23(A), the electric refrigerator-freezer (8300) includes a CPU using the transistor described above. Specifically, the electric refrigerator-freezer (8300) has a housing (8301), a refrigerator door (8302), a freezer door (8303), a CPU (8304), etc. In Fig. 23(A), the CPU (8304) is formed inside the housing (8301). By including the CPU using the transistor described above, the power of the electric refrigerator-freezer (8300) can be saved.

In Fig. 23(B) and Fig. 23(C), an example of an electric vehicle is shown. An electric vehicle (9700) is equipped with a secondary battery (9701). The power of the secondary battery (9701) is controlled by a control circuit (9702) and supplied to a driving device (9703). The control circuit (9702) is controlled by a processing device (9704) having a ROM, RAM, CPU, etc. (not shown). By including a CPU using the transistor described above, the power of the electric vehicle (9700) can be saved.

The driving device (9703) is configured by a DC motor or an AC motor unit, or a combination of a motor and an internal combustion engine. The processing device (9704) outputs a control signal to the control circuit (9702) based on input information such as the driver's operation information (acceleration, deceleration, stop, etc.) of the electric vehicle (9700) or information during driving (information on uphill or downhill roads, information on the load applied to the driving wheels, etc.). The control circuit (9702) adjusts the electric energy supplied from the secondary battery (9701) and controls the output of the driving device (9703) by the control signal of the processing device (9704). In the case where an AC motor is mounted, an inverter that converts DC to AC is also built in, although not shown.

[Example 1]

In this embodiment, the etching speed when an oxide semiconductor film is wet etched and the shape of the side surface of the oxide semiconductor film are explained using FIGS. 24 to 30.

First, the types and etching rates of oxide semiconductor films and etching solutions, respectively, are explained.

Below, the manufacturing methods of Sample 1 and Sample 2 are described.

An oxide semiconductor film was deposited on a glass substrate. Sample 1 has an In-Ga-Zn oxide film having a thickness of 100 nm formed on a glass substrate using a sputtering target of a metal oxide having In:Ga:Zn = 1:1:1 (atomic ratio). Sample 2 has an In-Ga-Zn oxide film having a thickness of 100 nm formed on a glass substrate using a sputtering target of a metal oxide having In:Ga:Zn = 1:3:2 (atomic ratio).

As the conditions for forming the In-Ga-Zn oxide film in Sample 1, the sputtering target was set to an In:Ga:Zn = 1:1:1 (atomic ratio) target, argon at a flow rate of 50 sccm and oxygen at a flow rate of 50 sccm were supplied as sputtering gases into the reaction chamber of the sputtering device, the pressure inside the reaction chamber was controlled to 0.6 Pa, and a direct current power of 5 kW was supplied. In addition, the substrate temperature when forming the In-Ga-Zn oxide film was set to 170°C.

As the conditions for forming the In-Ga-Zn oxide film in Sample 2, the sputtering target was set to an In:Ga:Zn=1:3:2 (atomic ratio) target, 90 sccm of Ar and 10 sccm of oxygen were supplied as sputtering gases into the reaction chamber of the sputtering device, the pressure inside the reaction chamber was controlled to 0.3 Pa, and 5 kW of DC power was supplied. In addition, the substrate temperature when forming the In-Ga-Zn oxide film was set to 100°C.

Next, the In-Ga-Zn oxide films formed on Samples 1 and 2 were wet-etched. In this wet-etching process, one of the first to third etching solutions was used. As the first etching solution, 85 wt% phosphoric acid at 25°C was used. As the second etching solution, an oxalic acid-based aqueous solution at 60°C (for example, ITO-07N (aqueous solution containing 5 wt% or less oxalic acid) manufactured by Kanto Chemical Co., Inc.) was used. As the third etching solution, a phosphoric acid-based aqueous solution at 30°C (for example, a mixed-acid aluminum solution manufactured by Wako Pure Chemical Industries (aqueous solution containing 72 wt% phosphoric acid, 2 wt% nitric acid, and 9.8 wt% acetic acid)) was used.

Next, the relationship between each etching solution and the etching rate in Sample 1 and Sample 2 is shown in Figure 24.

As illustrated in Fig. 24, sample 1 having an In-Ga-Zn oxide film (represented as In-Ga-Zn-O(111)) formed using In:Ga:Zn = 1:1:1 (atomic ratio) as a sputtering target can be seen to have a fast etching rate in etching using an oxalic acid aqueous solution as the second etchant.

Meanwhile, sample 2 having an In-Ga-Zn oxide film (represented as In-Ga-Zn-O(132)) formed using In:Ga:Zn=1:3:2 (atomic ratio) as a sputtering target can be seen to have an etching rate of the same degree in all etchants.

Next, the shape of the side surface of the oxide semiconductor film when the oxide semiconductor film having a laminated structure is etched using one of the first to third etching solutions will be described.

Below, the manufacturing method of Samples 3 and 4 is described. In addition, Samples 3 and 4 have a two-layer structure in which a first In-Ga-Zn oxide film and a second In-Ga-Zn oxide film are laminated.

A laminated oxide semiconductor film was deposited on a glass substrate. First, a first In-Ga-Zn oxide film having a thickness of 35 nm was deposited on a glass substrate using a sputtering target of a metal oxide having an atomic ratio of In:Ga:Zn = 1:1:1. Next, a second In-Ga-Zn oxide film having a thickness of 20 nm was deposited using a sputtering target of a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:2.

In addition, the first In-Ga-Zn oxide film is a film formed using the same film formation conditions as the In-Ga-Zn oxide film of sample 1. In addition, the second In-Ga-Zn oxide film is a film formed using the same film formation conditions as the In-Ga-Zn oxide film of sample 2.

Next, the oxide semiconductor film of the laminated structure was etched. Sample 3 used 85 wt% phosphoric acid at 25°C as the first etchant. Sample 4 used 30°C phosphoric acid aqueous solution as the third etchant.

Next, the manufacturing method of sample 5 is described. In addition, sample 5 has a three-layer structure in which the first In-Ga-Zn oxide film to the third In-Ga-Zn oxide film are laminated.

On a glass substrate, a silicon nitride film and a silicon oxynitride film were deposited by the CVD method. Next, a laminated oxide semiconductor film was deposited on the silicon oxynitride film. Next, a first In-Ga-Zn oxide film having a thickness of 5 nm was deposited on the silicon oxynitride film using a sputtering target of a metal oxide having an In:Ga:Zn ratio of 1:3:2 (atomic ratio). Next, a second In-Ga-Zn oxide film having a thickness of 20 nm was deposited using a sputtering target of a metal oxide having an In:Ga:Zn ratio of 3:1:2 (atomic ratio). Next, a third In-Ga-Zn oxide film having a thickness of 20 nm was deposited using a sputtering target of a metal oxide having an In:Ga:Zn ratio of 1:1:1 (atomic ratio). Next, a silicon oxynitride film was deposited on the third In-Ga-Zn oxide film using the CVD method.

In addition, the first In-Ga-Zn oxide film in sample 5 was formed using the conditions that the sputtering target was an In:Ga:Zn=1:3:2 (atomic ratio) target, 90 sccm of Ar and 10 sccm of oxygen were supplied as sputtering gases into the reaction chamber of the sputtering device, the pressure inside the reaction chamber was controlled to 0.6 Pa, and 5 kW of DC power was supplied. The second In-Ga-Zn oxide film was formed using the conditions that the sputtering target was an In:Ga:Zn=3:1:2 (atomic ratio) target, 50 sccm of Ar and 50 sccm of oxygen were supplied as sputtering gases into the reaction chamber of the sputtering device, the pressure inside the reaction chamber was controlled to 0.6 Pa, and 5 kW of DC power was supplied. The third In-Ga-Zn oxide film was formed using the conditions of using a sputtering target of In:Ga:Zn = 1:1:1 (atomic ratio), supplying 100 sccm of oxygen as a sputtering gas into the reaction chamber of the sputtering device, controlling the pressure inside the reaction chamber to 0.6 Pa, and supplying 5 kW of direct current power. In addition, the substrate temperature when forming the first to third In-Ga-Zn oxide films was set to 170°C.

Next, the oxide semiconductor film of the laminated structure was etched. Sample 5 used an oxalic acid aqueous solution at 60°C as the second etchant.

Next, the manufacturing method of sample 6 is described. In addition, sample 6 has a two-layer structure in which a first In-Ga-Zn oxide film and a second In-Ga-Zn oxide film are laminated.

On a glass substrate, a silicon oxynitride film was deposited by the CVD method. Next, on the silicon oxynitride film, using the same deposition conditions as Samples 3 and 4, a first In-Ga-Zn oxide film having a thickness of 35 nm was deposited using a sputtering target of a metal oxide having an In:Ga:Zn ratio of 1:1:1 (atomic ratio), and then a second In-Ga-Zn oxide film having a thickness of 20 nm was deposited using a sputtering target of a metal oxide having an In:Ga:Zn ratio of 1:3:2 (atomic ratio). Next, a silicon oxynitride film was deposited on the second In-Ga-Zn oxide film.

Next, the oxide semiconductor film having a laminated structure was etched. Sample 6 had the oxide semiconductor film having a laminated structure etched using a dry etching method. In addition, BCl ₃ was used as an etching gas.

Next, the cross-sectional shapes of samples 3 to 6 were observed using STEM (Scanning Transmission Electron Microscopy).

A phase contrast image (TE image) of Sample 3 at a magnification of 200,000 times is shown in Fig. 25(A), and a schematic diagram of Fig. 25(A) is shown in Fig. 25(B). In addition, a Z contrast image (ZC image) of Sample 3 at a magnification of 150,000 times is shown in Fig. 26.

A phase contrast image (TE image) of Sample 4 at a magnification of 200,000 times is shown in Fig. 27(A), and a schematic diagram of Fig. 27(A) is shown in Fig. 27(B).

A phase contrast image (TE image) of Sample 5 at a magnification of 150,000 times is shown in Fig. 28(A), and a schematic diagram of Fig. 28(A) is shown in Fig. 28(B). In order to explain the details near the side surface of the oxide semiconductor film of the laminated structure in Sample 5, a Z contrast image (ZC image) of Sample 5 at a magnification of 150,000 times is shown in Fig. 29(A), and a schematic diagram of Fig. 29(A) is shown in Fig. 29(B).

A phase contrast image (TE image) of Sample 6 at a magnification of 150,000 times is shown in Fig. 30(A), and a schematic diagram of Fig. 30(A) is shown in Fig. 30(B).

As illustrated in Fig. 25(B), in sample 3, a first In-Ga-Zn oxide film (803) is formed on a glass substrate (801). A second In-Ga-Zn oxide film (805) is formed on the first In-Ga-Zn oxide film (803). A resist (807) is formed on the second In-Ga-Zn oxide film (805).

In addition, as illustrated in Fig. 26, in sample 3, the boundary between the first In-Ga-Zn oxide film (803) and the second In-Ga-Zn oxide film (805) can be identified by the difference in their thickness. That is, in the transistor which is one embodiment of the present invention, even when the oxide semiconductor film and the oxide film contain common elements, the boundary between the two can be identified by the difference in their compositions.

As illustrated in Fig. 27(B), in sample 4, a first In-Ga-Zn oxide film (813) is formed on a glass substrate (811). A second In-Ga-Zn oxide film (815) is formed on the first In-Ga-Zn oxide film (813). A resist (817) is formed on the second In-Ga-Zn oxide film (815).

In Samples 3 and 4, the angle between the side surfaces of the glass substrate (801), the glass substrate (811), and the first In-Ga-Zn oxide film (803), the first In-Ga-Zn oxide film (813) is taken as angle (θ1). The angle between the interfaces of the first In-Ga-Zn oxide film (803), the first In-Ga-Zn oxide film (813), and the second In-Ga-Zn oxide film (805), the second In-Ga-Zn oxide film (815) and the side surfaces of the second In-Ga-Zn oxide film (805), the second In-Ga-Zn oxide film (815) is taken as angle (θ2). As illustrated in FIGS. 25 and 27, it can be seen that in Samples 3 and 4, the angle (θ2) is larger than the angle (θ1).

As illustrated in Fig. 28(B), in sample 5, a silicon oxynitride film (823) is formed on a silicon nitride film (821). A laminated oxide semiconductor film (825) is formed on the silicon oxynitride film (823). A silicon oxynitride film (827) is formed on the silicon oxynitride film (823) and the oxide semiconductor film (825) of the laminated structure. In addition, a low-density region (829) is formed on the silicon oxynitride film (827).

In sample 5, the angle between the interface of the silicon oxynitride film (823) and the oxide semiconductor film (825) of the laminated structure and the side surface of the oxide semiconductor film (825) of the laminated structure is taken as angle (θ3). As illustrated in Fig. 29(B), in sample 5, the angle (θ3) is an obtuse angle. In addition, since the ZC phase has a different contrast due to the difference in atomic number, it can be seen that a film (826) having a different composition from the oxide semiconductor film is formed on the side surface of the oxide semiconductor film (825) of the laminated structure. As a result of analyzing this film (826) by energy dispersive X-ray spectrometry (EDX), it was found that it contained tungsten.

As illustrated in Fig. 30(B), in sample 6, a silicon nitride oxide film (833) is formed on a glass substrate (831). A laminated oxide semiconductor film (835) is formed on the silicon nitride oxide film (833). A silicon nitride oxide film (837) is formed on the silicon nitride oxide film (833) and the laminated oxide semiconductor film (835).

In sample 6, the angle between the interface of the silicon nitride film (833) and the oxide semiconductor film (835) of the laminated structure and the side surface of the oxide semiconductor film (835) of the laminated structure is taken as angle (θ4). As illustrated in Fig. 30(B), in sample 6, the angle (θ4) does not change depending on the position of the side surface of the oxide semiconductor film and is almost the same.

From the above, it can be seen that, by using a wet etching method using phosphoric acid or a phosphoric acid-based aqueous solution as an etching solution, in a layered oxide semiconductor film, the angle (θ1) between the side surface of the In-Ga-Zn oxide film formed using In:Ga:Zn = 1:1:1 (atomic ratio) as a sputtering target and the interface of the underlying film of the In-Ga-Zn oxide film can be made smaller than the angle (θ2) between the side surface of the In-Ga-Zn oxide film formed using In:Ga:Zn = 1:3:2 (atomic ratio) as a sputtering target and the interface of the underlying film of the In-Ga-Zn oxide film.

100 : Substrate
104 : Gate electrode
106 : Multilayer film
106a: Oxide semiconductor film
106b: oxide film
106c: Low resistance area
106d: Low resistance area
107 : Oxide film
112 : Gate Insulator
113 : Step
116a : Source electrode
116b : Drain electrode
117 : Oxide film
118 : Protective insulation film
118a: Silicon oxide film
118b: Silicon oxide film
118c: Silicon nitride film
126a: Oxide semiconductor film
126b : Oxide film
200 : Substrate
202 : Lower insulation film
204 : Gate electrode
206 : Multilayer film
206a: Oxide semiconductor film
206b: oxide film
206c: oxide film
206d: Low resistance area
206e: Low resistance area
207 : Oxide film
212 : Gate Insulator
212a : Source electrode
212b : Drain electrode
213 : Step
214 : Step
216a : Source electrode
216b : Drain electrode
216c : Electrode
218 : Protective insulation film
226a: Oxide semiconductor film
226b: oxide film
226c : Oxide film
260 : Semiconductor film
401: Semiconductor substrate
403: Element isolation area
407: Gate Insulator
409: Gate electrode
411a : Impurity area
411b: Impurity area
415 : Insulating film
417 : Insulating film
419 : Transistor
419a : Contact plug
419b : Contact plug
420 : Insulating film
421 : Insulating film
422 : Insulating film
423a : Wiring
423b : Wiring
424 : Electrode
425 : Insulating film
445 : Insulating film
449 : Wiring
456 : Wiring
500 : Microcomputer
501 : DC power supply
502 : Bus line
503 : Power Gate Controller
504 : Power Gate
505 : CPU
506: Volatile memory
507: Non-volatile memory
508 : Interface
509 : Detection Unit
511 : Light sensor
512 : Amp
513 : AD converter
514 : Photoelectric conversion element
517 : Transistor
519 : Transistor
530 : Light-emitting element
700 : Substrate
719 : Light-emitting element
720 : Insulating film
721 : Insulating film
731 : Terminal
732 : FPC
733a : Wiring
733b : Wiring
733c : Wiring
734 : Sealing material
735 : Driving circuit
736 : Driving circuit
737 : Pixel
741 : Transistor
742 : Capacitor
743 : Switch element
744 : Signal line
750 : Pixels
751 : Transistor
752 : Capacitor
753 : Liquid crystal element
754 : Injection line
755 : Signal line
781 : Electrode
782 : Light-emitting layer
783 : Electrode
784 : Bulkhead
785a : Middle floor
785b : Middle layer
785c : Mid-level
785d : Mid-level
786a : Emissive layer
786b : Emissive layer
786c : Emitting layer
791 : Electrode
792 : Insulating film
793: Liquid crystal layer
794 : Insulating film
795 : Spacer
796 : Electrode
797 : Substrate
801 : Glass substrate
803: In-Ga-Zn oxide film
805: In-Ga-Zn oxide film
807 : Register
811 : Glass substrate
813: In-Ga-Zn oxide film
815: In-Ga-Zn oxide film
817 : Register
821: Silicon nitride film
823: Silicon nitride oxide film
825: Oxide semiconductor film
826 : End
827: Silicon nitride oxide film
829: Low density area
831 : Glass substrate
833: Silicon nitride oxide film
835: Oxide semiconductor film
837: Silicon nitride oxide film
1141 : Switching element
1142 : Memory Cell
1143 : Memory cell group
1189 : ROM Interface
1190 : Substrate
1191 : ALU
1192 : ALU Controller
1193: Instruction Decoder
1194 : Interrupt Controller
1195 : Timing Controller
1196 : Register
1197 : Register Controller
1198 : Bus Interface
1199 : ROM
8100 : Alarm device
8101 : Microcomputer
8200 : Indoor unit
8201 : Housing
8202 : Vent
8203 : CPU
8204 : Outdoor unit
8300 : Electric Freezer Refrigerator
8301 : Housing
8302 : Refrigerator door
8303 : Freezer door
8304 : CPU
9700 : Electric Vehicle
9701 : Secondary battery
9702 : Control circuit
9703 : Drive Unit
9704 : Processing Unit

Claims (5)

As a semiconductor device,
gate electrode;
An insulating surface on the gate electrode;
A first oxide film comprising indium and located on and in contact with the insulating surface;
A second oxide film over the first oxide film and in contact with the first oxide film, the second oxide film containing indium;
A conductive film which is on the upper surface of the second oxide film and in contact with the upper surface of the second oxide film and in contact with the side surface of the first oxide film and the side surface of the second oxide film;
A silicon oxide film on the second oxide film and the conductive film; and
A silicon nitride film is included on the silicon oxide film and in contact with the silicon oxide film.
When viewed in cross-section, the length of the side surface of the first oxide film is greater than the length of the side surface of the second oxide film,
A semiconductor device and a method for manufacturing the same, wherein the thickness of the silicon oxide film is greater than the thickness of the silicon nitride film. As a semiconductor device,
gate electrode;
An insulating surface on the gate electrode;
A first oxide film comprising indium and gallium on and in contact with the insulating surface;
A second oxide film over the first oxide film and in contact with the first oxide film, the second oxide film containing indium and gallium;
A conductive film which is on the upper surface of the second oxide film and in contact with the upper surface of the second oxide film and in contact with the side surface of the first oxide film and the side surface of the second oxide film;
A silicon oxide film on the second oxide film and the conductive film; and
A silicon nitride film is included on the silicon oxide film and in contact with the silicon oxide film.
When viewed in cross-section, the length of the side surface of the first oxide film is greater than the length of the side surface of the second oxide film,
A semiconductor device and a method for manufacturing the same, wherein the thickness of the silicon oxide film is greater than the thickness of the silicon nitride film. As a semiconductor device,
gate electrode;
An insulating surface on the gate electrode;
A first oxide film comprising indium, gallium and zinc, which is on the insulating surface and in contact with the insulating surface;
A second oxide film over the first oxide film and in contact with the first oxide film, the second oxide film containing indium, gallium and zinc;
A conductive film which is on the upper surface of the second oxide film and in contact with the upper surface of the second oxide film and in contact with the side surface of the first oxide film and the side surface of the second oxide film;
A silicon oxide film on the second oxide film and the conductive film; and
A silicon nitride film is included on the silicon oxide film and in contact with the silicon oxide film.
When viewed in cross-section, the length of the side surface of the first oxide film is greater than the length of the side surface of the second oxide film,
A semiconductor device and a method for manufacturing the same, wherein the thickness of the silicon oxide film is greater than the thickness of the silicon nitride film. In any one of claims 1 to 3,
A semiconductor device, wherein the first oxide film is crystalline. In any one of claims 1 to 3,
A semiconductor device and a method for manufacturing the same, wherein the taper angle of the second oxide film is larger than the taper angle of the first oxide film.