KR20240071845A - Transmitter for transmitting data in ultra high speed using pll - Google Patents

Abstract

A transmitter for ultra-high-speed data transmission and reception using a phase-locked loop according to the present invention includes a first phase-locked loop for outputting a multiplied reference frequency that is a predetermined multiplied reference frequency; a clock recovery unit for recovering a clock of the reference frequency using the multiplied reference frequency output from the first phase locked loop; a second phase locked loop for receiving the multiplied reference frequency and outputting a predetermined multiplied local reference frequency; and an amplification/filtering unit for amplifying and filtering the local reference frequency output from the second phase locked loop.

Description

Transmitter for ultra-high-speed data transmission and reception using a phase-locked loop {TRANSMITTER FOR TRANSMITTING DATA IN ULTRA HIGH SPEED USING PLL}

The present invention relates to a transmitter for transmitting and receiving data, and more specifically, to a transmitter capable of transmitting and receiving data at ultra-high speeds using a plurality of phase-locked loops.

Transmitters and receivers for communications systems are designed to transmit and receive one of many signals, which typically have bandwidths that vary widely and can fall within a specific frequency range. It will be clear to those skilled in the art that these transmitters and receivers each emit or block electron radiation within a desired frequency band. Electromagnetic radiation may be output from or input into a transmitter or receiver, respectively, by various types of devices, including antennas, waveguides, coaxial cables, and optical fibers.

These communication system transmitters and receivers are capable of transmitting and receiving multiple signals, but such transmitters and receivers typically have different frequencies or bandwidths and utilize duplicate circuitry for each signal to be transmitted and received. This circuit replication is not the best optical multi-channel communication unit design structure due to the added cost and complexity associated with forming a completely independent transmitter and/or receiver for each communication channel.

Alternative transmitter and receiver structures are possible that can transmit and/or receive signals having the desired multi-channel optical bandwidth. These alternative transmitters and receivers operate at a sampling rate high enough to allow signals of the desired bandwidth to be digitized according to the Nyquist decision (e.g., digitized at a sampling rate equal to at least twice the bandwidth to be digitized). A digitizer (eg, analog-to-digital converter) may be used. Subsequently, the digitized signal is pre- or post-processed using digital signal processing techniques to differentiate between multiple channels within the digitized bandwidth.

1 shows a prior art transceiver 100. Radio frequency (RF) signals are received at antenna 102, processed through RF converter 104, and digitized by analog-to-digital converter 106. The digitized signal is processed through a distributed Fourier transform (DFT) 108 and a channel processor 110 from the channel processor 110 to the cellular network and public switched telephone network (PSTN). For both transmissions, signals received from the cellular network are processed through a channel processor 110, an inverse distributed Fourier transformer (IDFT) 114, and a digital-to-analog converter 116.

The analog signal from digital-to-analog converter 116 is converted in RF up converter 118 and radiated from antenna 120.

A disadvantage of this alternative type of communication unit is that the digital processing portion of the communication unit is such that the Nyquist judgment is met for a maximum bandwidth of received electromagnetic radiation equal to the sum of the individual communication channels forming the composite received electromagnetic radiation bandwidth. The point is that it must have a sufficiently high sampling rate to do this. If the composite bandwidth signal is wide enough, the digital processing portion of the communication unit can be very expensive and consume significant amounts of power. Additionally, channels developed by DFT or IDFT filtering techniques typically must be adjacent to each other.

As described above, a need exists for transmitters and receivers, such as transmitters and receivers, that are capable of transmitting and receiving multiple signals within corresponding channels with the same transmitter and receiver circuitry. However, it is desirable for such transmitter and receiver circuits to reduce constraints on communication unit design associated with the transceiver structures. If such a transmitter and receiver structure were developed, it would be ideally suited for wireless telephony systems. Base stations typically need to transmit and receive multiple channels within a wide frequency bandwidth. Likewise, such multi-channel transmitter and receiver structures would be well suited to personal communications systems that would have narrow service areas (rather than their opposing service areas) for each base station, such that a corresponding number of base stations would be needed to cover a given geographic area. will be. Operators purchasing base stations would ideally want to have units that are less complex and less expensive to install through their licensed service area. Traditional communication units are designed to operate under single information signal coding and channelization standards. In contrast, these multi-channel communication units can be reprogrammed at will, either via software during manufacturing processing or in the field after installation, to enable these multi-channel communication units to operate according to any of a variety of information signal codings and standards. Includes digital signal processing part.

Registered Patent No. 10-0199316 Multi-channel digital transceiver and method Registered Patent No. 10-0574605 Transmission system and method

The present invention is able to correct the collapse of the clock that occurs when multiplication to ultra-high frequencies by placing a clock recovery unit between a plurality of phase-locked loops using a voltage-controlled oscillator and a plurality of phase-locked loops, thereby converting a predetermined reference signal to an ultra-high frequency. The purpose is to provide a transmitter that can transmit and receive data at ultra-high speeds by multiplying it with a local reference signal.

The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A transmitter for ultra-high-speed data transmission and reception using a phase-locked loop according to the present invention includes a first phase-locked loop for outputting a first multiplied reference frequency of an input reference frequency; a clock recovery unit for recovering a clock of the reference frequency using the multiplied reference frequency output from the first phase locked loop; a second phase locked loop for receiving the multiplied reference frequency and outputting a second multiplied local reference frequency; and an amplification/filtering unit for amplifying and filtering the local reference frequency output from the second phase locked loop.

Preferably, the first phase locked loop is a first phase detector that compares the reference frequency and the first divided signal and outputs an up signal and a down signal that change depending on the phase difference between the reference frequency and the first divided signal. ; a first charge pump that repeatedly turns on and off according to changes in the up and down signals output from the first phase detector and charges and discharges the load capacity on the output side; a first loop filter implemented with a resistor and a capacitor to filter the signal output from the first charge pump; a first operational amplifier that receives a predetermined reference voltage and the output of the first loop filter and amplifies it; A first voltage controlled oscillator that outputs a first oscillation frequency using the output voltage of the first operational amplifier - The first voltage controlled oscillator is implemented as a two-stage differential ring oscillator and produces four phase signals each with a phase difference of 90 degrees. Print box - ; and a first divider that divides the phase signal output from the first voltage controlled oscillator to output a first divided signal.

Preferably, when receiving four phase signals output from the first voltage controlled oscillator, each having a phase difference of 90 degrees, a phase interpolator interpolates the phase signals according to the output of the DA converter below; an up/down detector that compares the reference frequency and the output of the phase interpolator and generates high-speed up/down pulses; Up/down filters that convert high-speed up/down pulses output from the up/down detector into low-speed up/down commands; DAC control logic that generates commands to control the DA converter; and a DA converter that converts the digital command output from the DAC control logic into an analog value and outputs it.

Preferably, the up/down filter is a ripple counter.

Preferably, the amplification/filtering unit includes: an amplifier that amplifies the output level of the second voltage controlled oscillator in the second phase locked loop; a band-pass filter for removing unwanted waves from the output of the amplifier; a frequency doubler that doubles the frequency output from the band-pass filter and outputs the multiplied local reference frequency; An active device that combines the downward frequency and local reference frequency applied from one side to output the upward frequency and local reference frequency to the other side, and combines the upward frequency and local reference frequency applied from the other side to output the downward frequency and local reference frequency to one side. mixer; a low-pass filter that passes a downstream frequency output from the active mixer and a local reference frequency and blocks the local reference frequency; and a cavity filter that passes the upward frequency output from the active mixer and the local reference frequency and blocks the local reference frequency.

According to the transmitter for ultra-high-speed data transmission and reception using a phase-locked loop of the present invention, a clock recovery unit is placed between a plurality of phase-locked loops using a voltage-controlled oscillator and a plurality of phase-locked loops to multiply the clock generated when multiplied to an ultra-high frequency. There is an advantageous effect in that collapse can be straightened and data can be transmitted and received at ultra-high speed by multiplying a predetermined reference signal into an ultra-high frequency local reference signal.

1 is a block diagram of a prior art multi-channel transceiver;
Figure 2 is a circuit diagram of a transmitter for ultra-high-speed data transmission and reception using a phase-locked loop according to an embodiment of the present invention, and
Figure 3 is a detailed diagram of a DA converter and phase interpolator according to an embodiment of the present invention.

Additional objects, features and advantages of the present invention may be more clearly understood from the following detailed description and accompanying drawings.

Prior to a detailed description of the present invention, it should be noted that the present invention is capable of various modifications and may have various embodiments, and the examples described below and shown in the drawings are not intended to limit the present invention to specific embodiments. No, it should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between.

The terms used in this specification are merely used to describe specific embodiments and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that it does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

In addition, terms such as "...unit", "...unit", and "...module" used in the specification refer to a unit that processes at least one function or operation, which is hardware or software or hardware and It can be implemented through a combination of software.

In addition, when describing with reference to the accompanying drawings, identical components will be assigned the same reference numerals regardless of the reference numerals, and overlapping descriptions thereof will be omitted. In describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

Figure 2 is a circuit diagram of a transmitter for ultra-high-speed data transmission and reception using a phase-locked loop according to an embodiment of the present invention.

A transmitter for ultra-high-speed data transmission and reception using a phase-locked loop according to an embodiment of the present invention includes a first phase-locked loop (211, 213, 215, 217, 219, 221), a clock recovery unit (225, 227, 229, 231) ), second phase locking loops (233, 235, 237, 239, 241, 243), and amplification/filtering units (245, 247, 249, 251, 253, 255).

The first phase locked loop (211, 213, 215, 217, 219, 221) is configured to first multiply the input reference frequency (Fref.) and output the multiplied reference frequency, and the first phase detector (211) ), a first charge pump 213, a first loop filter 215, a first operational amplifier 217, a first voltage controlled oscillator 219, and a first divider 221. Here, the first phase locked loop can multiply the reference frequency by 10 times.

Specifically, the first phase detector 211 compares the reference frequency (Fref.) and the first divided signal output from the first divider 221, and changes the frequency according to the phase difference between the reference frequency and the first divided signal. Outputs a signal (UP) and a down signal (DOWN).

The first charge pump 213 repeatedly turns on and off according to changes in the up signal (UP) and down signal (DOWN) output from the first phase detector 211, and charges and discharges the load capacity on the output side.

The first loop filter 215 is implemented with a resistor and a capacitor and filters the signal output from the first charge pump 213.

The first operational amplifier 217 receives the reference voltage (Vref) and the output of loop filter 1 (215) and amplifies it.

The first voltage controlled oscillator 219 outputs a first oscillation frequency using the output voltage of the first operational amplifier 217. Here, the first voltage controlled oscillator 219 can be implemented as a two-stage differential ring oscillator and can output four phase signals, each having a phase difference of 90 degrees.

The first divider 220 divides the phase signal output from the first voltage controlled oscillator 219 and outputs a first divided signal.

The clock recovery units (223, 225, 227, 229, 231) are configured to recover the clock of the input reference frequency (Fref.), and include a phase interpolator (223), an up/down detector (225), and an up/down detector. It includes a filter 227, DAC control logic 229, and DA converter 231.

The phase interpolator 223 receives four phase signals output from the first voltage controlled oscillator 219, each having a phase difference of 90 degrees, and interpolates them according to the DA converter 231. The specific configuration of the phase interpolator 223 will be described in FIG. 3.

The up/down detector 225 compares the reference frequency (Fref.) and the output from the phase interpolator 223 and generates high-speed up/down pulses.

The up/down filter 227 converts the high-speed up/down pulse output from the up/down detector 225 into a low-speed up/down command. For example, the up/down filter 227 can be implemented using a ripple counter that outputs once when input 16 times. This is necessary to minimize power consumption.

The DAC control logic 229 generates commands to control the DA converter 231.

The DA converter 231 converts the digital command output from the DAC control logic 229 into an analog value and outputs it.

The second phase locked loop (233, 235, 237, 239, 241, 243) is configured to receive the multiplied reference frequency (10Fref., 100MHz), multiply it for the second time, and output the multiplied local reference frequency. The second phase It includes a detector 233, a second charge pump 235, a second loop filter 237, a second operational amplifier 239, a second voltage controlled oscillator 241, and a second divider 243. Here, the second phase locked loop can multiply the multiplication reference frequency by 170 times.

The second phase detector 233 compares the multiplication reference frequency (10Fref., 100MHz) and the second divided signal output from the second divider 243, and determines the phase difference between the multiplication reference frequency (10Fref.) and the second divided signal. Outputs an up signal (UP) and a down signal (DOWN) that change depending on the condition.

The second charge pump 235 repeatedly turns on and off according to changes in the up signal (UP) and down signal (DOWN) output from the second phase detector 233, and charges and discharges the load capacity on the output side.

The second loop filter 237 is implemented with a resistor and a capacitor, and filters the signal output from the second charge pump 235.

The second operational amplifier 239 receives the reference voltage (Vref) and the output of the second loop filter 237 and amplifies it.

The second voltage controlled oscillator 241 outputs a second oscillation frequency using the output voltage of the second operational amplifier 239. Here, the second voltage controlled oscillator 241 may be implemented as a two-stage differential ring oscillator, and the second oscillation frequency output from the second voltage controlled oscillator 241 may have a frequency of 17 GHz.

The second divider 243 divides the output of the second voltage controlled oscillator 241 and outputs a second divided signal.

The amplifying/filtering units (245, 247, 249, 251, 253, 255) are configured to amplify and filter the local reference frequency output from the second phase-locked loop, and include an amplifier 245, a band-pass filter 247, It includes a frequency doubler 249, an active mixer 251, a low-pass filter 253, and a cavity filter 255.

The amplifier 245 amplifies the output level of the second voltage controlled oscillator 241.

The band-pass filter 247 removes unwanted waves, such as second harmonic components, from the output of the amplifier 245.

The frequency doubler 249 doubles the frequency output from the band-pass filter 247 and outputs the multiplied local reference frequency. For example, the frequency of 17 GHz output from the band-pass filter 247 is multiplied by the local reference frequency of 34 GHz and output.

The active mixer 251 combines the 3.3GHz frequency and the local reference frequency (34GHz) applied from one side and outputs the 37.3GHz frequency and the local reference frequency (34GHz) to the other side, and the 37.3GHz frequency and the local reference frequency applied from the other side. (34GHz) is combined to output a 3.3GHz frequency and a local reference frequency (34GHz) on one side.

The low-pass filter 253 passes the 3.3 GHz frequency output from the active mixer 251 and the local reference frequency (34 GHz), and blocks the local reference frequency (34 GHz).

The cavity filter 255 passes the 37.3 GHz frequency output from the active mixer 251 and the local reference frequency (34 GHz), and blocks the local reference frequency (34 GHz).

Figure 3 is a detailed diagram of a DA converter and phase interpolator according to an embodiment of the present invention.

According to one embodiment of the present invention, the four phase signals generated by the first voltage-controlled oscillator 219 of the DA converter 231 are supplied to the phase interpolator 223 by the corresponding amplifiers 301, 303, 305, and 307. ) are each amplified by . Afterwards, the four amplified phase signals are added through an adder 309. The gain of the individual amplifiers 301, 303, 305, 307 is controlled by one of the corresponding DA converters 311, 313, 315, 317.

The embodiments described in this specification and the accompanying drawings merely illustratively illustrate some of the technical ideas included in the present invention. Accordingly, the embodiments disclosed in this specification are not intended to limit the technical idea of the present invention, but rather to explain it, and therefore, it is obvious that the scope of the technical idea of the present invention is not limited by these embodiments. All modifications and specific embodiments that can be easily inferred by a person skilled in the art within the scope of the technical idea included in the specification and drawings of the present invention should be construed as being included in the scope of the present invention.

211, 213, 215, 217, 219, 221: first phase locked loop
211: first phase detector
213: first charge pump
215: first loop filter
217: first operational amplifier
219: First voltage controlled oscillator
221: first divider
223, 225, 227, 229, 231: Clock recovery unit
223: Phase interpolator
225: up/down detector
227: Up/down filter
229: DAC control logic
231: DA converter
233, 235, 237, 239, 241, 243: second phase locked loop
233: second phase detector
235: second charge pump
237: second loop filter
239: Second operational amplifier
241: Second voltage controlled oscillator
243: second divider
245, 247, 249, 251, 253, 255: Amplification/filtering unit
245: amplifier
247: Bandpass filter
249: Frequency doubler
251: Active Mixer
253: Low-pass filter
255: cavity filter

Claims (5)

a first phase lock loop for outputting a first multiplied reference frequency by multiplying the input reference frequency;
a clock recovery unit for recovering a clock of the reference frequency using the multiplied reference frequency output from the first phase locked loop;
a second phase locked loop for receiving the multiplied reference frequency and outputting a local reference signal of a second multiplied ultra-high frequency; and
An amplification/filtering unit for amplifying and filtering the local reference signal output from the second phase locked loop.
Transmitter for ultra-high-speed data transmission and reception using a phase-locked loop including.
The method of claim 1, wherein the first phase locked loop:
a first phase detector that compares the reference frequency and the first divided signal and outputs an up signal and a down signal that change according to the phase difference between the reference frequency and the first divided signal;
a first charge pump that repeatedly turns on and off according to changes in the up and down signals output from the first phase detector and charges and discharges the load capacity on the output side;
a first loop filter implemented with a resistor and a capacitor to filter the signal output from the first charge pump;
a first operational amplifier that receives a predetermined reference voltage and the output of the first loop filter and amplifies it;
A first voltage controlled oscillator that outputs a first oscillation frequency using the output voltage of the first operational amplifier - The first voltage controlled oscillator is implemented as a two-stage differential ring oscillator and produces four phase signals each with a phase difference of 90 degrees. Print box - ; and
A first divider that divides the phase signal output from the first voltage controlled oscillator and outputs a first divided signal.
Transmitter for ultra-high-speed data transmission and reception using a phase-locked loop including.
The method of claim 2, wherein the clock recovery unit,
When receiving four phase signals output from the first voltage controlled oscillator, each having a phase difference of 90 degrees, a phase interpolator interpolates the phase signals according to the output of the DA converter below;
an up/down detector that compares the reference frequency and the output of the phase interpolator and generates high-speed up/down pulses;
Up/down filters that convert high-speed up/down pulses output from the up/down detector into low-speed up/down commands;
DAC control logic that generates commands to control the DA converter; and
A DA converter that converts the digital command output from the DAC control logic into an analog value and outputs it.
Transmitter for ultra-high-speed data transmission and reception using a phase-locked loop including.
In claim 3,
A transmitter for ultra-high-speed data transmission and reception using a phase-locked loop, wherein the up/down filter is a ripple counter.
The method of claim 4, wherein the amplification/filtering unit,
an amplifier that amplifies the output level of the second voltage controlled oscillator in the second phase locked loop;
a band-pass filter for removing unwanted waves from the output of the amplifier;
a frequency doubler that doubles the frequency output from the band-pass filter and outputs the multiplied local reference frequency;
An active device that combines the downward frequency and local reference frequency applied from one side to output the upward frequency and local reference frequency to the other side, and combines the upward frequency and local reference frequency applied from the other side to output the downward frequency and local reference frequency to one side. mixer;
a low-pass filter that passes a downstream frequency output from the active mixer and a local reference frequency and blocks the local reference frequency; and
A cavity filter that passes the upward frequency and the local reference frequency output from the active mixer and blocks the local reference frequency.
Transmitter for ultra-high-speed data transmission and reception using a phase-locked loop including.

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