KR20210111146A - Switching element, semiconductor memory device including the switching element and method for fabricating the same - Google Patents

Abstract

The present technology provides a switching element, a semiconductor memory device including the switching element, and a manufacturing method thereof. The switching element comprises: a first gate insulating film formed on a substrate; a second gate insulating film formed on an upper portion of the first gate insulating film, overlapping a part of the first gate insulating film, and including a ferroelectric object; a second gate electrode formed on the second gate insulating film; and a first gate electrode interposed between the first gate insulating film and the second gate insulating film and selectively controlling the second gate insulating film to have negative capacitance. Therefore, the switching element can increase an operation speed and operation reliability.

Description

A switching element, a semiconductor memory device including the switching element, and a manufacturing method thereof

The present invention relates to an electronic device, and more particularly, to a switching device including a negative capacitor, a semiconductor memory device including the switching device, and a manufacturing method thereof.

In order to meet the high performance and low price demanded by consumers, it is necessary to improve the density of semiconductor devices. In particular, since the degree of integration in a semiconductor memory device is an important factor determining the performance and price of a product, various efforts are being made to improve the degree of integration. For example, in a semiconductor memory device including a plurality of memory cells, research on a three-dimensional semiconductor memory device capable of reducing the area occupied by the memory cells per unit area of a substrate by three-dimensionally arranging the memory cells is in progress. have.

SUMMARY Embodiments of the present invention provide a switching device capable of improving operating speed and operating reliability, a semiconductor memory device including the switching device, and a method of manufacturing the same.

A switching device according to an embodiment of the present invention includes a first gate insulating film formed on a substrate; a second gate insulating layer formed on the first gate insulating layer, overlapping a portion of the first gate insulating layer, and including a ferroelectric; a second gate electrode formed on the second gate insulating layer; and a first gate electrode interposed between the first gate insulating layer and the second gate insulating layer and selectively controlling the second gate insulating layer to have a negative capacitance.

A switching device according to an embodiment of the present invention includes a first gate stack formed on a substrate; and at least one or more second gate stacks formed on the substrate so as to be adjacent to the first gate stack, wherein the first gate stack includes a first gate insulating layer sequentially stacked on the substrate, a first gate electrode; a second gate insulating layer including a ferroelectric having a negative capacitance in response to a bias applied to the first gate electrode and a second gate electrode, wherein the second gate stack is a third gate sequentially stacked on the substrate It may include an insulating layer, a fourth gate insulating layer including a ferroelectric having a spontaneously induced negative capacitance, and a third gate electrode.

A switching device according to an embodiment of the present invention includes a first gate stack formed on a substrate; and a second gate stack formed on the substrate to be adjacent to the first gate stack, wherein the first gate stack includes a first gate insulating film sequentially stacked on the substrate and a ferroelectric having a spontaneously induced negative capacitance. A second gate insulating layer and a first gate electrode may include a memory layer including a charge trap layer sequentially stacked on the substrate, and a second gate electrode.

A semiconductor memory device according to an embodiment of the present invention includes: a plurality of memory cells sharing a channel structure; and a first switching element connected to one side of the memory cells by sharing the channel structure, wherein the first switching element includes: a first gate insulating film surrounding the channel structure; a first gate electrode surrounding the first gate insulating layer; a second gate insulating layer surrounding a portion of the first gate electrode and including a ferroelectric having a negative capacitance in response to a bias applied to the first gate electrode; and a second gate electrode surrounding the second gate insulating layer and having a flat plate shape.

A semiconductor memory device according to an embodiment of the present invention includes: a plurality of memory cells sharing a channel structure; and a first switching device connected to one side of the memory cells by sharing the channel structure, wherein the first switching device includes a first gate structure and a second gate structure stacked apart from each other, the first gate The structure includes a first gate insulating layer surrounding the channel structure, a second gate insulating layer surrounding the first gate insulating layer and including a ferroelectric having a spontaneously induced negative capacitance, and a first gate electrode having a flat plate shape surrounding the second gate insulating layer. The second gate structure may include a memory film that surrounds the channel structure and includes a charge trap film, and a second gate electrode that surrounds the memory film and has a flat plate shape.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes: forming a first stacked body in which a first material layer and a second material layer are alternately stacked at least once on a substrate; forming a first open part penetrating the first laminate; forming a second gate insulating layer including a ferroelectric on a sidewall of the first open part; forming the second material layer on the sidewall of the first open portion on which the second gate insulating layer is formed and on the first laminate; sequentially forming a first gate insulating film and a channel film on sidewalls of the second material film in the first open part; removing the second material layer; and gap-filling a conductive material in the space from which the second material layer has been removed to form a first gate electrode interposed between the first gate insulating layer and the second gate insulating layer and a second gate electrode in contact with the second gate insulating layer. may include.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes: forming a first stacked body in which a first material layer and a second material layer are alternately stacked at least once on a substrate; forming a first open part penetrating the first laminate; forming a second gate insulating layer including a ferroelectric along a surface of the first open part; forming a second laminate in which the first material film and the second material film are alternately stacked a plurality of times on the first laminate; forming a second open part through the second laminate to be connected to the first open part; forming a memory layer on a sidewall of the second open part; sequentially forming a first gate insulating film and a channel film along surfaces of the first open portion and the second open portion; removing the second material layer; and forming a gate electrode in contact with the second gate insulating film and a control gate in contact with the memory film by gap-filling a conductive material in the space from which the second material film is removed.

The present technology, based on the means for solving the above problems, has a negative capacitor and provides a gate structure capable of easily controlling the negative capacitance, thereby improving the operation speed and operation reliability of a switching element and a semiconductor memory device having the same. can be improved

1 is a cross-sectional view illustrating a switching device according to an embodiment of the present invention.
FIG. 2 is a view for explaining a turn-on operation and a turn-off operation of the switching element illustrated in FIG. 1 .
3 is a cross-sectional view illustrating a switching device according to an embodiment of the present invention.
FIG. 4 is a view for explaining a turn-on operation and a turn-off operation of the switching element shown in FIG. 3 .
5 is a cross-sectional view illustrating a switching device according to an embodiment of the present invention.
6 is a view for explaining a turn-on operation and a turn-off operation of the switching element shown in FIG. 5 .
7 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
8 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.
9 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention.
FIG. 10 is an enlarged cross-sectional view of area A shown in FIG. 9 .
11A to 11H are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention.
12 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.
13 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention.
FIG. 14 is an enlarged cross-sectional view of area B shown in FIG. 13 .
15A to 15I are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention.
16 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.
17 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention.
18 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.
19 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention.
20 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.
21 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention.
22 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present invention.
23 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout.

SUMMARY Embodiments of the present invention, which will be described later, are to provide a switching element capable of improving operation speed, a semiconductor memory device having the switching element to improve operation reliability, and a method of manufacturing the same.

To this end, the switching device according to the embodiment of the present invention may include a negative capacitor field effect transistor (NCFET). For reference, the negative capacitor transistor may implement a subthreshold voltage swing (SS) of 60 mV/dec (Boltzmann tyranny) or less, which is known as a physical limit. Negative capacitor transistors are known to reduce the sub-threshold voltage swing to the level of 10mV/dec.

Hereinafter, a switching device according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 is a cross-sectional view illustrating a switching device according to an embodiment of the present invention.

As shown in FIG. 1 , the switching device SE1 according to the embodiment includes a gate insulating layer 210 , a first gate electrode 212 , and a second gate insulating layer 214 including a ferroelectric having a negative capacitance. ) and the second gate electrode 216 may include a gate stack GS in which the second gate electrode 216 is sequentially stacked, and junction regions 202 formed in the substrate 200 on both sides of the gate stack GS. Here, a channel 204 electrically connecting the junction regions 202 may be formed on the surface of the substrate 200 under the gate stack GS in response to a bias applied to the gate stack GS.

In the switching device SE1, the gate stack GS may include a negative capacitor. In this case, the negative capacitor may include a first gate electrode 212 , a second gate insulating layer 214 , and a second gate electrode 216 overlapping each other.

The first gate insulating layer 210 is formed on the substrate 200 and may include oxide or nitride. For example, the first gate insulating layer 210 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ) , aluminum oxide (Al ₂ O ₃ ) and titanium oxide (TiO ₂ ) It may include any one single layer or a multilayer layer in which two or more are stacked.

The first gate electrode 212 may serve to implement a negative capacitor by varying the capacitance of the second gate insulating layer 214 including a ferroelectric. Specifically, the second gate insulating layer 214 may have a positive capacitance in a thermal equilibrium state. Here, the thermal equilibrium state refers to a state in which no external force is applied to the second gate insulating layer 214 . For example, the thermal equilibrium state may be a state in which no bias is applied to the first gate electrode 212 . On the other hand, the second gate insulating layer 214 may have a negative capacitance in response to a bias applied to the first gate electrode 212 . To this end, the first gate electrode 212 extends from the first region 212A and the first region 212A inserted between the first gate insulating layer 210 and the second gate insulating layer 214 to form a second gate electrode. 216 may include a second region 212B adjacent to one sidewall and a gap 218 .

In the first gate electrode 212 , the first region 212A may serve to vary the capacitance of the second gate insulating layer 214 . The second region 212B of the first gate electrode 212 may serve to receive a bias for changing the capacitance of the second gate insulating layer 214 from the outside. Meanwhile, although not shown in the drawing, an insulating layer may be gap-filled between the second region 212B of the first gate electrode 212 and the second gate electrode 216 .

The line width of the gap 218 in the channel length direction may be at least greater than the thickness of the first gate insulating layer 210 . This is to prevent an interference phenomenon between the first gate electrode 212 and the second gate electrode 216 facing each other on the sidewalls. The line width of the gap 218 prevents leakage current from occurring due to the bias applied to each of the first gate electrode 212 and the second gate electrode 216 and forms the gate stack GS within a limited area. It can be set as far as possible. For reference, when the interval between the first gate electrode 212 and the second gate electrode 216 , that is, the line width of the gap 218 is smaller than a preset range, the bias applied to the first gate electrode 212 causes A leakage current may occur in the junction region 202 . Here, the preset range may refer to the thickness of the first gate insulating layer 210 . This is because a bias is applied to the first gate electrode 212 to additionally induce a negative capacitance while the second gate electrode 216 is biased to form the channel 204 . Due to the leakage current generated as the line width of the gap 218 is narrowed, the efficiency of controlling the potential level of the channel 204 may be reduced during the operation of the switching element SE1 .

Since the first gate electrode 212 is inserted between the first gate insulating layer 210 and the second gate insulating layer 214 , gold (Au), gadolinium scandate (GdScO ₃ ), silicon (Si), polysilicon (poly Si), copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta) and ruthenium (Ru) It may include a metal oxide, a metal nitride, or a metal oxynitride containing at least one of.

Meanwhile, in this embodiment, the case where the second region 212B of the first gate electrode 212 is formed to face one sidewall of the second gate electrode 216 and has an 'L'-shaped cross-sectional shape has been exemplified. not limited As a modification, the second region 212B of the first gate electrode 212 may be formed to face both one sidewall and the other sidewall of the second gate electrode 216 to have a 'U'-shaped cross-sectional shape.

The second gate insulating layer 214 serves as a dielectric layer of the negative capacitor and may include a ferroelectric material. Specifically, the capacitance of the second gate insulating layer 214 may be changed from positive to negative in response to a bias applied to the first gate electrode 212 . To this end, the second gate insulating layer 214 is a metal having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, or a monoclinic system. Oxides may be included. For example, as the metal oxide having a fluorite structure, hafnium oxide (HfO _x ) or zirconium oxide (ZrO _x ) may be used. In addition, as the metal oxide having a fluorite structure, one selected from the group consisting of hafnium oxide (HfO _x ) or zirconium oxide (ZrO _x ), silicon (Si), aluminum (Al), lanthanum (La), and gadolinium (Gd) Those doped with the above elements may be used. In this case, in order to easily change the capacitance in response to the bias applied to the first gate electrode 212 and to stably maintain the fluorite structure, the second gate insulating layer 214 may have a thickness in the range of 1 nm to 20 nm.

Specifically, the second gate insulating layer 214 is a hafnium oxide (HfO _x ), hafnium zirconium oxide (Hf _1-x Zr _x O ₂ ), hafnium aluminum oxide (Hf _1-x Al _x O ₂ ) or hafnium silicon oxide ( Hf _1-x Si _x O ₂ ) may include any one selected from the group consisting of. In this case, the second gate insulating film 214 may be a single film or a multilayer film in which two or more metal oxides having different crystal structures or compositions are stacked. For example, the second gate insulating film 214 may be a single film made of hafnium oxide or a multilayer film in which hafnium oxide and hafnium zirconium oxide are stacked.

In addition, as the second gate insulating layer 214 , both a ferroelectric organic material and a ferroelectric inorganic material capable of realizing a negative capacitor may be applied. For example, as ferroelectric inorganic _{PZT (PbZr x Ti 1-x} O 3), BaTiO 3, PbTiO 3 , such as perovskite (Perovskite) ferroelectric, LiNbO _3, LiTaO ₃ may like-Ilmenite (Pseudo-ilmenite) ferroelectric, PbNb Tungsten-Bronze (TB) ferroelectrics such as ₃ O ₆ , Ba ₂ NaNb ₅ O _{15 , SBT(SrBi 2} Ta ₂ O ₉ ), BLT((Bi,La) ₄ Ti ₃ O ₁₂ ), Bi ₄ Ti ₃ O ₁₂ such as _{RMnO 3} containing rare earth elements (R) such as Y, Er, Ho, Tm, Yb, Lu, as well as bismuth layered ferroelectrics and _{pyrochlore ferroelectrics such as La 2} Ti ₂ O _{7 and solid solutions of these ferroelectrics.} and PGO (Pb ₅ Ge ₃ O ₁₁ ), BFO (BiFeO ₃ ), and the like can also be used. Also, Group 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe may be used. In addition, as a ferroelectric organic material, polyvinylidene fluoride (PVDF), a polymer containing PVDF, a copolymer containing PVDF, a terpolymer containing PVDF, an odd number of nylons, cyanopolymers, and polymers or copolymers thereof At least one of them may be used.

The second gate insulating layer 214 may be formed using atomic layer deposition (ALD). This is to realize a stable crystal structure and composition, and to prevent the negative capacitor effect from being deteriorated due to traps generated at the interface between the second gate insulating layer 214 and the second gate insulating layer 214 in contact.

The second gate electrode 216 may serve to control the on/off of the switching element SE1 . In other words, the channel 204 may be formed in the substrate 200 under the gate stack GS in response to the bias applied to the second gate electrode 216 . The second gate electrode 216 is made of platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium ( Ti), tantalum (Ta), tungsten (W), copper (Cu), nickel (Ni), cobalt (Co), and may include at least one metal selected from the group consisting of molybdenum (Mo). For example, the second gate electrode 216 may include a conductive nitride (eg, TiN or MoN), a conductive oxynitride (eg, TiON), or a combination thereof (eg, TiSiN or TiAlON) of the above metals. .

Meanwhile, in the present embodiment, the case of the planar type in which the gate stack GS has a horizontal channel has been exemplified, but the present invention is not limited thereto. As a modification, the gate stack GS may have a channel structure such as a recess type or a fin type.

As described above, the switching element SE1 according to the embodiment includes the second gate insulating film 214 having a negative capacitance in response to the bias applied to the first gate electrode 212, so that the switching element SE1 Operation speed can be improved.

In addition, by integrating the first gate electrode 212 including the first region 212A and the second region 212B in the gate stack GS, the switching device SE1 including the negative capacitor is formed within a limited area. can provide

In addition, since it is possible to selectively control the capacitance polarity, capacitance, and potential level of the channel 118 of the second gate insulating layer 214 by using the bias applied to the first gate electrode 212, the switching element SE1 Operation reliability can be improved.

FIG. 2 is a view for explaining a turn-on operation and a turn-off operation of the switching element illustrated in FIG. 1 .

1 and 2 , in the off state, the first gate electrode 212 and the second gate electrode 216 may have an off voltage level VLoff. Here, the off voltage level VLoff may be a ground potential. Accordingly, in the OFF state, a ground voltage may be applied to the first gate electrode 212 and the second gate electrode 216 .

A first turn-on voltage Von1 and a second turn-on voltage Von2 may be applied to each of the first gate electrode 212 and the second gate electrode 216 in a turn-on operation period for turning on the switching element SE1 . .

The first turn-on voltage Von1 may be swept from the off voltage level VLoff to the first voltage level VL1. The sweep from the off voltage level VLoff to the first voltage level VL1 may be performed at the start point of the turn-on operation period and may have a vertical profile. Here, the first voltage level VL1 may be lower than the off voltage level VLoff. That is, the first voltage level VL1 may have a negative polarity.

Subsequently, the first turn-on voltage Von1 may sweep from the first voltage level VL1 to the second voltage level VL2 . In this case, the voltage level may be sequentially boosted from the first voltage level VL1 to the second voltage level VL2 for a predetermined time. That is, the voltage level may be sequentially boosted to have a stepped profile or a linear profile from the first voltage level VL1 to the second voltage level VL2 for a predetermined time. Here, the predetermined time may correspond to the turn-on operation period. The second voltage level VL2 may have a higher voltage level than the off voltage level VLoff and have a polarity different from that of the first voltage level VL1 . Accordingly, the second voltage level VL2 may be a voltage having a positive polarity.

The first turn-on voltage Von1 sweeps from the off voltage level VLoff to a first voltage level VL1 having a negative polarity, and successively a second voltage level VL2 having a positive polarity at the first voltage level VL1. ) to induce a negative capacitor effect. That is, this is to change the second gate insulating layer 214 to have a negative capacitance. In this case, the sequential step-up of the voltage level from the first voltage level VL1 to the second voltage level VL2 for a predetermined time is to secure operation reliability. Accordingly, by controlling the magnitude of the first voltage level VL1 and the second voltage level VL2 and the sweep time from the first voltage level VL1 to the second voltage level VL2, the second gate insulating layer 214 is formed. Negative capacitance can be controlled.

The second turn-on voltage Von2 may be swept from the off voltage level VLoff to the third voltage level VL3. In this case, the voltage level may be sequentially boosted from the off voltage level VLoff to the third voltage level VL3 for a predetermined time. That is, the voltage level may be sequentially boosted to have a stepped profile or a linear profile from the off voltage level VLoff to the third voltage level VL3 for a predetermined time. Here, the predetermined time may be shorter than the turn-on operation period. Accordingly, the first turn-on voltage Von1 is shifted from the off voltage level VLoff to the first voltage level VL1 at a time point when the second turn-on voltage Von2 sweeps from the off voltage level VLoff to the third voltage level VL3. ) may be faster. The third voltage level VL3 may have a higher voltage level than the off voltage level VLoff and have a polarity different from that of the first voltage level VL1 . Accordingly, the third voltage level VL3 may be a voltage having a positive polarity.

Meanwhile, in the present embodiment, when the second turn-on voltage Von2 sweeps from the off voltage level VLoff to the third voltage level VL3, the voltage level is sequentially boosted for a predetermined time. doesn't happen As a modification, the second turn-on voltage Von2 may be swept from the off voltage level VLoff to the third voltage level VL3, but boosted in a short time to have a vertical profile.

After the switching element SE1 is turned on, each of the first gate electrode 212 and the second gate electrode 216 may maintain the second voltage level VL2 and the third voltage level VL3 in the on state. And, when the first turn-on voltage Von1 and the second turn-on voltage Von2 applied to each of the first gate electrode 212 and the second gate electrode 216 are simultaneously blocked, the switching element SE1 is turned off. can Thereafter, in the off state, each of the first gate electrode 212 and the second gate electrode 216 may have an off voltage level VLoff.

Meanwhile, in the present embodiment, the turn-on operation period has been described separately, but since the switching element SE1 includes a negative capacitor, the sub-threshold voltage swing value can be implemented below the theoretical limit of 60 mV/dec (Boltzmann tyranny). Accordingly, it is possible to shorten a time required for a turn-on operation compared to a typical switching device, for example, a transistor.

3 is a cross-sectional view illustrating a switching device according to an embodiment of the present invention.

As shown in FIG. 3 , the switching device SE2 according to the embodiment includes a first gate stack GS1 formed on a substrate 200 , a first gate stack GS1 formed on the substrate 200 , and a gap with the first gate stack GS1 . Junction regions 202 formed in the substrate 200 to be adjacent to one side of the adjacent second gate stack GS2 and the first gate stack GS1 and the other side of the second gate stack GS2 having 208 , respectively. may include. Here, junction regions are formed on the surface of the substrate 200 under the first gate stack GS1 and the second gate stack GS2 in response to a bias applied to each of the first gate stack GS1 and the second gate stack GS2 . A channel 204 may be formed to electrically connect between the 202 .

In the switching device SE2, the first gate stack GS1 may include a negative capacitor. The negative capacitor may include a substrate 216 or a channel 204 that overlaps each other, a second gate insulating layer 222 , and a first gate electrode 224 .

In addition, the switching device SE2 is formed on the substrate 200 between the first gate stack GS1 and the second gate stack GS2 to provide a channel 204 and a second channel induced by the first gate stack GS1. A connection region 206 connecting the channels 204 induced by the gate stack GS2 to each other may be further included. The junction regions 202 and the connection region 206 may be impurity regions formed by ion implantation of impurities into the substrate 200 . On the other hand, the gap between the first gate stack GS1 and the second gate stack GS2, that is, the line width of the gap 208 is narrow, so that the channel 204 and the second gate induced by the first gate stack GS1 are narrow. When the channel 204 guided by the stack GS2 is electrically connectable, the connection region 206 may be omitted.

The first gate stack GS1 may serve to improve the operating speed of the switching device SE2 by using the negative capacitor effect. The second gate stack GS2 adjacent to the first gate stack GS1 may be a memory stack, and the switching element SE2 is controlled by controlling a surface potential level of the substrate 200 on which the channel 204 is formed. It can play a role in improving the operational reliability of Also, the second gate stack GS2 may serve to vary the threshold voltage of the switching element SE2 within a predetermined range. The line width of the first gate stack GS1 in the channel length direction may be equal to or greater than the line width of the second gate stack GS2 . In addition, the distance between the first gate stack GS1 and the second gate stack GS2 in the channel length direction, that is, the line width of the gap 208 is determined by the bias applied to the first gate stack GS1. It can be set so as not to affect the threshold voltage of (GS2).

The first gate stack GS1 includes a first gate insulating layer 220 formed on the substrate 200 , a second gate insulating layer 222 formed on the first gate insulating layer 220 and including a ferroelectric, and a second gate insulating layer. A first gate electrode 224 formed on the 222 may be included.

The first gate insulating layer 220 is formed on the substrate 200 and may include oxide or nitride. For example, the first gate insulating layer 220 is silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ) , aluminum oxide (Al ₂ O ₃ ) and titanium oxide (TiO ₂ ) It may include any one single layer or a multilayer layer in which two or more are stacked.

The second gate insulating layer 222 acts as a dielectric layer of the negative capacitor and may include a ferroelectric having a spontaneously induced negative capacitance. That is, the second gate insulating layer 222 may have a negative capacitance in a thermal equilibrium state. To this end, the second gate insulating layer 222 may include a metal oxide having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, or a monoclinic system. For example, hafnium oxide or zirconium oxide may be used as the metal oxide having a fluorite structure. In addition, as the metal oxide having a fluorite structure, hafnium oxide or zirconium oxide doped with at least one element selected from the group consisting of silicon (Si), aluminum (Al), lanthanum (La) and gadolinium (Gd) may be used. have. In this case, the second gate insulating layer 222 may have a thickness in a range of 1 nm to 10 nm to have a spontaneously induced negative capacitance and maintain a stable fluorite structure.

Specifically, the second gate insulating layer 222 is a hafnium oxide (HfO _x ), hafnium zirconium oxide (Hf _1-x Zr _x O ₂ ), hafnium aluminum oxide (Hf _1-x Al _x O ₂ ) or hafnium silicon oxide ( Hf _1-x Si _x O ₂ ) may include any one selected from the group consisting of. In this case, the second gate insulating film 222 may be a single film or a multilayer film in which two or more metal oxides having different crystal structures or compositions are stacked. For example, the second gate insulating film 222 may be a single film made of hafnium oxide or a multilayer film in which hafnium oxide and hafnium zirconium oxide are stacked.

In addition, as the second gate insulating layer 222 , both a ferroelectric organic material and a ferroelectric inorganic material capable of realizing a negative capacitor may be applied. For example, as ferroelectric inorganic _{PZT (PbZr x Ti 1-x} O 3), BaTiO 3, PbTiO 3 , such as perovskite (Perovskite) ferroelectric, LiNbO _3, LiTaO ₃ may like-Ilmenite (Pseudo-ilmenite) ferroelectric, PbNb Tungsten-Bronze (TB) ferroelectrics such as ₃ O ₆ , Ba ₂ NaNb ₅ O _{15 , SBT(SrBi 2} Ta ₂ O ₉ ), BLT((Bi,La) ₄ Ti ₃ O ₁₂ ), Bi ₄ Ti ₃ O ₁₂ such as _{RMnO 3} containing rare earth elements (R) such as Y, Er, Ho, Tm, Yb, Lu, as well as bismuth layered ferroelectrics and _{pyrochlore ferroelectrics such as La 2} Ti ₂ O _{7 and solid solutions of these ferroelectrics.} and PGO (Pb ₅ Ge ₃ O ₁₁ ), BFO (BiFeO ₃ ), and the like can also be used. Also, Group 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe may be used. In addition, as a ferroelectric organic material, polyvinylidene fluoride (PVDF), a polymer containing PVDF, a copolymer containing PVDF, a terpolymer containing PVDF, an odd number of nylons, cyanopolymers, and polymers or copolymers thereof At least one of them may be used.

The second gate insulating layer 222 may be formed using atomic layer deposition (ALD). This is to realize a stable crystal structure and composition, and to prevent the negative capacitor effect from being deteriorated due to traps generated at the interface between the second gate insulating layer 222 and the second gate insulating layer 222 .

Meanwhile, in the present embodiment, the case in which the second gate insulating layer 222 is formed on the first gate insulating layer 220 is exemplified, but the present invention is not limited thereto. As a modification, a floating electrode (not shown) may be inserted between the first gate insulating layer 220 and the second gate insulating layer 222 . The floating electrode (not shown) may serve to improve the interface characteristics in contact with the second gate insulating layer 222 . In addition, the floating electrode (not shown) may play a role of improving operational reliability by dispersing the bias applied to the first gate electrode 224 by the coupling effect. Since the floating electrode (not shown) is inserted between the first gate insulating layer 220 and the second gate insulating layer 222 , gold (Au), gadolinium scandate (GdScO3), silicon (Si) ), polysilicon (poly Si), copper (Cu), silver (Ag), molybdenum (Mo), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), and ruthenium (Ru) at least It may include one of a metal oxide, a metal nitride, or a metal oxynitride.

The first gate electrode 224 is made of platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), titanium ( Ti), tantalum (Ta), tungsten (W), copper (Cu), nickel (Ni), cobalt (Co), and may include at least one metal selected from the group consisting of molybdenum (Mo). For example, the first gate electrode 224 may include a conductive nitride (eg, TiN or MoN), a conductive oxynitride (eg, TiON), or a combination thereof (eg, TiSiN or TiAlON) of the aforementioned metals. .

The second gate stack GS2 is formed on the substrate 200 , and a memory layer ML and a memory layer ML in which a tunnel insulating layer 230 , a charge trap layer 232 , and a blocking layer 234 are sequentially stacked. ) may include a second gate electrode 236 formed on it. That is, the second gate stack GS2 may be a memory stack.

The tunnel insulating layer 230 and the blocking layer 234 may include an oxide, and the charge trap layer 232 may include a nitride. Here, the threshold voltage value of the second gate stack GS2 may be varied within a predetermined range by injecting charges into the charge trap layer 232 or removing charges injected into the charge trap layer 232 . Through this, the threshold voltage of the switching element SE2 may be varied.

The second gate electrode 236 is made of platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), aluminum (Al), or titanium (Ti) in consideration of the characteristics of the interface in contact with the memory layer ML. , tantalum (Ta), tungsten (W), copper (Cu), nickel (Ni), cobalt (Co), and may include at least one or more metals selected from the group consisting of molybdenum (Mo). For example, the second gate electrode 236 may include a conductive nitride, a conductive oxynitride, or a combination thereof of the aforementioned metals.

Meanwhile, in the present embodiment, the planar type case in which each of the first gate stack GS1 and the second gate stack GS2 has a horizontal channel has been exemplified, but the present invention is not limited thereto. As a modification, each of the first gate stack GS1 and the second gate stack GS2 may have a channel structure such as a recess type or a fin type.

As described above, the switching device SE2 according to the embodiment includes the second gate insulating layer 222 having a spontaneously induced negative capacitance, thereby improving the operating speed of the switching device SE2. In addition, since the second gate insulating layer 222 has a spontaneously induced negative capacitance, the turn-on operation period can be shortened, and thus the operation speed of the switching element SE2 can be further improved.

In addition, by providing the second gate stack GS2 including the memory layer ML, the operation reliability of the switching device SE2 may be improved.

In addition, since each of the first gate stack GS1 and the second gate stack GS2 can be independently controlled, the switching device SE2 capable of digesting various operation modes can be provided.

FIG. 4 is a view for explaining a turn-on operation and a turn-off operation of the switching element shown in FIG. 3 .

3 and 4 , in the off state, the first gate electrode 224 and the second gate electrode 236 may have an off voltage level VLoff. Here, the off voltage level VLoff may be a ground potential. Accordingly, in the OFF state, a ground voltage may be applied to the first gate electrode 224 and the second gate electrode 236 .

A first turn-on voltage Von1 and a second turn-on voltage Von2 may be applied to each of the first gate electrode 224 and the second gate electrode 236 in the turn-on operation period for turning on the switching element SE2 . .

The first turn-on voltage Von1 may be swept from the off voltage level VLoff to the first voltage level VL1. In this case, the voltage level may be sequentially boosted from the off voltage level VLoff to the first voltage level VL1 for a predetermined time. That is, the voltage level may be sequentially boosted to have a stepped profile or a linear profile from the off voltage level VLoff to the first voltage level VL1 for a predetermined time. Here, the predetermined time may correspond to the turn-on operation period, and the sequential step-up of the voltage level from the off voltage level VLoff to the second voltage level VL2 during the predetermined time is to secure operation reliability. The first voltage level VL1 may be higher than the off voltage level VLoff. Accordingly, the first voltage level VL1 may have a positive polarity.

The second turn-on voltage Von2 may be swept from the off voltage level VLoff to the second voltage level VL2. In this case, the voltage level may be sequentially boosted from the off voltage level VLoff to the second voltage level VL2 for a predetermined time. That is, the voltage level may be sequentially boosted to have a stepped profile or a linear profile from the off voltage level VLoff to the second voltage level VL2 for a predetermined time. Here, the predetermined time may be shorter than the turn-on operation period. The second voltage level VL2 may be higher than the off voltage level VLoff. Accordingly, the second voltage level VL2 may have a positive polarity.

Meanwhile, in the present embodiment, when the second turn-on voltage Von2 sweeps from the off voltage level VLoff to the second voltage level VL2, the voltage level is sequentially boosted for a predetermined time. doesn't happen As a modification, the second turn-on voltage Von2 may be swept from the off voltage level VLoff to the second voltage level VL2, but boosted in a short time to have a vertical profile.

After the switching element SE2 is turned on, each of the first gate electrode 224 and the second gate electrode 236 may maintain the first voltage level VL1 and the second voltage level VL2 in the on state. And, when the first turn-on voltage Von1 and the second turn-on voltage Von2 applied to each of the first gate electrode 224 and the second gate electrode 236 are blocked at the same time, the switching element SE2 is turned off. can Thereafter, in the off state, each of the first gate electrode 224 and the second gate electrode 236 may have an off voltage level VLoff.

Meanwhile, in the present embodiment, the turn-on operation period has been described separately, but since the switching element SE2 includes a negative capacitor, the sub-threshold voltage swing value can be implemented below the theoretical limit of 60 mV/dec. Accordingly, it is possible to shorten a time required for a turn-on operation compared to a typical switching device, for example, a transistor.

5 is a cross-sectional view illustrating a switching device according to an embodiment of the present invention.

As shown in FIG. 5 , the switching device SE3 according to the embodiment is formed on the substrate 200 and includes a third gate stack GS3 adjacent to each other and at least one fourth gate stack GS4 . can do. In addition, junction regions 202 formed in the substrate 200 to be adjacent to one side of the third gate stack GS3 and the other side of the fourth gate stack GS4 may be included, respectively. Here, on the surface of the substrate 200 under the third gate stack GS3 and the fourth gate stack GS4 , a junction region is provided in response to a bias applied to each of the third gate stack GS3 and the fourth gate stack GS4 . A channel 204 may be formed to electrically connect between the 202 .

Meanwhile, in the present embodiment, the case in which the switching element SE3 includes one fourth gate stack GS4 is exemplified, but the present invention is not limited thereto. As a modification, a plurality of fourth gate stacks GS4 may be provided.

In addition, the switching element SE3 is formed on the substrate 200 between the third gate stack GS3 and the fourth gate stack GS4 and includes the channel 204 and the fourth induced by the third gate stack GS3 . A connection region 206 connecting the channels 204 induced by the gate stack GS4 to each other may be further included. The junction regions 202 and the connection region 206 may be impurity regions formed by ion implantation of impurities into the substrate 200 . On the other hand, the gap 208 between the third gate stack GS3 and the fourth gate stack GS4 is narrow, so that the channel 204 and the fourth gate stack GS4 induced by the third gate stack GS3 are narrowed. When the channel 204 induced by the signal is electrically connectable, the connection region 206 may be omitted.

In the switching device SE3 , each of the third gate stack GS3 and the fourth gate stack GS4 may serve to improve the operating speed of the switching device SE3 by using a negative capacitor effect. Accordingly, each of the third gate stack GS3 and the fourth gate stack GS4 may include a negative capacitor. In addition, the fourth gate stack GS4 may control the surface potential level of the substrate 200 on which the channel 204 is formed to improve the operational reliability of the switching element SE3 . The line width of the third gate stack GS3 in the channel length direction may be equal to or greater than the line width of the fourth gate stack GS4. And, the line width of the gap 208 between the third gate stack GS3 and the fourth gate stack GS4 in the channel length direction is the width of the fourth gate stack GS4 by the bias applied to the third gate stack GS3. It may be set so as not to affect the threshold voltage.

The third gate stack GS3 includes a first gate insulating layer 210 formed on the substrate 200 , formed on the first gate insulating layer 210 , overlapping a portion of the first gate insulating layer 210 , and including a ferroelectric. The second gate insulating layer 214 , the second gate electrode 216 formed on the second gate insulating layer 214 , and the first region 212A inserted between the first gate insulating layer 210 and the second gate insulating layer 214 . ) and a second region 212B extending from the first region 212A and having a second gate electrode 216 and a gap 218 adjacent thereto, wherein the second gate insulating layer 214 selectively provides negative capacitance. It may include a first gate electrode 212 that is controlled to have it. Here, the negative capacitor may include a first gate electrode 212 , a second gate insulating layer 214 , and a second gate electrode 216 overlapping each other.

In the switching device SE3, the third gate stack GS3 may correspond to the gate stack GS shown in FIG. 1 . In other words, in the present embodiment, the third gate stack GS3 may have substantially the same configuration as the gate stack GS shown in FIG. 1 . Therefore, in the present embodiment, detailed description of overlapping contents in each configuration of the third gate stack GS3 will be omitted.

In the third gate stack GS3 , the second gate insulating layer 214 may function as a dielectric layer of the negative capacitor. The capacitance of the second gate insulating layer 214 may be changed from positive to negative in response to a bias applied to the first gate electrode 212 . In order to easily change the capacitance and stably maintain the fluorite structure, the second gate insulating layer 214 may have a thickness in the range of 1 nm to 20 nm.

One sidewall of the second gate electrode 216 may face the fourth gate stack GS4 , and the other sidewall of the second gate electrode 216 may face the second region 212B of the first gate electrode 212 . can meet That is, the second region 212B of the first gate electrode 212 may be positioned adjacent to the junction region 202 . This is when controlling the surface potential level of the substrate 200 on which the channel 204 is formed in response to the bias applied to the third gate electrode 224 of the fourth gate stack GS4, the first gate electrode 212 ) to prevent interference caused by the bias applied to the

The fourth gate stack GS4 includes a third gate insulating layer 220 formed on the substrate 200 , a fourth gate insulating layer 222 formed on the third gate insulating layer 220 and including a ferroelectric, and a fourth gate insulating layer. A third gate electrode 224 formed on the 222 may be included. Here, the negative capacitor may include the substrate 200 or channel 204, the fourth gate insulating layer 222, and the third gate electrode 224 overlapping each other.

In the switching device SE3 , the fourth gate stack GS4 may correspond to the first gate stack GS1 illustrated in FIG. 3 . In other words, in the present embodiment, the fourth gate stack GS4 may have substantially the same configuration as the first gate stack GS1 illustrated in FIG. 3 . Therefore, in the present embodiment, detailed description of overlapping contents in each configuration of the fourth gate stack GS4 will be omitted.

The fourth gate insulating layer 222 acts as a dielectric layer of the negative capacitor and may include a ferroelectric having a spontaneously induced negative capacitance. That is, the fourth gate insulating layer 222 may have a negative capacitance in a thermal equilibrium state. In order to have a spontaneously induced negative capacitance and maintain a stable fluorite structure, the fourth gate insulating layer 222 may have a thickness smaller than that of the second gate insulating layer 214 . Specifically, the fourth gate insulating layer 222 may have a thickness in the range of 1 nm to 10 nm.

Meanwhile, in the present embodiment, a planar type case in which each of the third gate stack GS3 and the fourth gate stack GS4 has a horizontal channel is exemplified, but the present invention is not limited thereto. As a modification, each of the third gate stack GS3 and the fourth gate stack GS4 may have a channel structure such as a recess type or a fin type.

As described above, the switching device SE3 according to the embodiment includes the third gate stack GS3 including the second gate insulating layer 214 d having a negative capacitance in response to the bias applied to the first gate electrode 212 . ), it is possible to improve the operating speed of the switching element SE3.

In addition, by providing a fourth gate stack GS4 including a fourth gate insulating layer 222 having a spontaneously induced negative capacitance together with the third gate stack GS3, the operation speed of the switching element SE3 is further improved can do it

In addition, since it is possible to selectively control the capacitance polarity, capacitance, and potential level of the channel 118 of the second gate insulating layer 214 by using the bias applied to the first gate electrode 212, the switching device SE3 Operation reliability can be improved.

In addition, since each of the third gate stack GS3 and the fourth gate stack GS4 can be independently controlled, the switching device SE3 capable of digesting various operation modes can be provided.

6 is a view for explaining a turn-on operation and a turn-off operation of the switching element shown in FIG. 5 .

5 and 6 , in the off state, the first gate electrode 212 , the second gate electrode 216 , and the third gate electrode 224 may each have an off voltage level VLoff. Here, the off voltage level VLoff may be a ground potential. Accordingly, in the OFF state, a ground voltage may be applied to each of the first gate electrode 212 , the second gate electrode 216 , and the third gate electrode 224 .

A first turn-on voltage Von1 and a second turn-on voltage are respectively applied to the first gate electrode 212 , the second gate electrode 216 , and the third gate electrode 224 in the turn-on operation period for turning on the switching element SE3 . (Von2) and a third turn-on voltage Von3 may be applied.

The first turn-on voltage Von1 may be swept from the off voltage level VLoff to the first voltage level VL1. The sweep from the off voltage level VLoff to the first voltage level VL1 may be performed at the start point of the turn-on operation period and may have a vertical profile. Here, the first voltage level VL1 may be lower than the off voltage level VLoff. That is, the first voltage level VL1 may have a negative polarity. Subsequently, the first turn-on voltage Von1 may sweep from the first voltage level VL1 to the second voltage level VL2 . In this case, the voltage level may be sequentially boosted from the first voltage level VL1 to the second voltage level VL2 for a predetermined time. That is, the voltage level may be sequentially boosted to have a stepped profile or a linear profile from the first voltage level VL1 to the second voltage level VL2 for a predetermined time. Here, the predetermined time may correspond to the turn-on operation period. The second voltage level VL2 may have a higher voltage level than the off voltage level VLoff and have a polarity different from that of the first voltage level VL1 . Accordingly, the second voltage level VL2 may have a positive polarity.

The second turn-on voltage Von2 may be swept from the off voltage level VLoff to the third voltage level VL3. In this case, the voltage level may be sequentially boosted from the off voltage level VLoff to the third voltage level VL3 for a predetermined time. That is, the voltage level may be sequentially boosted to have a stepped profile or a linear profile from the off voltage level VLoff to the third voltage level VL3 for a predetermined time. Here, the predetermined time may be shorter than the turn-on operation period. Accordingly, the first turn-on voltage Von1 is shifted from the off voltage level VLoff to the first voltage level VL1 at a time point when the second turn-on voltage Von2 sweeps from the off voltage level VLoff to the third voltage level VL3. ) may be faster. The third voltage level VL3 may have a higher voltage level than the off voltage level VLoff and have a polarity different from that of the first voltage level VL1 . Accordingly, the third voltage level VL3 may have a positive polarity.

Meanwhile, in the present embodiment, when the second turn-on voltage Von2 sweeps from the off voltage level VLoff to the third voltage level VL3, the voltage level is sequentially boosted for a predetermined time. doesn't happen As a modification, the second turn-on voltage Von2 may be swept from the off voltage level VLoff to the third voltage level VL3, but boosted in a short time to have a vertical profile.

The third turn-on voltage Von3 may be swept from the off voltage level VLoff to the fourth voltage level VL4. In this case, the voltage level may be sequentially boosted from the off voltage level VLoff to the fourth voltage level VL4 for a predetermined time. That is, the voltage level may be sequentially boosted to have a stepped profile or a linear profile from the off voltage level VLoff to the fourth voltage level VL4 for a predetermined time. Here, the predetermined time may be shorter than the turn-on operation period. Accordingly, the first turn-on voltage Von1 is shifted from the off voltage level VLoff to the first voltage level VL1 at a time point when the third turn-on voltage Von3 is swept from the off voltage level VLoff to the fourth voltage level VL4. ) may be faster. The third turn-on voltage Von3 sweeps from the off voltage level VLoff to the fourth voltage level VL4 is the second turn-on voltage Von2 shifts from the off voltage level VLoff to the third voltage level VL3 ) at the same time as the sweep time, or it may be earlier. The fourth voltage level VL4 may have a higher voltage level than the off voltage level VLoff and have a polarity different from that of the first voltage level VL1 . Accordingly, the fourth voltage level VL4 may have a positive polarity.

Meanwhile, in the present embodiment, when the third turn-on voltage Von3 sweeps from the off-voltage level VLoff to the fourth voltage level VL4, the voltage level is sequentially boosted for a predetermined time. doesn't happen As a modification, the third turn-on voltage Von3 may be swept from the off voltage level VLoff to the fourth voltage level VL4, but boosted in a short time to have a vertical profile.

After the switching element SE3 is turned on, each of the first gate electrode 212 to the third gate electrode 224 may maintain the second voltage level VL2 to the fourth voltage level VL4 in the on state. And, when the first turn-on voltage Von1 to the third turn-on voltage Von3 applied to each of the first gate electrode 212 to the third gate electrode 224 are simultaneously cut off, the switching element SE3 is turned on. can Thereafter, in the off state, each of the first gate electrode 212 to the third gate electrode 224 may have an off voltage level VLoff.

Meanwhile, in the present embodiment, the turn-on operation section has been described separately, but since the switching element SE3 includes a negative capacitor, the sub-threshold voltage swing value can be implemented below the theoretical limit of 60 mV/dec (Boltzmann tyranny). Accordingly, it is possible to shorten a time required for a turn-on operation compared to a typical switching device, for example, a transistor.

Hereinafter, a semiconductor memory device including the above-described switching device and a method of manufacturing the same will be described in detail. Here, the semiconductor memory device may include a nonvolatile semiconductor memory device having a 3D structure, for example, a 3D NAND.

The semiconductor memory device may include a selection transistor connected in series to one side and the other side of a plurality of memory cells sharing a channel. In a semiconductor memory device according to an embodiment of the present invention, which will be described later, the operation speed and operation reliability of the semiconductor memory device may be improved by applying the above-described switching element to the selection transistor.

7 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

7 , the semiconductor memory device 1 may include a peripheral circuit (PC) and a memory cell array (3).

The peripheral circuit PC includes a program operation for storing data in the memory cell array 3 , a read operation for outputting data stored in the memory cell array 3 , and a memory cell array 3 . ) may be configured to control an erase operation for erasing data stored in . For example, the peripheral circuit (PC) includes a voltage generator (5), a row decoder (6), a control circuit (7), and a page buffer group (8). can do.

The memory cell array 3 may include a plurality of memory blocks. The memory cell array 3 may be connected to the row decoder 6 through word lines WL, and may be connected to the page buffer group 8 through bit lines BL.

The control circuit 7 may control the peripheral circuit PC in response to the command CMD and the address ADD.

In response to the control of the control circuit 7 , the voltage generator 5 includes a pre-erase voltage, an erase voltage, a ground voltage, a program voltage, a verification voltage, a pass voltage, a read voltage, etc. used for a program operation, a read operation, and an erase operation. It is possible to generate various operating voltages of

The row decoder 6 may select a memory block in response to the control of the control circuit 7 . The row decoder 6 may be configured to apply operating voltages to the word lines WL connected to the selected memory block.

The page buffer group 8 may be connected to the memory cell array 3 through bit lines BL. The page buffer group 8 may temporarily store data received from an input/output circuit (not shown) during a program operation in response to the control of the control circuit 7 . The page buffer group 8 may sense the voltage or current of the bit lines BL during a read operation or a verify operation in response to the control of the control circuit 7 . The page buffer group 8 may select the bit lines BL in response to the control of the control circuit 7 .

Structurally, the memory cell array 3 may be disposed side by side with the peripheral circuit PC, or the memory cell array 3 may overlap a part of the peripheral circuit PC.

8 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 8 , the memory block BLK1 may include a source layer SL and a plurality of cell strings CS1 commonly connected to a plurality of word lines WL1 to WLn. In addition, the plurality of cell strings CS1 may be connected to the plurality of bit lines BL.

Each of the plurality of cell strings CS1 includes a source select transistor SST connected to the source layer SL, a drain select transistor DST connected to the bit line BL, a source select transistor SST, and a drain select transistor DST connected to the bit line BL. ) may include a plurality of memory cells MC1 to MCn connected in series between them. Here, each of the source select transistor SST and the drain select transistor DST may include two gates (or gate electrodes). In addition, each of the source select transistor SST and the drain select transistor DST may include a negative capacitor.

Gates of the plurality of memory cells MC1 to MCn may be respectively connected to a plurality of word lines WL1 to WLn that are spaced apart from each other and stacked. The plurality of word lines WL1 to WLn may be disposed between the source select lines SSL1 and SSL1 and the drain select lines DSL1 and DSL2 .

The first source select line SSL1 may be connected to the second gate electrode of the source select transistor SST, and the second source select line SSL2 may be connected to the first gate electrode of the source select transistor SST. The second source selection line SSL2 may be positioned above the first source selection line SSL1 . Here, the first gate electrode of the source select transistor SST may serve to control the negative capacitance. In addition, the second gate electrode of the source select transistor SST may serve to control on/off of the channel.

The first drain select line DSL1 may be connected to a first gate electrode of the drain select transistor DST, and the second drain select line DSL2 may be connected to a second gate electrode of the drain select transistor DST. Here, the first gate electrode of the drain select transistor DST may serve to control the negative capacitance. In addition, the second gate electrode of the drain select transistor DST may serve to control channel on/off.

The source layer SL may be connected to the source of the source select transistor SST. A drain of the drain select transistor DST may be connected to a bit line BL corresponding to a drain of the drain select transistor DST.

9 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention. And, FIG. 10 is an enlarged cross-sectional view of area A shown in FIG. 9 .

8 to 10 , the cell string CS1 according to the embodiment includes a channel structure 300 positioned between the source layer SL and the bit line BL, and a plurality of memory cells MC1 to MCn), the first switching element 400 and the second switching element 500 may be included. The source layer SL may have a flat plate shape and may serve as a source of the source select transistor SST. The bit line BL may be electrically connected to the channel structure 300 through the contact plug CP.

The channel structure 300 connects between the source layer SL and the bit line BL stacked apart from each other and may have a vertical column shape. Accordingly, one end and the other end of the channel structure 300 may be electrically connected to the source layer SL and the bit line BL, respectively. The channel structure 300 may include a core pillar 302 , a capping layer 306 , and a channel layer 304 . The core pillar 302 may have a cylindrical shape and may include an insulating material. The capping layer 306 may be positioned between the core pillar 302 and the bit line BL, and may include a doped semiconductor layer. For example, the doped semiconductor layer may include a silicon layer doped with an n-type impurity. The capping layer 302 may serve as a drain of the drain select transistor DST and may be connected to the contact plug CP of the bit line BL. The channel layer 304 may surround the bottom and side surfaces of the core pillar 302 and may be electrically connected to the source layer SL. In addition, the channel layer 304 may surround the side surface of the capping layer 306 and may be electrically connected to the capping layer 306 . The channel film 304 may include a semiconductor film. For example, the semiconductor film may include a silicon film.

The plurality of memory cells MC1 to MCn surround the channel structure 300 and may have a stacked shape spaced apart from each other. Among the plurality of memory cells MC1 to MCn, the memory cells MC1 and MCn positioned adjacent to each of the first switching element 400 and the second switching element 500 may be used as dummy cells. Each of the plurality of memory cells MC1 to MCn may include a memory structure MS surrounding the channel structure 300 . Here, the memory structure MS may have substantially the same configuration as the second gate stack GS2 shown in FIG. 3 . That is, the tunnel insulating layer 230 surrounding the channel layer 304 of the memory structure MS, the charge trap layer 232 surrounding the tunnel insulating layer 230, and the blocking layer 234 and the blocking layer surrounding the charge trap layer 232 . A gate electrode 236 surrounding the layer 234 and having a flat plate shape may be included. In the memory structure MS, the gate electrode 236 may function as a word line WL. Since the memory structure MS has substantially the same configuration as the second gate stack GS2 shown in FIG. 3 , an additional detailed description thereof will be omitted.

Each of the first switching device 400 and the second switching device 500 may include a negative capacitor. The first switching element 400 and the second switching element 500 may each share a channel structure 300 and may be located on one side and the other side of the memory cells MC1 to MCn. Specifically, the first switching element 400 may be positioned between the source layer SL and the memory cells MC1 to MCn, and the second switching element 500 may include the bit line BL and the memory cells MC1 to MCn. It can be located between MC1~MCn). Accordingly, the first switching element 400 may act as a source select transistor SST, and the second switching element 500 may act as a drain select transistor DST. In the direction in which the channel structure 300 extends, that is, in the channel length direction, the first switching element 400 and the second switching element 500 may have symmetrical shapes.

Each of the first switching device 400 and the second switching device 500 may include gate structures 410 and 510 having a gate all around (GAA) structure surrounding the channel structure 300 . The gate structures 410 and 510 may have substantially the same configuration as the gate stack GS shown in FIG. 1 . That is, the gate structures 410 and 510 include a first gate insulating layer 210 surrounding the channel layer 304 , a first gate electrode 212 surrounding the first gate insulating layer 210 , and a portion of the first gate electrode 212 . It may include a second gate insulating layer 214 surrounding the ferroelectric material having a negative capacitance, and a second gate insulating layer 214 surrounding the second gate insulating layer 214 and having a flat plate shape. Here, the first gate electrode 212 is positioned between the first gate insulating layer 210 and the second gate insulating layer 214 , and a first region 212A and a first region 212A surrounding the first gate insulating layer 210 . ) extending from the sidewall of the second gate electrode 216 and having a gap 218 adjacent thereto, and may include a second region 212B having a flat plate shape. The line width of the gap 218 in the channel length direction may be at least greater than the thickness of the first gate insulating layer 210 . In addition, the line width of the gap 218 in the channel length direction may be smaller than the distance between the memory structure MS and the gate structures 410 and 510 .

The second region 212B of the first gate electrode 212 includes the memory structure MS and the second gate electrode 216 of the gate structures 410 and 510 to easily control a channel boosting effect. can be located between Through this, turn-on and turn-off can be controlled through the bias applied to the first gate electrode 212 , thereby preventing unnecessary interference in the adjacent memory cells MC1 and MCn. In other words, by adjusting the potential level of the channel induced by the first switching device 400 and the second switching device 500 through the bias applied to the first gate electrode 212, the adjacent memory cells MC1 and MCn. operation reliability can be improved.

In the gate structure 410 of the first switching device 400 , the first gate electrode 212 and the second gate electrode 216 serve as the second source selection line SSL2 and the first source selection line SSL1 , respectively. can In the gate structure 510 of the second switching device 500 , the first gate electrode 212 and the second gate electrode 216 serve as the first drain selection line DSL1 and the second drain selection line DSL2, respectively. can Since the gate structures 410 and 510 have substantially the same configuration as the gate stack GS shown in FIG. 1 , an additional detailed description thereof will be omitted.

The turn-on operation and turn-off operation of the first switching element 400 and the second switching element 500 may be substantially the same as those illustrated in FIG. 2 . In addition, a known method may be used for the program operation, the erase operation, and the read operation of the source layer SL, the bit line BL, and the memory cells MC1 to MCn.

Meanwhile, in the present embodiment, the case in which each of the first switching element 400 and the second switching element 500 includes a negative capacitor is exemplified, but the present invention is not limited thereto. As a modification, only one of the first switching element 400 and the second switching element 500 may include a negative capacitor.

As described above, the semiconductor memory device according to the present embodiment includes the first switching device 400 and the second switching device 500 having a negative capacitor, thereby improving the operating speed and operating reliability of the semiconductor memory device. can In particular, since the sub-threshold voltage swing value can be implemented below the theoretical limit of 60 mV/dec, the on/off response speed for the channel can be improved. In addition, during the erase operation of the memory cells MC1 to MCn, the turn-on slope of the gate induced drain leakage (GIDL), that is, the GIDL formation time may be shortened, thereby improving the erase speed. Here, the GIDL formation time may refer to a turn-on operation period of each of the first switching element 400 and the second switching element 500 . In addition, since the GIDL formation time can be shortened during the erase operation, it is possible to fundamentally prevent a problem that occurs when a hole is created in the middle of the channel in the erase pause situation. For reference, when the sub-threshold voltage swing value of the source select transistor (SST) and the drain select transistor (DST) exceeds 60 mV/dec, since the GIDL formation time is long during the erase operation, the erase pause command is executed in the middle of the GIDL formation (i.e. , in the middle of the turn-on operation period), the hole is accumulated in the channel while a hole is created in the channel in response to the erase pause command, and an error is generated during the erase operation due to the accumulated hole in the channel. may occur.

11A to 11H are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention. For reference, FIGS. 11A to 11H are for explaining an example of the method of manufacturing the semiconductor memory device illustrated in FIGS. 8 to 10 , and cross-sectional shapes may be partially different from those illustrated in FIG. 9 for process reasons.

As shown in FIG. 11A , a pre-source layer 14A is formed on the substrate 10 on which a predetermined structure, for example, a peripheral circuit is formed. The pre-source layer 14A may be formed in a form in which the first sacrificial layer 12 is inserted between the semiconductor layers doped with impurities. For example, in the pre-source layer 14A, the first silicon layer 11 doped with n-type impurities, the first sacrificial layer 12 , and the second silicon layer 13 doped with n-type impurities are sequentially formed. It can be formed as a laminated multilayer film.

Meanwhile, although not shown in the drawings, a separation insulating layer may be formed between the pre-source layer 14A and the substrate 10 before the pre-source layer 14A is formed. The isolation insulating layer electrically separates the pre-source layer 14A and the substrate 10 and may serve to prevent the substrate 10 from being damaged between processes.

Next, after forming the first stacked body 17 in which the first material layer 15 and the second material layer 16 are alternately stacked at least once or more, the first layered body 17 is formed until the pre-source layer 14A is exposed. The first open portion 18 is formed by etching the first laminate 17 . The first stacked body 17 and the first open portion 18 are for forming the first selection transistor, that is, the source selection transistor. The first material layer 15 may be positioned on the lowermost layer and the uppermost layer of the first stacked body 17 . Through a subsequent process, the first material layer 15 may function as an interlayer insulating layer separating the stacked gate conductive layers, and the second material layer 16 may function as a sacrificial layer for forming the gate conductive layer. To this end, the first material layer 15 may be formed of a material having an etch selectivity to the second material layer 16 . For example, the first material layer 15 may include an oxide, and the second material layer 16 may include a nitride.

Next, after sequentially forming the first ferroelectric film 19 and the second material film 16 along the surface of the first laminate 17 on which the first open portion 18 is formed, the first ferroelectric film 19 ) and the second material film 16 are selectively selected from the first ferroelectric film 19 and the second material film 16 until the pre-source film 14A is exposed so that the second material film 16 remains on the sidewall of the first open portion 18 . etch with Here, the first ferroelectric film 19 is a dielectric of the negative capacitor, and may correspond to the second gate insulating film 214 in the gate structure 410 of the first switching device 400 shown in FIG. 9 .

The first ferroelectric film 19 may optionally include a ferroelectric having a negative capacitance. The ferroelectric may include a metal oxide furnace having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, or a monoclinic system. For example, the first ferroelectric film 19 may be formed of hafnium oxide. In addition, the first ferroelectric film 19 may be formed to have a thickness of 20 nm or less in order to easily change the capacitance and stably maintain the fluorite structure. For example, the first ferroelectric film 19 may be formed to have a thickness in a range of 1 nm to 20 nm.

The first ferroelectric film 19 may be formed using atomic layer deposition (ALD). This is to implement a stable crystal structure and composition, and to prevent the negative capacitor effect from being deteriorated due to traps occurring at the interface. Hereinafter, as an example of a method of forming the first ferroelectric film 19 , a case in which the first ferroelectric film 19 is formed of hafnium oxide will be described.

In the atomic layer deposition method, a unit cycle of sequentially supplying a precursor, purging a precursor, supplying an oxidizing agent, and purging an oxidizing agent may be repeated a plurality of times. While the unit cycle is repeated a plurality of times, the inside of the chamber may be controlled to have a temperature of 300°C or less, for example, 180°C to 300°C. The temperature inside the chamber affects the crystal structure of hafnium oxide, and hafnium oxide having a stable fluorite structure can be formed only when the hafnium oxide is deposited at a temperature of 300° C. or less.

As a hafnium precursor in the precursor supply step, Bis(methyl-η5-cyclopentadienyl) dimethylhafnium, Tetrakis(dimethylamido)hafnium, Tetrakis(ethylmethylamido) hafnium, Bis(methyl-η5-cyclopentadienyl)methoxymethylhafnium, tbutoxytris(ethylmethylamido)hafnium, etc. can be used. . The hafnium precursor may be chemically adsorbed on the surface of the base layer to form a monoatomic layer. Thereafter, the precursor remaining in the chamber may be purged to the outside by supplying a purge gas to the chamber. Argon gas or nitrogen gas may be used as the purge gas.

Oxygen gas may be used as an oxidizing agent in the oxidizing agent supply step. Here, while supplying the oxidizing agent, it is also possible to create a plasma atmosphere. In addition, after supplying an oxidizing agent to adsorb oxygen to the hafnium precursor adsorbed to the base layer, a plasma atmosphere may be created. Thereafter, the oxidizing agent remaining in the chamber may be purged to the outside by supplying a purge gas to the chamber.

After the thin film deposition is completed, an annealing process may be performed to heal defects at the interface of the first ferroelectric film 19 and to stabilize the crystal structure. The annealing process may be performed at a temperature in the range of 400° C. to 900° C. in an oxygen atmosphere. The annealing process is performed in an oxygen atmosphere in order to suppress the composition ratio imbalance of the thin film and to improve the film quality by binding oxygen to defects in the thin film. In particular, this is because, as the thin film is formed using the atomic layer deposition method, point defects having a positive charge generated in the thin film can be removed.

11B , the first open portion 18 is expanded by etching the pre-source layer 14A exposed on the bottom surface of the first open portion 18 , but the expanded first open portion 18 is An etching process is performed to penetrate the first sacrificial layer 12 . This is to electrically connect the channel layer and the source layer to be formed through a subsequent process.

Next, the second sacrificial layer 20 is formed to gap-fill the expanded first open portion 18 . The second sacrificial layer 20 may be formed of a material having an etch selectivity to the first sacrificial layer 12 .

As shown in FIG. 11C , a second stacked body 21 in which the first material layer 15 and the second material layer 16 are alternately stacked a plurality of times is formed on the first stacked body 17 . In the second stacked body 21 , the first material film 15 may be positioned on the lowermost and uppermost layers, and the first material film 15 positioned on the lowermost and uppermost layers may have a relatively larger thickness.

Next, the second stacked body 21 is selectively etched until the second sacrificial layer 20 is exposed to form a second open portion 22 penetrating the second stacked body 21 . The second stacked body 21 and the second open portion 22 are for forming a plurality of memory cells.

Next, a memory layer 23 is formed on the sidewall of the second open portion 22 . The memory film 23 may be formed as a charge trap film or a multilayer film in which a charge trap film and a blocking film are stacked. The charge trap layer may include a nitride, and the blocking layer may include an oxide.

Next, a third sacrificial layer 24 is formed to gap-fill the second open portion 22 on which the memory layer 23 is formed. The third sacrificial layer 24 may be formed of the same material as the second sacrificial layer 20 .

As shown in FIG. 11D , a third stacked body 25 in which the first material layer 15 and the second material layer 16 are alternately stacked at least once or more is formed on the second stacked body 21 . . In the third stacked body 25 , the second material layer 16 may be positioned at the lowermost layer, and the first material layer 15 may be positioned at the uppermost layer. In addition, the first material layer 15 positioned on the uppermost layer of the third stacked body 25 may have a relatively larger thickness. This is to secure a space for forming a capping layer in a subsequent process.

Next, the third stacked body 25 is selectively etched until the second material layer 16 located at the lowermost layer of the third stacked body 25 is exposed to form the third open part 26 , A second ferroelectric film 27 is formed on the sidewall of the third open part 26 . The second ferroelectric layer 27 is a dielectric of the negative capacitor and may correspond to the second gate insulating layer 214 in the gate structure 510 of the second switching device 500 shown in FIG. 9 . The second ferroelectric film 27 may be formed in the same manner as the first ferroelectric film 19 .

Next, after forming the second material film 16 on the sidewall of the third open portion 26 on which the second ferroelectric film 27 is formed, the third stacked body 25 is maintained until the third sacrificial film 24 is exposed. ), the second material layer 16 positioned on the lowermost layer is etched to expand the third open part 26 . Here, the third stacked body 25 and the third open portion 26 are for forming a drain select transistor.

As shown in FIG. 11E , the third sacrificial film 24 and the second sacrificial film 20 are sequentially removed through the third open part 26 to form the first open part 18 and the second open part ( 22) and the third open part 26 form a channel hole 28 connected to each other.

Next, a tunnel insulating layer 29 and a channel layer 30 are sequentially formed along the surface of the channel hole 28 . Here, the surface of the channel hole 28 may be a side surface and a bottom surface of the channel hole 28 , the tunnel insulating film 29 may include an oxide, and the channel film 30 may include a semiconductor film. The semiconductor film used as the channel film 30 may be a silicon film not doped with impurities. The tunnel insulating layer 29 formed on the first stacked body 17 may be used as the first gate insulating layer 210 in the gate structure 410 of the first switching device 400 shown in FIG. 9 . In addition, the tunnel insulating layer 29 formed on the third stacked body 25 may be used as the first gate insulating layer 210 in the gate structure 510 of the second switching device 500 shown in FIG. 9 .

Next, the core pillar 31 is formed on the channel layer 30 to gap-fill the channel hole 28 . The core pillar 31 may include an oxide.

Next, the core pillar 31 is recessed to a predetermined thickness, and a capping layer 37 in contact with the channel layer 30 is formed in the recessed space. The capping layer 37 may be formed of a semiconductor layer doped with an impurity, for example, a silicon layer doped with an n-type impurity. The capping layer 37 may serve as a drain of the drain select transistor.

As shown in FIG. 11F , a fourth open portion penetrating through the first laminate 17 to the third laminate 25 and exposing the first sacrificial film 12 of the pre-source film 14A ( 32) is formed. The fourth open part 32 may be for forming a common source line 36 or a support structure. A plane of the fourth open part 32 may have a slit shape.

Next, an etching process of removing the second material layer 16 from the first stacked body 17 to the third stacked body 25 through the fourth open part 32 is performed. Through an etching process of selectively removing the second material layer 16 , a space for forming a plurality of gate conductive layers may be secured.

As shown in FIG. 11G , a plurality of gate conductive layers 33 are formed by gap-filling a conductive material in the space where the second material layer 16 is removed. A metallic material may be used as a conductive material for forming the plurality of gate conductive layers 33 . Here, the gate conductive film 33 formed on the first stacked body 17 is the first gate electrode 212 and the second gate electrode ( 216) can be used. The gate conductive layer 33 formed on the second stacked body 21 may be used as the gate electrode 236 of each of the plurality of memory cells MC1 to MCn shown in FIG. 9 . In addition, the gate conductive film 33 formed on the third stacked body 25 is the first gate electrode 212 and the second gate electrode ( 216) can be used.

Next, after performing a separation process for separating the plurality of stacked gate conductive layers 33 , for example, an etch-back process, a spacer 34 is formed on the sidewall of the fourth open part 32 . The spacer 34 may be formed of any one or two or more stacked layers selected from the group consisting of oxide, nitride, and oxynitride.

Next, an etching process is performed to remove the first sacrificial layer 12 exposed through the fourth open part 32 , and the tunnel insulating layer 29 exposed as the first sacrificial layer 12 is continuously removed. ) is selectively etched to expose the channel layer 30 .

11H , a conductive layer is formed to gap-fill the space where the first sacrificial layer 12 is removed. The conductive layer gap-filling the space in which the first sacrificial layer 12 is removed may be formed of a semiconductor layer, for example, the third silicon layer 35 doped with an n-type impurity. The third silicon layer 35 may be in contact with the channel layer 30 , and the impurity doping concentration of the third silicon layer 35 is higher than that of the first silicon layer 11 and the second silicon layer 13 . could be bigger

Accordingly, the source layer 14 including the first silicon layer 11 to the third silicon layer 35 and in contact with the channel layer 30 may be formed.

Next, the fourth open portion 32 is gap-filled and a common source line 36 in contact with the source layer 14 is formed. The common source line 36 may be formed of a semiconductor film or a multilayer film in which a semiconductor film and a metallic film are stacked. The semiconductor layer may be formed of a silicon layer doped with an n-type impurity, and may be formed together during the process of forming the third silicon layer 35 doped with the n-type impurity of the source line.

Meanwhile, in the present embodiment, the case in which the fourth open part 32 is formed on the common source line 36 is exemplified, but the present invention is not limited thereto. As a modification, a support structure for supporting the first stacked body 17 to the third stacked body 25 may be formed in the fourth open part 32 by being gap-filled with an insulating material.

12 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.

12 , the memory block BLK2 may include a source layer SL and a plurality of cell strings CS2 commonly connected to a plurality of word lines WL1 to WLn. In addition, the plurality of cell strings CS2 may be connected to the plurality of bit lines BL.

Each of the plurality of cell strings CS2 includes source select transistors SST1 and SST2 connected to the source layer SL, drain select transistors DST1 and DST2 connected to the bit line BL, and source select transistors SST1 . , SST2 and a plurality of memory cells MC1 to MCn connected in series between the drain select transistors DST1 and DST2. Each of the first source select transistor SST1 connected to the source layer SL and the second drain select transistor DST2 connected to the bit line BL may include a negative capacitor.

Gates of the plurality of memory cells MC1 to MCn may be respectively connected to a plurality of word lines WL1 to WLn that are spaced apart from each other and stacked. The plurality of word lines WL1 to WLn may be disposed between the source select lines SSL1 and SSL1 and the drain select lines DSL1 and DSL2 .

The first source select line SSL1 may be connected to the gate electrode of the first source select transistor SST1 , and the second source select line SSL2 may be connected to the first gate electrode of the second source select transistor SST2 . have. The source and drain of the first source select transistor SST1 may be connected to the source of the smok SL and the second source select transistor SST2 , respectively. A drain of the second source select transistor SST2 may be connected to the memory cell MC1 . In addition, the second source selection line SSL2 may be positioned above the first source selection line SSL1 .

The first drain select line DSL1 may be connected to the gate electrode of the first drain select transistor DST1 , and the second drain select line DSL2 may be connected to the second gate electrode of the second drain select transistor DST2 . have. A source and a drain of the first drain select transistor DST1 may be connected to the source of the memory cell MCn and the second drain select line DSL2, respectively. A drain of the second drain selection line DSL2 may be connected to the bit line BL. In addition, the second drain selection line DSL2 may be positioned above the first drain selection line DSL1 .

13 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention. And, FIG. 14 is an enlarged cross-sectional view of area B shown in FIG. 13 .

12 to 14 , the cell string CS2 according to the embodiment includes the channel structure 300 positioned between the source layer SL and the bit line BL, and a plurality of memory cells MC1 to MCn), the first switching element 400 and the second switching element 500 may be included.

The channel structure 300 connects between the source layer SL and the bit line BL stacked apart from each other and may have a vertical column shape. The channel structure 300 may include a core pillar 302 , a capping layer 306 , and a channel layer 304 . The channel structure 300 may have substantially the same configuration and shape as the channel structure 300 illustrated in FIG. 9 . Accordingly, an additional detailed description of the channel structure 300 will be omitted.

The plurality of memory cells MC1 to MCn surround the channel structure 300 and may have a stacked shape spaced apart from each other. Among the plurality of memory cells MC1 to MCn, the memory cells MC1 and MCn positioned adjacent to each of the first switching element 400 and the second switching element 500 may be used as dummy cells. Each of the plurality of memory cells MC1 to MCn may include a memory structure MS surrounding the channel structure 300 . The memory structure MS may have substantially the same configuration as the second gate stack GS2 shown in FIG. 3 . Also, the memory structure MS may have substantially the same configuration and shape as the memory structure MS shown in FIGS. 9 and 10 . Accordingly, an additional detailed description of the memory structure MS will be omitted.

The first switching device 400 and the second switching device 500 each have a gap 208 with the first gate structures 420 and 520 including negative capacitors and the first gate structures 420 and 520 and adjacent to each other. It may include second gate structures 430 and 530 . The first switching element 400 and the second switching element 500 may each share a channel structure 300 and may be located on one side and the other side of the memory cells MC1 to MCn. Specifically, the first switching element 400 may be positioned between the source layer SL and the memory cells MC1 to MCn, and the second switching element 500 may include the bit line BL and the memory cells MC1 to MCn. It can be located between MC1~MCn). Accordingly, the first switching element 400 may act as a source select transistor SST, and the second switching element 500 may act as a drain select transistor DST. In the direction in which the channel structure 300 extends, that is, in the channel length direction, the first switching element 400 and the second switching element 500 may have symmetrical shapes.

Each of the first switching device 400 and the second switching device 500 has a first gate structure 420 and 520 and a second gate structure 430 having a gate all around (GAA) structure surrounding the channel structure 300 . , 530) may be included.

The first gate structures 420 and 520 may have substantially the same configuration as the first gate stack GS1 illustrated in FIG. 3 . That is, the first gate structures 420 and 520 include the first gate insulating layer 220 surrounding the channel layer 304 and the second gate insulating layer 220 surrounding the first gate insulating layer 220 and including a ferroelectric having a spontaneously induced negative capacitance. The gate insulating layer 222 and the second gate insulating layer 222 may include a first gate electrode 224 having a flat plate shape. The first gate structures 420 and 520 have substantially the same configuration as the first gate stack GS1 shown in FIG. 3 , and thus a detailed description thereof will be omitted.

The second gate structures 430 and 530 may have substantially the same configuration as the second gate stack GS2 shown in FIG. 3 . In addition, the second gate structures 430 and 530 may have substantially the same configuration as the memory structures MS of each of the plurality of memory cells MC1 to MCn. That is, the second gate structures 430 and 530 include a tunnel insulating layer 230 surrounding the channel layer 304 , a charge trap layer 232 surrounding the tunnel insulating layer 230 , and a blocking layer surrounding the charge trap layer 232 . 234 ) and a second gate electrode 236 surrounding the blocking film 234 and having a flat plate shape. Since the second gate structures 430 and 530 have substantially the same configuration as the second gate stack GS2 shown in FIG. 3 , a detailed description thereof will be omitted.

In each of the first gate structure 420 and the second gate structure 430 of the first switching device 400 , the first gate electrode 224 and the second gate electrode 236 are connected to the first source selection line SSL1 , respectively. and a second source selection line SSL2. Accordingly, each of the first gate structure 420 and the second gate structure 430 of the first switching device 400 may function as a gate of the first source select transistor SST1 and the second source select transistor SST2. .

In each of the first gate structure 520 and the second gate structure 530 of the second switching device 500 , the first gate electrode 224 and the second gate electrode 236 are connected to the second drain selection line DSL2 , respectively. and a first drain selection line DSL1 . Accordingly, each of the first gate structure 520 and the second gate structure 530 of the second switching device 500 may function as a gate of the second drain select transistor DST2 and the first drain select transistor DST1 . .

The turn-on operation and turn-off operation of the first switching element 400 and the second switching element 500 may be substantially the same as those illustrated in FIG. 4 . In addition, a known method may be used for the program operation, the erase operation, and the read operation of the source layer SL, the bit line BL, and the memory cells MC1 to MCn.

Meanwhile, in the present embodiment, the case in which each of the first switching element 400 and the second switching element 500 includes a negative capacitor is exemplified, but the present invention is not limited thereto. As a modification, only one of the first switching element 400 and the second switching element 500 may include a negative capacitor.

As described above, the semiconductor memory device according to the present embodiment includes the first switching device 400 and the second switching device 500 having a negative capacitor, thereby improving the operating speed and operating reliability of the semiconductor memory device. can

15A to 15I are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention. For reference, FIGS. 15A to 15I are provided to explain an example of the method of manufacturing the semiconductor memory device illustrated in FIGS. 12 to 14 , and cross-sectional shapes may be partially different from those illustrated in FIG. 13 for process reasons.

As shown in FIG. 15A , a pre-source layer 54A is formed on the substrate 50 on which a predetermined structure, for example, a peripheral circuit is formed. The pre-source layer 54A may be formed in a form in which the first sacrificial layer 52 is inserted between the semiconductor layers doped with impurities. For example, in the pre-source layer 54A, a first silicon layer 51 doped with n-type impurities, a first sacrificial layer 52 , and a second silicon layer 53 doped with n-type impurities are sequentially formed. It can be formed as a laminated laminated film.

Meanwhile, although not shown in the drawings, a separation insulating layer may be formed between the pre-source layer 54A and the substrate 50 before the pre-source layer 54A is formed. The isolation insulating layer electrically separates the pre-source layer 54A and the substrate 50 and may serve to prevent the substrate 50 from being damaged between processes.

Next, after forming the first stacked body 57 in which the first material layer 55 and the second material layer 56 are alternately stacked at least once or more, the first stacked body 57 and the pre-source layer are formed. A first open portion 58 passing through the first sacrificial film 52 of 54A is formed. The first stacked body 57 and the first open portion 58 are for forming a source select transistor. The first material layer 55 may be positioned on the lowermost layer and the uppermost layer of the first stacked body 57 . Through a subsequent process, the first material layer 55 may function as an interlayer insulating layer separating the stacked gate conductive layers, and the second material layer 56 may function as a sacrificial layer for forming the gate conductive layer. To this end, the first material layer 55 may be formed of a material having an etch selectivity to the second material layer 56 . For example, the first material layer 55 may include an oxide, and the second material layer 56 may include a nitride.

As shown in FIG. 15B , a first ferroelectric film 59 is formed along the surface of the first open part 58 . A surface of the first open part 58 may be a side surface and a bottom surface of the first open part 58 . Here, the first ferroelectric film 59 is a dielectric of the negative capacitor and may serve as a second gate insulating film of the first selection transistor. The first ferroelectric film 59 may be formed at a temperature of 300° C. or less by using an atomic layer deposition method. And, after the thin film deposition is completed, an annealing process may be performed at a temperature in the range of 400°C to 900°C.

Next, a second sacrificial film 60 for gap-filling the first open portion 58 is formed on the first ferroelectric film 59 . The second sacrificial film 60 may serve to protect the first ferroelectric film 59 between subsequent processes.

As shown in FIG. 15C , a second stacked body 61 in which the first material layer 55 and the second material layer 56 are alternately stacked a plurality of times is formed. In the second stacked body 61 , the second material film 56 may be positioned on the lowermost layer, the first material film 55 may be positioned on the uppermost layer, and the first material film 55 positioned on the uppermost layer is It may have a relatively larger thickness. This is to secure a space for forming a capping layer in a subsequent process.

Next, after forming the second open portion 62 exposing the second sacrificial film 60 by selectively etching the second stacked body 61 , the memory film ( 63) is formed. The memory layer 63 may be formed as a charge trap layer or a stacked layer in which a charge trap layer and a blocking layer are stacked. The charge trap layer may include a nitride, and the blocking layer may include an oxide.

As shown in FIG. 15D , the channel hole through which the first open part 58 and the second open part 62 are interconnected is formed by removing the second sacrificial film 60 exposed through the second open part 62 . After forming, a tunnel insulating film 64 and a channel film 65 are sequentially formed along the surface of the channel hole. The tunnel insulating layer 64 may include an oxide, and the channel layer 65 may include a semiconductor layer. The tunnel insulating layer 64 formed on the first stacked body 57 may act as a gate insulating layer of the source select transistor.

Next, a core pillar 66 is formed on the channel layer 65 to gap-fill the channel hole. The core pillar 66 may include an oxide.

Next, the second stacked body 61 , the memory layer 63 , the tunnel insulating layer 64 , the channel layer 65 , and a portion of the core pillar 66 are selectively etched to form a third open part 67 . . The third open part 67 is for forming a second selection transistor, and is formed to penetrate through at least the second material layer 56 positioned at the top of the second material layers 56 of the second stacked body 61 . can be formed

As shown in FIG. 15E , a second ferroelectric film 68 is formed on the sidewall of the third open part 67 . The second ferroelectric layer 68 is a negative capacitor dielectric, and may include a ferroelectric having a spontaneously induced negative capacitance.

Next, a tunnel insulating layer 64 , a channel layer 65 , and a core pillar 66 are sequentially formed on the sidewall of the third open part 67 on which the second ferroelectric layer 68 is formed. The tunnel insulating layer 64 may act as a gate insulating layer of the drain select transistor.

Meanwhile, in the present embodiment, the third open portion 67 is formed, and after the second ferroelectric film 68 is formed, the tunnel insulating film 64 , the channel film 65 and the core pillar 66 are formed again. The case has been exemplified, but the present invention is not limited thereto. As a modification, the tunnel insulating film 64 , the channel film 65 and The core pillars 66 may be formed at once. For example, after forming the second open portion 62 , a sacrificial film partially filling the second open portion 62 is formed, and a second ferroelectric film 68 is formed on the sidewall of the upper end of the second open portion 62 . After forming the sacrificial layers in the first open part 58 and the second open part 62 , the tunnel insulating layer 64 , the channel layer 65 , and the core pillar 66 may be sequentially formed. .

Next, after the core pillar 66 is recessed to a predetermined thickness, a capping layer 69 in contact with the channel layer 65 is formed in the recessed space. The capping film 69 may be formed of a semiconductor film doped with an impurity, for example, a silicon film doped with an n-type impurity. The capping layer 69 may serve as a junction region of the second selection transistor, for example, a drain.

As shown in FIG. 15F , a fourth open part penetrating through the first laminate 57 and the second laminate 61 and exposing the first sacrificial film 52 of the pre-source film 54A ( 70) is formed. The fourth open part 70 may be for forming the common source line 74 or a support structure. A plane of the fourth open part 70 may have a slit shape.

Next, the second material layer 56 is removed from the first stacked body 57 and the second stacked body 61 through the fourth open part 70 . Through an etching process of selectively removing the second material layer 56 , a space for forming the gate conductive layer may be secured.

As shown in FIG. 15G , a plurality of gate conductive layers 71 are formed by gap-filling a conductive material in the space where the second material layer 56 is removed. A metallic material may be used as a conductive material for forming the gate conductive film.

Next, after performing a separation process for separating the plurality of stacked gate conductive layers 71 , for example, an etch-back process, a spacer 72 is formed on the sidewall of the fourth open part 70 . The spacer 72 may be formed of any one or two or more stacked layers selected from the group consisting of oxide, nitride, and oxynitride.

As shown in FIG. 15H , the first sacrificial layer 52 of the pre-source layer 54A exposed through the fourth open part 70 is removed, and as the first sacrificial layer 52 is removed, it is exposed. The tunnel insulating layer 64 and the first ferroelectric layer 59 are sequentially removed to expose the channel layer 65 .

As shown in FIG. 15I , a conductive layer is formed to gap-fill the space where the first sacrificial layer 52 is removed. The conductive layer gap-filling the space from which the first sacrificial layer 52 is removed may be formed of a semiconductor layer, for example, the third silicon layer 73 doped with an n-type impurity. The third silicon layer 73 may be in contact with the channel layer 65 , and the impurity doping concentration of the third silicon layer 73 is higher than that of the first silicon layer 51 and the second silicon layer 53 . could be bigger

Accordingly, the source film 54 including the first silicon film 51 to the third silicon film 73 and in contact with the channel film 65 may be formed.

Next, the fourth open portion 70 is gap-filled and a common source line 74 in contact with the source layer 54 is formed. The common source line 74 may be formed of a semiconductor film or a stacked film in which a semiconductor film and a metallic film are stacked. The semiconductor film may be formed of a silicon film doped with an n-type impurity, and may be formed together during the process of forming the third silicon film 73 doped with the n-type impurity of the source line.

Meanwhile, in the present embodiment, the case in which the fourth open portion 70 is formed on the common source line 74 has been exemplified, but the present invention is not limited thereto. As a modification, an insulating material may be gap-filled in the fourth open part 70 to form a support structure supporting the first stacked body 57 to the third stacked body.

16 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.

16 , the memory block BLK3 may include a source layer SL and a plurality of cell strings CS3 commonly connected to a plurality of word lines WL1 to WLn. In addition, the plurality of cell strings CS3 may be connected to the plurality of bit lines BL.

Each of the plurality of cell strings CS3 includes source select transistors SST1 and SST2 connected to the source layer SL, drain select transistor DST and source select transistors SST1 and SST2 connected to the bit line BL. and a plurality of memory cells MC1 to MCn connected in series between the drain select transistor DST. Each of the first source select transistor SST1 connected to the source layer SL and the drain select transistor DST connected to the bit line BL may include a negative capacitor.

Gates of the plurality of memory cells MC1 to MCn may be respectively connected to a plurality of word lines WL1 to WLn that are spaced apart from each other and stacked. The plurality of word lines WL1 to WLn may be disposed between the source select lines SSL1 and SSL1 and the drain select lines DSL1 and DSL2 .

The first source select line SSL1 may be connected to the gate electrode of the first source select transistor SST1 , and the second source select line SSL2 may be connected to the first gate electrode of the second source select transistor SST2 . have. The source and drain of the first source select transistor SST1 may be connected to the source of the smok SL and the second source select transistor SST2 , respectively. A drain of the second source select transistor SST2 may be connected to the memory cell MC1 . In addition, the second source selection line SSL2 may be positioned above the first source selection line SSL1 .

The first drain select line DSL1 may be connected to a first gate electrode of the drain select transistor DST, and the second drain select line DSL2 may be connected to a second gate electrode of the drain select transistor DST. Here, the first gate electrode of the drain select transistor DST may serve to control the negative capacitance. In addition, the second gate electrode of the drain select transistor DST may serve to control channel on/off.

17 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention.

16 and 17 , the cell string CS3 according to the embodiment includes a channel structure 300 positioned between the source layer SL and the bit line BL, and a plurality of memory cells MC1 to MCn), the first switching element 400 and the second switching element 500 may be included.

The channel structure 300 connects between the source layer SL and the bit line BL stacked apart from each other and may have a vertical column shape. The channel structure 300 may include a core pillar 302 , a capping layer 306 , and a channel layer 304 . The channel structure 300 may have substantially the same configuration and shape as the channel structure 300 illustrated in FIG. 9 . Accordingly, an additional detailed description of the channel structure 300 will be omitted.

The plurality of memory cells MC1 to MCn surround the channel structure 300 and may have a stacked shape spaced apart from each other. Among the plurality of memory cells MC1 to MCn, the memory cells MC1 and MCn positioned adjacent to each of the first switching element 400 and the second switching element 500 may be used as dummy cells. Each of the plurality of memory cells MC1 to MCn may include a memory structure MS surrounding the channel structure 300 . The memory structure MS may have substantially the same configuration as the second gate stack GS2 shown in FIG. 3 . Also, the memory structure MS may have substantially the same configuration and shape as the memory structure MS shown in FIGS. 9 and 10 . Accordingly, an additional detailed description of the memory structure MS will be omitted.

The first switching element 400 may include a first source select transistor SST1 and a second source select transistor SST2 . The first switching device 400 may include a first gate structure 420 including a negative capacitor and a second gate structure 430 adjacent to the first gate structure 420 with a gap. The first gate structure 420 may include a ferroelectric having a spontaneously induced negative capacitance. The first switching element 400 may have substantially the same configuration as the switching element SE2 illustrated in FIG. 3 . Also, the first switching element 400 may have substantially the same configuration and shape as the first switching element 400 illustrated in FIGS. 13 and 14 . Accordingly, an additional detailed description of the first switching element 400 will be omitted.

The second switching device 500 may include a drain select transistor DST. The second switching device 500 may include a gate structure 510 including a negative capacitor. The first gate structure 510 may optionally include a ferroelectric having a negative capacitance. The second switching element 500 may have substantially the same configuration as the switching element SE1 illustrated in FIG. 1 . Also, the second switching element 500 may have substantially the same configuration and shape as the second switching element 500 illustrated in FIGS. 9 and 10 . Accordingly, an additional detailed description of the second switching element 500 will be omitted.

The turn-on operation and the turn-off operation of the first switching element 400 may be substantially the same as those illustrated in FIG. 4 . The turn-on operation and the turn-off operation of the second switching element 500 may be substantially the same as those illustrated in FIG. 2 . In addition, a known method may be used for the program operation, the erase operation, and the read operation of the source layer SL, the bit line BL, and the memory cells MC1 to MCn.

As described above, the semiconductor memory device according to the present embodiment includes the first switching device 400 and the second switching device 500 having a negative capacitor, thereby improving the operating speed and operating reliability of the semiconductor memory device. can

Here, the first switching device 400 includes a ferroelectric having a negative capacitance spontaneously induced by a dielectric film of a negative capacitor, and includes a first gate structure 420 and a second gate structure 430 that can be independently controlled. As a result, it is possible to control the plurality of cell strings CS3 at a high speed without increasing the stacked number of the source select transistors SST1 and SST2.

In addition, the second switching device 500 includes a ferroelectric selectively having a negative capacitance as a dielectric layer of a negative capacitor, and selectively controls a capacitance polarity and a potential level of a capacitance channel using a bias applied to the gate structure 510 . Therefore, it is possible to improve the operation speed and operation reliability of the semiconductor memory device. In particular, the reliability of the erase operation may be improved.

18 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.

18 , the memory block BLK4 may include a source layer SL and a plurality of cell strings CS4 commonly connected to a plurality of word lines WL1 to WLn. In addition, the plurality of cell strings CS4 may be connected to the plurality of bit lines BL.

Each of the plurality of cell strings CS4 includes source select transistors SST1 to SST3 connected to the source layer SL, drain select transistor DST and source select transistors SST1 to SST3 connected to the bit line BL. and a plurality of memory cells MC1 to MCn connected in series between the drain select transistor DST. Here, each of the source select transistors SST1 to SST3 and the drain select transistor DST may include a negative capacitor.

Gates of the plurality of memory cells MC1 to MCn may be respectively connected to a plurality of word lines WL1 to WLn that are spaced apart from each other and stacked. The plurality of word lines WL1 to WLn may be disposed between the source select lines SSL1 to SSL4 and the drain select lines DSL1 and DSL2 .

The first source select line SSL1 may be connected to the gate electrode of the first source select transistor SST1 , and the second source select line SSL2 may be connected to the gate electrode of the second source select transistor SST2 . In addition, each of the third source selection line SSL3 and the fourth source selection line SSL4 may be connected to the first gate electrode and the second gate electrode of the third source selection transistor SST3 . The first source select transistor SST1 to the third source select transistor SST3 may be connected in series, and one side of the first source select transistor SST1 may be connected to the source film SL, and the third source select transistor The other end of the SST3 may be connected to the memory cell MC1 .

The first drain select line DSL1 may be connected to a first gate electrode of the drain select transistor DST, and the second drain select line DSL2 may be connected to a second gate electrode of the drain select transistor DST.

19 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention.

18 and 19 , the cell string CS4 according to the embodiment includes the channel structure 300 and the plurality of memory cells MC1 to located between the source layer SL and the bit line BL. MCn), the first switching element 400 and the second switching element 500 may be included.

The channel structure 300 connects between the source layer SL and the bit line BL stacked apart from each other and may have a vertical column shape. The channel structure 300 may include a core pillar 302 , a capping layer 306 , and a channel layer 304 . The channel structure 300 may have substantially the same configuration and shape as the channel structure 300 illustrated in FIG. 9 . Accordingly, an additional detailed description of the channel structure 300 will be omitted.

The plurality of memory cells MC1 to MCn surround the channel structure 300 and may have a stacked shape spaced apart from each other. Among the plurality of memory cells MC1 to MCn, the memory cells MC1 and MCn positioned adjacent to each of the first switching element 400 and the second switching element 500 may be used as dummy cells. Each of the plurality of memory cells MC1 to MCn may include a memory structure MS surrounding the channel structure 300 . The memory structure MS may have substantially the same configuration as the second gate stack GS2 shown in FIG. 3 . Also, the memory structure MS may have substantially the same configuration as the memory structure MS shown in FIGS. 9 and 10 . Accordingly, an additional detailed description of the memory structure MS will be omitted.

The second switching device 500 may include a drain select transistor DST. The second switching device 500 may include a gate structure 540 including a negative capacitor. The gate structure 540 may optionally include a ferroelectric having a negative capacitance. The second switching element 500 may have substantially the same configuration as the switching element SE1 illustrated in FIG. 1 . Also, the second switching element 500 may have substantially the same configuration and shape as the second switching element 500 illustrated in FIGS. 9 and 10 . Accordingly, an additional detailed description of the second switching element 500 will be omitted.

The first switching element 400 may include first source select transistors SST1 to third source select transistors SST3 . The first switching device 400 may include a first gate structure 440 to a third gate structure 460 each having a negative capacitor and being spaced apart from each other and stacked. Here, each of the first gate structure 440 and the second gate structure 450 may have substantially the same configuration as the first gate stack GS1 illustrated in FIG. 3 . Accordingly, each of the first gate structure 440 and the second gate structure 450 may include a ferroelectric having a spontaneously induced negative capacitance. In addition, each of the first gate structure 440 and the second gate structure 450 may have substantially the same configuration and shape as the second gate structure 430 of the first switching device 400 illustrated in FIG. 13 . . Accordingly, an additional detailed description of the first gate structure 440 and the second gate structure 450 of the first switching device 400 will be omitted.

In the first switching device 400 , the third gate structure 460 may have substantially the same configuration as the gate stack GS shown in FIG. 1 . Accordingly, the third gate structure 460 may selectively include a ferroelectric having a negative capacitance. Also, the third gate structure 460 may have substantially the same configuration and shape as the gate structure 410 of the first switching device 400 illustrated in FIG. 9 . Accordingly, an additional detailed description of the third gate structure 460 of the first switching device 400 will be omitted.

While the second switching element 500 is configured with one drain select transistor DST, the first switching element 400 has first to third source select transistors SST1 to SST3 spaced apart from each other and stacked. ) may be due to the shape of the channel structure 300 . Specifically, the diameter of the lower end of the channel structure 300 at which the first switching element 400 is located is inevitably smaller than the diameter of the upper end at which the second switching element 500 is located due to process reasons. Accordingly, if the first switching device 400 includes more transistors than the second switching device 500 , the effect on the memory cell MC1 adjacent to the first switching device 400 may be reduced. In addition, since the threshold voltage of the transistors positioned at the lower end of the channel structure 300 having a relatively small diameter respond more sensitively to the bias applied to the gate electrode, the operating characteristics may be improved. That is, when the first switching element 400 includes more transistors than the second switching element 500 , the operation reliability of the semiconductor memory device may be improved.

In the first switching device 400 , the turn-on operation and the turn-off operation of the first gate structure 440 and the second gate structure 450 may be substantially the same as those illustrated in FIG. 4 . The turn-on operation and turn-off operation of the third gate structure 460 of the first switching element 400 and the first switching element 500 may be substantially the same as those illustrated in FIG. 2 . In addition, a known method may be used for the program operation, the erase operation, and the read operation of the source layer SL, the bit line BL, and the memory cells MC1 to MCn.

As described above, the semiconductor memory device according to the present embodiment includes the first switching device 400 and the second switching device 500 having a negative capacitor, thereby improving the operating speed and operating reliability of the semiconductor memory device. can

Here, the first switching device 400 includes a ferroelectric having a negative capacitance spontaneously induced by a dielectric film of a negative capacitor, and includes a first gate structure 440 and a second gate structure 450 that can be independently controlled. As a result, it is possible to control the plurality of cell strings CS4 at a high speed without increasing the stacked number of the source selection transistors SST1 to SST3 .

In addition, the first switching device 400 includes a third gate structure 460 including a ferroelectric selectively having a negative capacitance as a dielectric film of a negative capacitor, so that a bias applied to the third gate structure 460 is used. Since the capacitance polarity and the potential level of the capacitance channel can be selectively controlled, the operation speed and operation reliability of the semiconductor memory device can be improved.

20 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 20 , the memory block BLK5 may include a source layer SL and a plurality of cell strings CS5 commonly connected to a plurality of word lines WL1 to WLn. In addition, the plurality of cell strings CS5 may be connected to the plurality of bit lines BL.

Each of the plurality of cell strings CS5 includes source select transistors SST1 to SST3 connected to the source layer SL, drain select transistors DST1 and DST2 connected to the bit line BL, and source select transistors SST1 . to SST3) and a plurality of memory cells MC1 to MCn connected in series between the drain select transistors DST1 and DST2. Here, each of the source select transistors SST1 to SST3 and the drain select transistors DST1 and DST2 may include a negative capacitor.

Gates of the plurality of memory cells MC1 to MCn may be respectively connected to a plurality of word lines WL1 to WLn that are spaced apart from each other and stacked. The plurality of word lines WL1 to WLn may be disposed between the source select lines SSL1 to SSL4 and the drain select lines DSL1 to DSL3 .

The first source select line SSL1 may be connected to the gate electrode of the first source select transistor SST1 , and the second source select line SSL2 may be connected to the gate electrode of the second source select transistor SST2 . In addition, each of the third source selection line SSL3 and the fourth source selection line SSL4 may be connected to the first gate electrode and the second gate electrode of the third source selection transistor SST3 . The first source select transistor SST1 to the third source select transistor SST3 may be connected in series, and one side of the first source select transistor SST1 may be connected to the source film SL, and the third source select transistor The other end of the SST3 may be connected to the memory cell MC1 .

The first drain selection line DSL1 and the second drain selection line DSL2 may be respectively connected to the first gate electrode and the second gate electrode of the first drain selection transistor DST1 . In addition, the third drain select line DSL3 may be connected to the gate electrode of the second drain select transistor DST2 . The first drain select transistor DST1 and the second drain select transistor DST2 may be connected in series, and one side of the first drain select transistor DST1 may be connected to the memory cell MCn, and the second drain select transistor DST1 may be connected to the memory cell MCn. The other end of the DST2 may be connected to the bit line BL.

21 is a perspective view illustrating a cell string of a semiconductor memory device according to an embodiment of the present invention.

20 and 21 , the cell string CS5 according to the embodiment includes the channel structure 300 and the plurality of memory cells MC1 to located between the source layer SL and the bit line BL. MCn), the first switching element 400 and the second switching element 500 may be included. Here, the channel structure 300, the plurality of memory cells MC1 to MCn, and the first switching element 400 include the channel structure 300, the plurality of memory cells MC1 to MCn and the first switching element 400 shown in FIG. The first switching element 400 may have substantially the same configuration and shape. Accordingly, additional detailed descriptions thereof will be omitted.

The second switching element 500 may include a first drain select transistor DST1 and a second drain select transistor DST2 . The second switching device 500 may include a first gate structure 540 and a second gate structure 550 each including a negative capacitor.

In the second switching device 500 , the first gate structure 540 may have substantially the same configuration as the gate stack GS shown in FIG. 1 . Accordingly, the first gate structure 540 may selectively include a ferroelectric having a negative capacitance. Also, the first gate structure 540 may have substantially the same configuration and shape as the gate structure 510 of the second switching device 500 illustrated in FIG. 9 . Accordingly, an additional detailed description of the first gate structure 540 of the second switching device 500 will be omitted.

In the second switching device 500 , the second gate structure 550 may have substantially the same configuration as the first gate stack GS1 illustrated in FIG. 3 . Accordingly, the second gate structure 550 may include a ferroelectric having a spontaneously induced negative capacitance. Also, the second gate structure 550 may have substantially the same configuration and shape as the second gate structure 530 of the second switching device 500 illustrated in FIG. 13 . Accordingly, an additional detailed description of the second gate structure 550 of the second switching device 500 will be omitted.

In the first switching device 400 , the turn-on operation and the turn-off operation of the first gate structure 440 and the second gate structure 450 may be substantially the same as those illustrated in FIG. 4 . Also, a turn-on operation and a turn-off operation of the second gate structure 550 in the second switching device 500 may be substantially the same as those illustrated in FIG. 4 . The turn-on operation and turn-off operation of the third gate structure 460 of the first switching element 400 and the first gate structure 540 of the first switching element 500 may be substantially the same as those shown in FIG. 2 . have. In addition, a known method may be used for the program operation, the erase operation, and the read operation of the source layer SL, the bit line BL, and the memory cells MC1 to MCn.

As described above, the semiconductor memory device according to the present embodiment includes the first switching device 400 and the second switching device 500 having a negative capacitor, thereby improving the operating speed and operating reliability of the semiconductor memory device. can

Here, the second switching device 500 includes a first gate structure 540 including a ferroelectric selectively having a negative capacitance as a dielectric film of a negative capacitor, and using a bias applied to the first gate structure 540 . Since the capacitance polarity and the potential level of the capacitance channel can be selectively controlled, the operation speed and operation reliability of the semiconductor memory device can be improved.

In addition, the second switching element 500 includes a second gate structure 550 including a ferroelectric having a negative capacitance spontaneously induced by the dielectric film of the negative capacitor, thereby improving the operation speed and operation reliability of the semiconductor memory device. have. In particular, the reliability of the erase operation may be improved.

22 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present invention.

22 , the memory system 1100 includes a memory device 1120 and a memory controller 1110 .

The memory device 1120 may include a plurality of memory cells sharing a channel structure and a first switching element connected to one side of the memory cells by sharing a channel structure and including a negative capacitor. The first switching device includes a first gate insulating layer surrounding the channel structure, a first gate electrode surrounding the first gate insulating layer, and a ferroelectric having a negative capacitance in response to a bias applied to the first gate electrode and surrounding a portion of the first gate electrode. The second gate insulating layer including the second gate insulating layer and the second gate electrode surrounding the second gate insulating layer and having a flat plate shape may be included.

Meanwhile, the memory device 1120 includes a plurality of memory cells sharing a channel structure and a first switching element connected to one side of the memory cells by sharing a channel structure, and including a negative capacitor, wherein the first switching element is It may include a first gate structure and a second gate structure stacked spaced apart from each other. The first gate structure includes a first gate insulating layer surrounding the channel structure, a second gate insulating layer surrounding the first gate insulating layer and including a ferroelectric having a spontaneously induced negative capacitance, and a first gate electrode having a flat plate shape surrounding the second gate insulating layer. may include. In addition, the second gate structure may include a memory film that surrounds the channel structure and includes a charge trap film, and a second gate electrode that surrounds the memory film and has a flat plate shape.

Since the memory device 1120 includes a switching element including a negative capacitor, an operation speed and operation reliability of the memory device 1120 may be improved.

The memory device 1120 may be a multi-chip package including a plurality of flash memory chips.

The memory controller 1110 is configured to control the memory device 1120 , and includes a static random access memory (SRAM) 1111 , a central processing unit (CPU) 1112 , a host interface 1113 , and an error correction block. ) 1114 , and a memory interface 1115 . The SRAM 1111 is used as an operation memory of the CPU 1112 , the CPU 1112 performs various control operations for data exchange of the memory controller 1110 , and the host interface 1113 is connected to the memory system 1100 . The host's data exchange protocol is provided. Also, the error correction block 1114 detects and corrects errors included in data read from the memory device 1120 , and the memory interface 1115 interfaces with the memory device 1120 . In addition, the memory controller 1110 may further include a read only memory (ROM) that stores code data for interfacing with the host.

23 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present invention.

As shown in FIG. 23 , the computing system 1200 includes a CPU 1220 electrically connected to a system bus 1260 , a random access memory (RAM) 1230 , a user interface 1240 , a modem 1250 , and a memory system. (1210). The computing system 1200 may be a mobile device.

The memory system 1210 may include a plurality of memory cells sharing a channel structure and a first switching device connected to one side of the memory cells by sharing a channel structure and including a negative capacitor. The first switching device includes a first gate insulating layer surrounding the channel structure, a first gate electrode surrounding the first gate insulating layer, and a ferroelectric having a negative capacitance in response to a bias applied to the first gate electrode and surrounding a portion of the first gate electrode. The second gate insulating layer including the second gate insulating layer and the second gate electrode surrounding the second gate insulating layer and having a flat plate shape may be included.

Meanwhile, the memory system 1210 includes a plurality of memory cells sharing a channel structure and a first switching element connected to one side of the memory cells by sharing a channel structure, and including a negative capacitor, wherein the first switching element is It may include a first gate structure and a second gate structure stacked spaced apart from each other. The first gate structure includes a first gate insulating layer surrounding the channel structure, a second gate insulating layer surrounding the first gate insulating layer and including a ferroelectric having a spontaneously induced negative capacitance, and a first gate electrode having a flat plate shape surrounding the second gate insulating layer. may include. In addition, the second gate structure may include a memory film that surrounds the channel structure and includes a charge trap film, and a second gate electrode that surrounds the memory film and has a flat plate shape.

Since the memory system 1210 includes a switching element including a negative capacitor, an operation speed and operational reliability of the memory system 1210 may be improved.

Although the present invention has been described in detail with reference to a preferred embodiment, the present invention is not limited to the above embodiment, and various modifications can be made by those skilled in the art within the scope of the technical spirit of the present invention. do.

GS: gate stack 200: substrate
202: junction region 204: channel
210: first gate insulating layer 212: first gate electrode
212A: first area 212B: second area
214: second gate insulating film 216: second gate electrode
Von1: first turn-on voltage Von2: second turn-on voltage
VLoff: off voltage level VL1: first voltage level
VL2: second voltage level VL3: third voltage level

Claims (64)

a first gate insulating film formed on the substrate;
a second gate insulating layer formed on the first gate insulating layer, overlapping a portion of the first gate insulating layer, and including a ferroelectric;
a second gate electrode formed on the second gate insulating layer; and
A first gate electrode interposed between the first gate insulating layer and the second gate insulating layer and selectively controlling the second gate insulating layer to have a negative capacitance
A switching device comprising a. According to claim 1,
wherein the first gate electrode includes a first region interposed between the first gate insulating layer and the second gate insulating layer, and a second region extending from the first region and adjacent to the sidewall of the second gate electrode having a gap. switching element. 3. The method of claim 2,
A line width of the gap is at least greater than a thickness of the first gate insulating layer. According to claim 1,
The second gate insulating layer is a switching device including a metal oxide having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, and a monoclinic system. 5. The method of claim 4,
The second gate insulating layer has a thickness in the range of 1 nm to 20 nm. According to claim 1,
In an off state, each of the first gate electrode and the second gate electrode has an off voltage level, and a first turn-on voltage and a second turn-on voltage are applied to each of the first gate electrode and the second gate electrode during a turn-on operation period. becomes,
The first turn-on voltage sweeps from the off-voltage level to a first voltage level lower than the off-voltage level, successively higher than the off-voltage level at the first voltage level, and having a polarity different from the first voltage level configured to sweep to a second voltage level,
and the second turn-on voltage is configured to sweep from the off-voltage level to a third voltage level higher than the off-voltage level. 7. The method of claim 6,
A switching device configured to sweep the first turn-on voltage from the off voltage level to the first voltage level earlier than when the second turn-on voltage sweeps from the off voltage level to the third voltage level. 7. The method of claim 6,
The off voltage level includes a ground potential, the first voltage level has a negative polarity, and the second voltage level and the third voltage level have a positive polarity. a first gate stack formed on the substrate; and
at least one or more second gate stacks formed on the substrate to be adjacent to the first gate stack;
The first gate stack includes a first gate insulating layer sequentially stacked on the substrate, a first gate electrode, a second gate insulating layer including a ferroelectric having a negative capacitance in response to a bias applied to the first gate electrode, and a second gate insulating layer. 2 gate electrodes,
and the second gate stack includes a third gate insulating layer sequentially stacked on the substrate, a fourth gate insulating layer including a ferroelectric having a spontaneously induced negative capacitance, and a third gate electrode. 10. The method of claim 9,
the second gate insulating layer overlaps a portion of the first gate insulating layer;
wherein the first gate electrode includes a first region interposed between the first gate insulating layer and the second gate insulating layer, and a second region extending from the first region and adjacent to the sidewall of the second gate electrode having a gap. switching element. 11. The method of claim 10,
A line width of the gap is at least greater than a thickness of the first gate insulating layer and smaller than a distance between the first gate stack and the second gate stack. 11. The method of claim 10,
One side wall of the second gate electrode faces the third gate electrode, and the other side wall of the second gate electrode faces the second region of the first gate electrode. 10. The method of claim 9,
Each of the second gate insulating layer and the fourth gate insulating layer includes a metal oxide having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, and a monoclinic system. 14. The method of claim 13,
A thickness of the second gate insulating layer is greater than a thickness of the fourth gate insulating layer. 15. The method of claim 14,
The second gate insulating layer has a thickness in a range of 1 nm to 20 nm, and the fourth gate insulating layer has a thickness in a range of 1 nm to 10 nm. 10. The method of claim 9,
A line width of the first gate stack is equal to or greater than a line width of the second gate stack. 10. The method of claim 9,
In the off state, each of the first gate electrode, the second gate electrode, and the third gate electrode has an off voltage level, and in the turn-on operation period, the first gate electrode, the second gate electrode, and the third gate electrode have an off voltage level. A first turn-on voltage, a second turn-on voltage and a third turn-on voltage are applied, respectively,
The first turn-on voltage sweeps from the off-voltage level to a first voltage level lower than the off-voltage level, successively higher than the off-voltage level at the first voltage level, and having a polarity different from the first voltage level configured to sweep to a second voltage level,
and the second turn-on voltage and the third turn-on voltage are configured to sweep from the off voltage level to a third voltage level and a fourth voltage level higher than the off voltage level, respectively. 18. The method of claim 17,
The first turn-on voltage is turned off when the second turn-on voltage is swept from the off voltage level to the third voltage level and when the third turn-on voltage is swept from the off voltage level to the fourth voltage level. A switching element configured such that a time point of sweeping from a voltage level to the first voltage level is earlier. 19. The method of claim 18,
A time point at which the third turn-on voltage sweeps from the off voltage level to the fourth voltage level is the same as or faster than a time point at which the second turn-on voltage sweeps from the off voltage level to the third voltage level. switching element. 18. The method of claim 17,
The off voltage level includes a ground potential, the first voltage level has a negative polarity, and the second voltage level, the third voltage level, and the fourth voltage level have a positive polarity. a first gate stack formed on the substrate; and
a second gate stack formed on the substrate to be adjacent to the first gate stack;
The first gate stack includes a first gate insulating film sequentially stacked on the substrate, a second gate insulating film including a ferroelectric having a spontaneously induced negative capacitance, and a first gate electrode;
The second gate stack is a switching device including a memory layer including a charge trap layer sequentially stacked on the substrate and a second gate electrode. 22. The method of claim 21,
The second gate insulating layer is a switching device including a metal oxide having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, and a monoclinic system. 23. The method of claim 22,
The second gate insulating layer has a thickness in the range of 1 nm to 10 nm. 22. The method of claim 21,
The second gate stack is a switching device for changing a threshold voltage value within a predetermined range by injecting or removing the injected charge into the charge trap layer. 22. The method of claim 21,
the memory layer includes a tunnel insulating layer interposed between the substrate and the charge trap layer and a blocking layer interposed between the charge trap layer and the second gate electrode;
The tunnel insulating layer and the blocking layer include an oxide, and the charge trap layer includes a nitride. 22. The method of claim 21,
A line width of the first gate stack is equal to or greater than a line width of the second gate stack. a plurality of memory cells sharing a channel structure; and
and a first switching element connected to one side of the memory cells by sharing the channel structure;
The first switching element,
a first gate insulating film surrounding the channel structure;
a first gate electrode surrounding the first gate insulating layer;
a second gate insulating layer surrounding a portion of the first gate electrode and including a ferroelectric having a negative capacitance in response to a bias applied to the first gate electrode; and
A second gate electrode surrounding the second gate insulating film and having a flat plate shape
A semiconductor memory device comprising a. 28. The method of claim 27,
wherein the first gate electrode includes a first region interposed between the first gate insulating layer and the second gate insulating layer, and a second region extending from the first region and adjacent to the sidewall of the second gate electrode having a gap. semiconductor memory device. 29. The method of claim 28,
A second region of the first gate electrode is positioned between the second gate electrode and the memory cells. 28. The method of claim 27,
The second gate insulating layer includes a metal oxide having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, and a monoclinic system. 31. The method of claim 30,
The second gate insulating layer has a thickness in a range of 1 nm to 20 nm. 28. The method of claim 27,
The channel structure includes a core pillar, a capping layer formed on the core pillar, and a channel layer surrounding side surfaces of the capping layer and a bottom and side surfaces of the core pillar. 28. The method of claim 27,
Each of the plurality of memory cells includes a memory structure, wherein the memory structure surrounds the channel structure and includes a memory film in which a tunnel insulating film, a charge trap film and a blocking film are sequentially stacked, and a gate electrode having a flat plate shape surrounding the memory film. A semiconductor memory device comprising a. 28. The method of claim 27,
and a second switching element connected to the other side of the memory cells by sharing the channel structure, wherein the second switching element has the same configuration and shape as that of the first switching element, wherein the channel structure extends in the direction A semiconductor memory device in which the first switching element and the second switching element have mutually symmetrical shapes. 28. The method of claim 27,
Further comprising a second switching device connected to the other side of the memory cells by sharing the channel structure, wherein the second switching device includes a first gate structure and a second gate structure stacked apart from each other,
The first gate structure includes a third gate insulating layer surrounding the channel structure, a fourth gate insulating layer surrounding the third gate insulating layer and including a ferroelectric having a spontaneously induced negative capacitance, and a flat plate shape surrounding the fourth gate insulating layer. a third gate electrode;
The second gate structure includes a memory film including an electric hard wrap film surrounding the channel structure, and a fourth gate electrode having a flat plate shape surrounding the memory film.
A semiconductor memory device comprising a. 36. The method of claim 35,
The second gate structure is disposed between the first gate structure and the memory cells. 36. The method of claim 35,
The second gate structure injects charges into the charge trap layer or removes the injected charges to vary a threshold voltage value within a predetermined range. 28. The method of claim 27,
Further comprising a second switching device connected to the other side of the memory cells by sharing the channel structure, wherein the second switching device includes a first gate structure and at least one second gate structure stacked spaced apart from each other,
The first gate structure includes a third gate insulating layer surrounding the channel structure, a third gate electrode surrounding the third gate insulating layer, and a portion of the third gate electrode and a negative capacitance in response to a bias applied to the third gate electrode. a fourth gate insulating film including a ferroelectric having a
The second gate structure includes a fifth gate insulating layer surrounding the channel structure, a sixth gate insulating layer surrounding the fifth gate insulating layer and having a spontaneously induced negative capacitance, and a fifth gate electrode having a flat plate shape surrounding the sixth gate insulating layer.
A semiconductor memory device comprising a. 39. The method of claim 38,
wherein the third gate electrode includes a first region interposed between the third gate insulating layer and the fourth gate insulating layer, and a second region extending from the first region and having a gap adjacent to the sidewall of the fourth gate electrode. semiconductor memory device. 40. The method of claim 39,
The first gate structure is positioned between the second gate structure and the memory cells, and the second region of the third gate electrode is positioned between the fourth gate electrode and the memory cells. 39. The method of claim 38,
In a direction in which the channel structure extends, the first gate structure of the first switching element and the second switching element has a symmetrical shape. 39. The method of claim 38,
Each of the second gate insulating film, the fourth gate insulating film, and the sixth gate insulating film includes a metal oxide having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, and a monoclinic system, wherein the A thickness of the second gate insulating layer and a thickness of the fourth gate insulating layer are greater than a thickness of the sixth gate insulating layer. 28. The method of claim 27,
The first switching device includes a first gate structure and at least one or more second gate structures stacked spaced apart from each other, wherein the first gate structure is located between the memory cells and the second gate structure,
the first gate structure includes the first gate insulating layer, the first gate electrode, the second gate insulating layer, and the second gate electrode;
The second gate structure includes a third gate insulating layer surrounding the channel structure, a fourth gate insulating layer surrounding the third gate insulating layer and having a spontaneously induced negative capacitance, and a third gate electrode having a flat plate shape surrounding the fourth gate insulating layer.
A semiconductor memory device comprising a. 44. The method of claim 43,
and a second switching element connected to the other side of the memory cells by sharing the channel structure, wherein the second switching element includes the first gate structure and at least one or more of the second gate structures, wherein the first The number of the second gate structures in the switching element is equal to or greater than the number of the second gate structures in the second switching element. a plurality of memory cells sharing a channel structure; and
and a first switching device connected to one side of the memory cells by sharing the channel structure, wherein the first switching device includes a first gate structure and a second gate structure stacked apart from each other,
The first gate structure includes a first gate insulating layer surrounding the channel structure, a second gate insulating layer surrounding the first gate insulating layer and including a ferroelectric having a spontaneously induced negative capacitance, and a flat plate shape surrounding the second gate insulating layer. a first gate electrode;
The second gate structure includes a memory film that surrounds the channel structure and includes a charge trap film, and a second gate electrode that surrounds the memory film and has a flat plate shape.
A semiconductor memory device comprising a. 46. The method of claim 45,
and a second switching element connected to the other side of the memory cells by sharing the channel structure, wherein the second switching element has the same configuration and shape as that of the first switching element, wherein the channel structure extends in the direction A semiconductor memory device in which the first switching element and the second switching element have mutually symmetrical shapes. 46. The method of claim 45,
Each of the plurality of memory cells includes a memory structure, and the memory structure has the same configuration and shape as the second gate structure. 46. The method of claim 45,
The second gate structure is disposed between the first gate structure and the memory cells. 46. The method of claim 45,
The second gate insulating layer includes a metal oxide having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, and a monoclinic system. 50. The method of claim 49,
The second gate insulating layer has a thickness in a range of 1 nm to 10 nm. 46. The method of claim 45,
The second gate structure injects charges into the charge trap layer or removes the injected charges to vary a threshold voltage value within a predetermined range. forming a first laminate in which a first material film and a second material film are alternately stacked at least once on a substrate;
forming a first open part penetrating the first laminate;
forming a second gate insulating layer including a ferroelectric on a sidewall of the first open part;
forming the second material layer on the sidewall of the first open portion on which the second gate insulating layer is formed and on the first laminate;
sequentially forming a first gate insulating film and a channel film on sidewalls of the second material film in the first open part;
removing the second material layer; and
forming a first gate electrode interposed between the first gate insulating layer and the second gate insulating layer and a second gate electrode in contact with the second gate insulating layer by gap-filling a conductive material in the space where the second material layer is removed;
A method of manufacturing a semiconductor memory device comprising a. 23. The method of claim 22,
Before the step of sequentially forming a first gate insulating film and a channel film on the sidewall of the second material film in the first open part,
forming a second laminate in which the first material film and the second material film are alternately stacked a plurality of times on the first laminate;
forming a second open part through the second laminate to be connected to the first open part; and
forming a memory layer on a sidewall of the second open part
A method of manufacturing a semiconductor memory device further comprising a. 54. The method of claim 53,
In the step of sequentially forming a first gate insulating film and a channel film on a sidewall of the second material film in the first open portion, the first gate insulating film and the channel film are sequentially formed on the memory film of the second open portion. Device manufacturing method. 54. The method of claim 53,
In the step of forming a second laminate in which the first material film and the second material film are alternately stacked a plurality of times on the first laminate, the first insulating film is positioned on the lowermost and uppermost layers of the second laminate. However, the method of manufacturing a semiconductor memory device in which the first insulating layer positioned at the lowermost layer and the uppermost layer of the second stacked body is formed to have a relatively thick thickness. 54. The method of claim 53,
The method of manufacturing a semiconductor memory device, wherein the memory layer is formed as a single charge trap layer or a multilayer layer in which a charge trap layer and a blocking layer are stacked. 53. The method of claim 52,
The first gate electrode includes a first region positioned between the first gate insulating layer and the second gate insulating layer, and a second region extending from one end of the first region to face the sidewall of the first gate electrode with a gap. A method of manufacturing a semiconductor memory device comprising a. 53. The method of claim 52,
The second gate insulating layer includes a fluorite-structured metal oxide having at least one stable composition region selected from among cubic, tetragonal, or monoclinic having a negative capacitance in response to a bias applied to the first gate electrode. A method of manufacturing a semiconductor memory device. 59. The method of claim 58,
The method of manufacturing a semiconductor memory device, wherein the second gate insulating layer is formed to have a thickness in a range of 1 nm to 20 nm. 59. The method of claim 58,
The step of forming the second gate insulating film,
forming the second gate insulating layer at a temperature in the range of 180°C to 300°C using an atomic layer deposition method; and
A method of manufacturing a semiconductor memory device, comprising the step of performing an annealing process in an oxygen atmosphere and a temperature in the range of 400 °C to 900 °C. forming a first laminate in which a first material film and a second material film are alternately stacked at least once on a substrate;
forming a first open part penetrating the first laminate;
forming a second gate insulating layer including a ferroelectric along a surface of the first open part;
forming a second laminate in which the first material film and the second material film are alternately stacked a plurality of times on the first laminate;
forming a second open part through the second laminate to be connected to the first open part;
forming a memory layer on a sidewall of the second open part;
sequentially forming a first gate insulating film and a channel film along surfaces of the first open portion and the second open portion;
removing the second material layer; and
forming a gate electrode in contact with the second gate insulating film and a control gate in contact with the memory film by gap-filling a conductive material in the space from which the second material film is removed;
A semiconductor device manufacturing method comprising a. 62. The method of claim 61,
and the second gate insulating layer includes a metal oxide having a fluorite structure having at least one stable composition region selected from a cubic system, a tetragonal system, and a monoclinic system having a spontaneously induced negative capacitance. 63. The method of claim 62,
The method of manufacturing a semiconductor memory device, wherein the second gate insulating layer is formed to have a thickness in a range of 1 nm to 10 nm. 63. The method of claim 62,
The step of forming the second gate insulating film,
forming the second gate insulating layer at a temperature in the range of 180°C to 300°C using an atomic layer deposition method; and
A method of manufacturing a semiconductor memory device, comprising the step of performing an annealing process in an oxygen atmosphere and a temperature in the range of 400 °C to 900 °C.

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