KR20150066512A - Nonvolatile charge trap memory device having a deuterated layer in a multy-layer charge-trapping region - Google Patents

Abstract

The present invention relates to scaling a charge trap memory device and to articles produced thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region for electrically connecting the source and drain. A tunnel dielectric layer is disposed over the substrate over the channel region, and a multilayer charge-trapping region is disposed over the tunnel dielectric layer. The multilayer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer, and a second nitride layer disposed on the first nitride layer .

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a non-volatile charge trap memory device having a deuterated layer in a multilayer charge-trapping region,

Cross-references to related applications

This application claims the benefit of US Provisional Patent Application Serial No. 60 / 931,905, filed on May 25, 2007, which claims the benefit of 35 USC 119 (e) And U.S. Serial No. 11 / 904,475, both of which are incorporated herein by reference.

The present invention relates to the field of semiconductor devices.

For decades past, the scaling of features of integrated circuits has been a driving force behind the ever-growing semiconductor industry. Scaling for smaller and smaller features enables functional units of increased density on a limited real estate of semiconductor chips. For example, reducing transistor size allows integration of an increased number of memory devices on a chip, making them suitable for manufacturing products with increased capacity. However, drives for much larger capacities are not without problems. The need to optimize the performance of individual devices is becoming increasingly important.

Non-volatile semiconductor memories typically use stacked floating gate type field-effect transistors. In these transistors, electrons are injected into the floating gate of the memory cell to be programmed by grounding the body region of the substrate on which the memory cell is formed and biasing the control gate. The oxide-nitride-oxide (ONO) stack may be used as a charge storage layer as in a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) transistor or as a split gate flash transistor, And is used as an isolation layer between the control gates. Figure 1 illustrates a cross-sectional view of a conventional non-volatile charge trap memory device.

Referring to FIG. 1, a semiconductor device 100 includes a SONOS gate stack 104 that includes a conventional ONO portion 106 formed on a silicon substrate 102. The semiconductor device 100 further includes source and drain regions 110 on either side of the SONOS gate stack 104 to define the channel region 112. The SONOS gate stack & The SONOS gate stack 104 includes a polysilicon gate layer 108 formed on and in contact with the ONO portion 106. The ONO portion 106 is formed of a polysilicon gate layer 108, The polysilicon gate layer 108 is electrically isolated from the silicon substrate 102 by the ONO portion 106. The ONO portion 106 typically includes a top oxide layer 106C overlying a tunnel oxide layer 106A, a nitride or oxynitride charge-trapping layer 106B, and a nitride or oxynitride layer 106B.

One problem with conventional SONOS transistors is the poor data retention of the nitride or oxynitride layer 106B because of the leakage current through this layer, And the use of the semiconductor device (100). One attempt to address this problem has focused on the use of silicon-rich SONOS layers, which allows a large initial isolation between the program voltage and the erase voltage at the start of life, but the rapid deterioration of charge storage capability . Other attempts focused on the oxygen-rich layers, which enabled a reduced rate of deterioration of the charge storage capability, but also reduced the initial separation between the program voltage and the erase voltage. The effects of both approaches to these data retention over time can be graphically illustrated. Figures 2 and 3 are plots of the threshold voltage (V) as a function of retention time (Sec) for conventional non-volatile charge trap memory devices.

2, the rapid deterioration of the charge storage capability for the silicon-rich layer is caused by the convergence of the programming threshold voltage (VTP) 202 and the erase threshold voltage (VTE) 204 to a certain minimum value 206 Is displayed. Referring to FIG. 3, a reduced separation between the VTP 302 and the VTE 304 is obtained for the oxygen-rich layer. As indicated by line 306, the overall useful lifetime of the device is not prominently extended by this approach.

Embodiments of the invention are illustrated by way of example and not of limitation in the figures of the accompanying drawings:
Figure 1 illustrates a cross-sectional view of a conventional non-volatile charge trap memory device.
Figure 2 is a plot of threshold voltage (V) as a function of retention time (Sec) for a conventional non-volatile charge trap memory device.
Figure 3 is a plot of threshold voltage (V) as a function of hold time (Sec) for a conventional non-volatile charge trap memory device.
4 illustrates a cross-sectional view of a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
Figure 5 illustrates a cross-sectional view of a non-volatile charge trap memory device according to an embodiment of the invention.
6A illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
Figure 6B illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
6C illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
6D illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
6E illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
6F illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
Figure 6G illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
6H illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
Figure 6i illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
Figure 7A illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
7B illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
Figure 7C illustrates a cross-sectional view illustrating the steps of forming a non-volatile charge trap memory device in accordance with an embodiment of the present invention.
8A illustrates a cross-sectional view of a non-volatile charge trap memory device including an ONNO stack.
8B illustrates a cross-sectional view of a non-volatile charge trap memory device including an ONNO stack.
Figure 9 shows a flow diagram illustrating a series of operations of a method for fabricating a non-volatile charge trap memory device including a split multi-layer charge-trapping region.
Figure 10A illustrates a non-planar multigate device including a fission charge-trapping region.
Figure 10B illustrates a cross-sectional view of the non-planar multi-gate device of Figure 10A.
11A and 11B illustrate a non-planar multigate device including a fission charge-trapping region and a horizontal nanowire channel.
Figure 11C illustrates a cross-sectional view of the vertical string of the non-planar multi-gate devices of Figure 11A.
12A and 12B illustrate a non-planar multi-gate device including a fission charge-trapping region and a vertical nanowire channel.

A non-volatile charge trap memory device and a method of forming the non-volatile charge trap memory device are described herein. In the following description, numerous specific details are set forth such as specific dimensions in order to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well known processing steps such as patterning steps or wet chemical cleanings are not described in detail in order not to unnecessarily obscure the present invention. Moreover, it is to be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

Nonvolatile charge trap memory devices are disclosed herein. The device may include a substrate having a channel region, and a pair of source and drain regions. A gate stack may be formed on the substrate above the channel region and between a pair of source and drain regions. In one embodiment, the gate stack includes a multilayer charge-trapping region having a first deuterated layer. The multilayer charge-trapping region may further include a deuterium-free charge-trapping layer. Alternatively, the multilayer charge-trapping region may comprise a partially deuterated charge-trapping layer having a deuterium concentration below the deuterium concentration of the first deuterated layer.

A non-volatile charge trap memory device comprising a multi-layer charge-trapping region having a deuterated layer may exhibit improved programming and erase rates and data retention. According to an embodiment of the present invention, a deuterated layer is formed between the charge-trapping layer of the multilayer charge-trapping region and the tunnel dielectric layer. In one embodiment, the deuterated layer is essentially trap-free and relieves hot electron degradation during erase and program cycles. By including a trap-free layer between the tunnel dielectric layer and the charge-trapping layer of the multilayer charge-trapping region, the Vt shift from erase and program cycles can be reduced, . According to another embodiment of the present invention, a second deuterated layer is also formed between the charge-trapping layer of the multilayer charge-trapping region and the top dielectric layer of the gate stack.

A non-volatile charge trap memory device may include a multi-layer charge-trapping region having a deuterium layer. 4 illustrates a cross-sectional view of a non-volatile charge trap memory device in accordance with an embodiment of the present invention.

Referring to FIG. 4, a semiconductor device 400 includes a gate stack 404 formed over a substrate 402. The semiconductor device 400 further includes source and drain regions 410 on a substrate 402 on either side of the gate stack 404 to provide a channel region 412). The gate stack 404 includes a tunnel dielectric layer 404A, a multilayer charge-trapping region 404B, a top dielectric layer 404C, and a gate layer 404D. Thus, the gate layer 404D is electrically insulated from the substrate 402. The multilayer charge-trapping region 404B includes a deuterated layer 406 between the charge-trapping layer 408 of the multilayer charge-trapping region 404B and the tunnel dielectric layer 404A. A pair of dielectric spacers 414 isolate the sidewalls of the gate stack 404.

Semiconductor device 400 may be any non-volatile charge trap memory device. In one embodiment, the semiconductor device 400 is a flash-type device in which the charge-trapping layer is a conductor layer or a semiconductor layer. According to another embodiment of the present invention, the semiconductor device 400 is a SONOS-type device in which the charge-trapping layer is an insulator layer. Typically, SONOS refers to "Semiconductor-Oxide-Nitride-Oxide-Semiconductor ", where the first" Semiconductor " Quot; Oxide "refers to the tunnel dielectric layer," Nitride "refers to the charge-trapping dielectric layer, the second refers to the top dielectric layer (also known as blocking dielectric layer) , And the second "Semiconductor" represents the gate layer. However, SONOS-type devices are not limited to these specific materials, as described below.

Substrate 402 and eventually channel region 412 may be comprised of any material suitable for semiconductor device fabrication. In one embodiment, the substrate 402 is a bulk substrate comprised of a single crystal of material that may include, but is not limited to, silicon, germanium, silicon-germanium or III-V compound semiconductor materials. In another embodiment, the substrate 402 includes a bulk layer having a top epitaxial layer. In certain embodiments, the bulk layer is comprised of a single crystal of a material that may include silicon, germanium, silicon-germanium, III-V compound semiconductor materials and quartz (but not limited to) The epitaxial layer consists of a single crystalline layer that may include, but is not limited to, silicon, germanium, silicon-germanium and III-V compound semiconductor materials. In another embodiment, the substrate 402 includes an uppermost epitaxial layer on the intermediate insulator layer overlying the lower bulk layer. The top epitaxial layer may comprise silicon (i. E., To form a silicon-on-insulator) semiconductor substrate, germanium, silicon-germanium and III-V compound semiconductor materials A single crystal layer. The insulator layer is comprised of a material that may include (but is not limited to) silicon dioxide, silicon nitride, and silicon oxynitride. The lower bulk layer consists of a single crystal that can include silicon, germanium, silicon-germanium, III-V compound semiconductor materials and quartz, but not limited to these. The substrate 402 and eventually the channel region 412 may contain dopant impurity atoms. In a particular embodiment, the channel region 412 is P-type doped, and in an alternative embodiment, the channel region 412 is N-type doped.

The source and drain regions 410 of the substrate 402 may be any regions having conductivity opposite the channel region 412. For example, according to an embodiment of the present invention, the source and drain regions 410 are N-type doped regions while the channel region 412 is a P-type doped region. In one embodiment, the substrate 402 and eventually the channel region 412 is comprised of boron-doped single-crystal silicon with a boron concentration in the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ atoms / cm ³ . The source and drain regions 410 are comprised of phosphorous-doped or arsenic-doped regions having a concentration of N-type dopants in the range of 5 × 10 ¹⁶ to 5 × 10 ¹⁹ atoms / cm ³ . In certain embodiments, the source and drain regions 410 have a depth in the range of 80 to 200 nanometers at the substrate 402. According to an alternative embodiment of the present invention, the source and drain regions 410 are P-type doped regions, while the channel region 412 is an N-type doped region.

The tunnel dielectric layer 404A can be made of any material and is capable of tunneling to the charge-trapping layer under the applied gate bias, while maintaining a suitable barrier for leakage when the device is unbiased. To a thickness of about < RTI ID = 0.0 > In one embodiment, the tunnel dielectric layer 404A is formed by a thermal oxidation process and consists of silicon dioxide or silicon oxynitride, or a combination thereof. In another embodiment, the tunnel dielectric layer 404A is formed by chemical vapor deposition or atomic layer deposition and is formed of a material selected from the group consisting of silicon nitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide and lanthanum oxide But not limited to, a dielectric layer. In certain embodiments, the tunnel dielectric layer 404A has a thickness in the range of 1 to 10 nanometers. In certain embodiments, the tunnel dielectric layer 404A has a thickness of approximately 2 nanometers.

The multilayer charge-trapping region 404B may be of any material and may have any thickness suitable for storing charge and ultimately raising the threshold voltage of the gate stack 404. In one embodiment, the multilayer charge-trapping region 404B is formed by a chemical vapor deposition process and includes, but is not limited to, stoichiometric silicon nitride, silicon-rich silicon nitride, and silicon oxynitride A dielectric material. According to an embodiment of the present invention, the multilayer charge-trapping region 404B includes a deuterated layer 406 between the tunnel dielectric layer 404A and the charge trapping layer 408, as shown in FIG. do. Deuterated layer 406 and charge-trapping layer 408 can each be made of a deuterated derivative and a non-deuterated derivative of the same material. For example, in accordance with an embodiment of the present invention, the deuterated layer 406 is a deuterated derivative of silicon oxynitride, while the charge-trapping layer 408 is a hydrogenated derivative of silicon oxynitride, . In one embodiment, the total thickness of the multilayer charge-trapping region 404B is in the range of 5 to 10 nanometers. In a particular embodiment, deuterated layer 406: the ratio of the respective thicknesses of the charge-trapping layer 408 is approximately 1: 1.

The multilayer charge-trapping region 404B may have an abrupt interface between the deuterium layer 406 and the charge-trapping layer 408. That is, according to an embodiment of the present invention, the charge-trapping layer 408 is deuterium-free. Alternatively, a gradient of deuterium atom concentration ranging in range from the high deuterium concentration of the deuterated layer 406 to the low deuterium concentration of the charge-trapping layer 408 may be formed. Thus, according to an alternative embodiment of the present invention, the charge-trapping layer 408 is a partially deuterated layer, but has a deuterium concentration below the deuterium concentration of the deuterated layer 406.

The top dielectric layer 404C may be of any material and may have any thickness suitable for maintaining a barrier to charge leakage without significantly reducing the capacitance of the gate stack 404. In one embodiment, the top dielectric layer 404C is formed by a chemical vapor deposition process and consists of silicon dioxide, silicon oxynitride, silicon nitride, or a combination thereof. In another embodiment, the top dielectric layer 404C is formed by atomic layer deposition and includes hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, and lanthanum oxide (High-k) dielectric layer. In certain embodiments, the top dielectric layer 404C has a thickness in the range of 1 to 20 nanometers.

The gate layer 404D may be comprised of any conductive or semiconductive material suitable for receiving a bias during operation of the SONOS-type transistor. According to an embodiment of the present invention, the gate layer 404D is formed by a chemical vapor deposition process and consists of doped polycrystalline silicon. In another embodiment, the gate layer 404D is formed by physical vapor deposition and comprises metal nitride, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel (But not limited to) a metal-containing material.

A non-volatile charge trap memory device may include a multilayer charge-trapping region having more than one deuterated layer. Figure 5 illustrates a cross-sectional view of a non-volatile charge trap memory device according to an embodiment of the invention.

Referring to FIG. 5, a semiconductor device 500 includes a gate stack 504 formed over a substrate 502. The semiconductor device 500 further includes source and drain regions 510 on a substrate 502 on either side of the gate stack 504 such that the substrate 502 under the gate stack 504 has channel regions 512). The gate stack 504 includes a tunnel dielectric layer 504A, a multilayer charge-trapping region 504B, a top dielectric layer 504C, and a gate layer 504D. Thus, the gate layer 504D is electrically isolated from the substrate 502. The multilayer charge-trapping region 504B includes a first deuterated layer 506 sandwiching the charge-trapping layer 508 of the multilayer charge-trapping region 504B and a second deuterated layer 506 sandwiching the charge- (516). A pair of dielectric spacers 514 isolate the sidewalls of the gate stack 504.

The semiconductor device 500 may be any semiconductor device described in connection with the semiconductor device 400 from Fig. The substrate 502, the source and drain regions 510, and the channel region 512 are each associated with the substrate 402, source and drain regions 410, and channel region 412 from FIG. 4 Any material described and dopant impurity atoms. The tunnel dielectric layer 504A, the top dielectric layer 504C and the gate layer 504D may be formed of any of the tunnel dielectric layer 404A, the top dielectric layer 404C and the gate layer 404D, . ≪ / RTI >

However, in contrast to the semiconductor device 400, the semiconductor device includes a multilayer charge-trapping region 504B having a second deuterated layer 516 over the charge-trapping layer 508, . The first deuterated layer 506 and the charge-trapping layer 508 can be made of any of the materials described with respect to deuterated layer 406 and charge-trapping layer 408 from Figure 4, respectively . In addition, the second deuterated layer 516 may also be comprised of any of the materials described in connection with the deuterated layer 406 from FIG. However, according to an embodiment of the present invention, the total thickness of the multilayer charge-trapping region 504B is in the range of 5 to 10 nanometers, i.e., the multilayer charge-trapping region 504B is a multilayer charge- - < / RTI > the same extent as the trapping zone 404B. Thus, the relative ratios of the thicknesses of the deuterated layers to the charge-trapping layer may differ from the relative ratios of the semiconductor device 400. For example, in one embodiment, the ratio of the respective thicknesses of the first deuterated layer 506: charge-trapping layer 508: second deuterated layer 516 is approximately 1: 2: 1.

Like the multilayer charge-trapping region 404B from Figure 4, the multilayer charge-trapping region 504B has an abrupt interface between the first deuterated layer 506 and the charge-trapping layer 508 . Likewise, it may be present between the second deuterated layer 516 and the charge-trapping layer 508 as a second abrupt interface. That is, according to an embodiment of the present invention, the charge-trapping layer 508 is free of deuterium. Alternatively, gradients of deuterium atom concentrations ranging from high deuterium concentrations in the first and second deuterated layers 506 and 516 to low deuterium concentrations in the charge-trapping layer 508 may be formed. Thus, according to an alternative embodiment of the present invention, the charge-trapping layer 508 is a partially deuterated layer, but has a deuterium concentration less than the deuterium concentration of the deuterated layers 506 and 516.

A non-volatile charge trap memory device may be fabricated to include a multilayer charge-trapping region having a deuterium layer. 6A-6I illustrate cross-sectional views illustrating steps in the formation of a non-volatile charge trap memory device in accordance with an embodiment of the present invention.

6A, a substrate 602 is provided. The substrate 602 may comprise any of the materials described above with respect to the substrates 402 and 502 from FIGS. 4 and 5, respectively, and may have any of the features described above.

Referring to FIG. 6B, a tunnel dielectric layer 620 is formed on the top surface of the substrate 602. The tunnel dielectric layer 620 may be formed of any material and any process described with reference to the tunnel dielectric layers 404A and 504A from Figures 4 and 5 and may have any of the thicknesses described above .

Referring to FIG. 6C, a multilayer charge-trapping region 622 is formed on the top surface of the tunnel dielectric layer 620. According to an embodiment of the present invention, the multilayer charge-trapping region 622 includes a deuterated layer 624 between the tunnel dielectric layer 620 and the charge-trapping layer 626, as shown in Figure 6C. . The deuterated layer 624 and the charge-trapping layer 626 are comprised of any of the materials described respectively with respect to deuterated layer 406 and charge-trapping layer 408 from Figure 4, Each having any of the thicknesses described. The multilayer charge-trapping region 622 and ultimately the deuterated layer 624 and the charge-trapping layer 626 are formed by any process suitable to provide a substantially uniform coverage over the tunnel dielectric layer 620 . According to an embodiment of the present invention, the multilayer charge-trapping region 622 is formed by a chemical vapor deposition process. In one embodiment, the deuterated layer 624 is first formed using deuterated formation gases, and then the charge-trapping layer 626 is then formed using deuterated formation gases, Gas is formed using non-deuterated formation gases. In a particular embodiment, the multilayer charge-trapping region 622 is comprised substantially of silicon oxynitride, and the deuterated layer 624 is first deuterated silane (SiD ₄ ), deuterated Such as but not limited to deuterated dichlorosilane (SiD ₂ Ch), nitrous oxide (N ₂ O), deuterated ammonia (ND ₃ ) and oxygen (O ₂ ) ) Forming gases. Subsequently, the charge-trapping layer 626 is replaced with a non-deuterated-bis (tert-butylamino) silane (non-deuterated-bis (TBBAS) BTBAS), and the silane embodiment, the deuterated layer 624 and the charge-trapping layer 626 are formed using the same process steps, That is, they are formed in the same process chamber with seamless transitions from deuterated formation gases to deuterated deuterated gases.

Abrupt deuterated and non-deuterated junctions may be present at the interface of the deuterated layer 624 and the charge-trapping layer 626. Thus, according to an embodiment of the present invention, the charge-trapping layer 626 is maintained deuterium free. Alternatively, some of the deuterium present in the deuterated layer 624 may be transferred to the charge-trapping layer 626 during deposition of the charge-trapping layer 626 or during subsequent high temperature process steps . That is, a gradient of the deuterium atom concentration that ranges from the high deuterium concentration of the deuterated layer 624 to the low deuterium concentration of the charge-trapping layer 626 can be formed. Thus, according to an alternative embodiment of the present invention, the charge trapping layer 626 is a partially deuterated layer, but has a deuterium concentration below the deuterium concentration of the deuterated layer 624. In certain embodiments, the deuterated formation gases are used to form a partially deuterated charge-trapping layer 626 having a deuterium concentration that is less than the deuterium concentration of deuterated layer 624.

6D, a top dielectric layer 628 is formed on the top surface of the multilayer charge-trapping region 622. The top dielectric layer 628 may be formed of any material and any process described in connection with the top dielectric layers 404C and 504C from Figures 4 and 5 and may have any of the thicknesses described above . According to an alternative embodiment of the present invention, top dielectric layer 628 is formed by using deuterated source gases. In this embodiment, the deuterated superficial dielectric layer 628 is then depleted of the source of deuterium to form a trap-free layer in the multilayer charge-trapping region 622 during a subsequent anneal process. Lt; / RTI > In a particular alternative embodiment, the deuterated superficial dielectric layer 628 is formed using formation gases such as, but not limited to, SiD ₄ , SiD ₂ Cl _2, and N ₂ O.

Referring to FIG. 6E, a gate layer 630 is formed on the top surface of the top dielectric layer 628. The gate layer 630 may be formed of any material and any process described in connection with the gate layers 404D and 504D from Figures 4 and 5, respectively. Thus, a gate stack 632 may be formed over the substrate 602. [

Referring to FIG. 6F, a gate stack 632 is patterned to form a patterned gate stack 604 over the substrate 602. The patterned gate stack 604 includes a patterned tunnel dielectric layer 604A, a patterned multilayer charge-trapping region 604B, a patterned top dielectric layer 604C, and a patterned gate layer 604D. The patterned multilayer charge-trapping area 604B includes a patterned deuterated layer 606 and a patterned charge-trapping layer 608. The gate stack 632 is formed by any process suitable to provide substantially vertical sidewalls for the gate stack 604 with high selectivity to the substrate 602 to form a patterned gate stack 604 Can be patterned. According to an embodiment of the present invention, the gate stack 632 is patterned to form a patterned gate stack 604 by a lithography and etching process. In a particular embodiment, the etch process is performed on a substrate such as, but not limited to, carbon tetrafluoride (CF ₄ ), O ₂ , hydrogen bromide (HBr) and chlorine (Cl ₂ ) Is an anisotropic etch process utilizing gases.

6G, dopant impurity atoms 640 are implanted into the exposed portions of the substrate 604 to form source and drain tip extension regions 650. [ May be desirable. Source and drain tip extension regions 650 will ultimately be part of the source and drain regions formed later, as described below. Thus, by forming the source and drain tip extension regions 650 as defined by the locations of the patterned gate stack 604, the channel region 612 can be defined as shown in FIG. 6G. In one embodiment, the concentration and conductivity types of dopant impurity atoms used to form the source and drain tip extension regions 650 are substantially the same as those used to form the source and drain regions described below Do.

Referring to FIG. 6H, it may be desirable to form a pair of dielectric spacers 614 on the sidewalls of the patterned gate stack 604. 6i, source and drain regions 610 are formed by implanting dopant impurity atoms 660 in the exposed portions of the substrate 604. As shown in FIG. Source and drain regions 610 may have any of the features, such as those described with respect to source and drain regions 410 and 510 from FIGS. 4 and 5, respectively. In accordance with an embodiment of the present invention, the profile of the source and drain regions 610 may include dielectric spacers 614, a patterned gate stack 604, and source and drain tip extension regions 610, (650).

A non-volatile charge trap memory device may be fabricated to include a multilayer charge-trapping region having more than one deuterated layer. Figures 7A-7C illustrate cross-sectional views illustrating steps in the formation of a non-volatile charge trap memory device in accordance with an embodiment of the present invention.

Referring to FIG. 7A, a tunnel dielectric layer 720 formed on the top surface of the substrate 702 is provided. Substrate 702 may comprise any of the materials described above with respect to substrates 402 and 502 from FIGS. 4 and 5, respectively, and may have any of the features described above. The tunnel dielectric layer 720 may be formed of any material and any process described with reference to the tunnel dielectric layers 404A and 504A from Figures 4 and 5 and may have any of the thicknesses described above .

Referring to FIG. 7B, a multilayer charge-trapping region 722 is formed on the top surface of the tunnel dielectric layer 720. According to an embodiment of the present invention, the multilayer charge-trapping region 722 includes a first deuterated layer 724 between the tunnel dielectric layer 720 and the charge-trapping layer 726. In addition, the multilayer charge-trapping region 722 includes a second deuterated layer 727 on the top surface of the charge-trapping layer 726, as shown in FIG. 7B. The first deuterated layer 724, the charge-trapping layer 726 and the second deuterated layer 727 are formed from the first deuterated layer 506, the charge-trapping layer 508, , And second deuterated layer 516, and may have any of the thicknesses described above. The multilayer charge-trapping regions 722 and eventually the first and second deuterated layers 724 and 727 and the charge-trapping layer 726 provide substantially uniform coverage over the tunnel dielectric layer 720 May be formed by any suitable process. According to an embodiment of the present invention, the multilayer charge-trapping region 722 is formed by a chemical vapor deposition process. In one embodiment, the first deuterated layer 724 is first formed using deuterated material gases, and the charge-trapping layer 726 is then formed using de-deuterated formation gases And finally, a second deuterated layer 727 is formed using deuterated hydrogenation gases. In a particular embodiment, the multilayer charge-trapping region 722 is comprised substantially of silicon oxynitride, and the first deuterated layer 724 is first formed of SiD ₄ , SiD ₂ Cl ₂ , N ₂ O, ND ₃ , (But not limited to) O ₂ . Subsequently, the charge-trapping layer 726 may be doped with forming gases such as, but not limited to, deuterated non-deuterated BTBAS, SiH ₄ , SiH ₂ Cl ₂ , N ₂ O, NH ₃ and O ₂ . Finally, a second deuterated layer 727 is formed using formation gases such as, but not limited to, SiD ₄ , SiD ₂ Cl ₂ , N ₂ O, ND _3, and O ₂ . In a particular embodiment, the first deuterated layer 724, the charge-trapping layer 726 and the second deuterated layer 727 are formed in the same process step, i.e., from deuterated formation gases to deuterated Is formed in the same process chamber with a seamless transition to formation gases and back to deuterated formation gases.

Abrupt deuterated and deuterated connections may be present at the interfaces of the first deuterated layer 724, the second deuterated layer 727 and the charge-trapping layer 726. Thus, according to an embodiment of the present invention, the charge-trapping layer 726 is maintained deuterium free. Alternatively, some of the deuterium present in the first and second deuterated layers 724 and 727 may be removed during deposition of the charge-trapping layer 726 and the second deuterated layer 727, May be moved to the charge-trapping layer 726 during the steps. That is, a gradient of deuterium atom concentration ranging in range from the high deuterium concentration of the first and second deuterated layers 724 and 727 to the low deuterium concentration of the charge-trapping layer 726 can be formed. Thus, according to an alternative embodiment of the present invention, the charge trapping layer 726 is a partially deuterated layer, but has a deuterium concentration below the deuterium concentration of the first and second deuterated layers 724. In certain embodiments, the deuterated formation gases are used to form a partially deuterated charge-trapping layer 726 having a deuterium concentration that is less than the deuterium concentration of deuterated layer 724.

Referring to FIG. 7C, process steps similar to the process steps described in connection with FIGS. 6D-6I are performed to form a non-volatile charge trap memory device having more than one dielectric layer. Thus, a patterned gate stack 704 is formed over the substrate 702. Source and drain regions 710 are formed on either side of the patterned gate stack 704 to define a channel region 712. The patterned gate stack 704 includes a patterned tunnel dielectric layer 704A, a patterned multilayer charge-trapping region 704B, a patterned top dielectric layer 704C, and a patterned gate layer 704D. The patterned multilayer charge-trapping region 704B includes a patterned first deuterated layer 706 and a patterned second deuterated layer 716 sandwiching the patterned charge-trapping layer 708 .

Implementations and alternatives

In one aspect, the present disclosure is directed to a charge trap memory device comprising a fission multi-layer charge-trapping region having two or more nitride-containing layers and one or more deuterated layers. 8A is a block diagram illustrating a side cross-sectional view of one such embodiment.

8A, a memory device 800 includes a gate stack 804 having a fissile multilayer charge-trapping region 804 formed on a surface 806 of a silicon substrate 808 or on a surface of a silicon layer formed on a substrate 802). In general, the device 800 further includes one or more diffusion regions 810, such as source and drain regions or structures, aligned with the gate stack 802 and separated by a channel region 812 .

In addition to the multilayer charge-trapping region 804, the gate stack 802 is formed by separating the gate stack from the channel region 812, the top or blocking dielectric layer 816, and the gate layer 818, Lt; RTI ID = 0.0 > 814 < / RTI >

The multilayer charge-trapping zone 804 generally comprises at least two layers with different compositions of silicon, oxygen and nitrogen. In one embodiment, the multilayer charge-trapping region comprises a first nitride layer 820 comprising substantially trap-free, silicon-rich, oxygen-rich nitride, And a second nitride layer 822 that includes a dense silicon rich nitrogen-rich and trap-dense, silicon-rich, nitrogen-rich, and oxygen-lean nitride. It has been found that the silicon-rich oxygen-rich first nitride layer 820 reduces the charge loss rate after programming and after erasing, which is evident at small voltage shifts in the retention mode. The silicon-rich nitrogen-rich and oxygen-lean second nitride layer 816 can be used to reduce the program voltage < RTI ID = 0.0 > and / or < / RTI & Erase voltages and speeds, thereby prolonging the device ' s operational lifetime.

In addition to the first and second nitride layers 820, 822, the multilayer charge-trapping region 804 further includes one or more deuterated layers. In the illustrated embodiment, the multilayer charge-trapping region 804 includes a first deuterated layer 824 that separates the first nitride layer 820 from the tunnel dielectric layer 814 and a second deuterated layer 824 that separates the second nitride layer 822 Lt; RTI ID = 0.0 > 816 < / RTI > The first and second deuterated layers 824 and 826 may be made of a deuterated derivative of the same material used to form the first and second nitride layers 820 and 822. For example, in embodiments where the first and second nitride layers 820 and 822 comprise silicon nitride and / or silicon oxynitride, the first and second deuterated layers 824 and 826 may be formed of silicon oxynitride Or a deuterated derivative.

In one embodiment, the total thickness of the multilayer charge-trapping region 804 is in the range of 5 to 10 nanometers, and the thicknesses of the individual deuterated layers and nitride layers are approximately the same.

The multilayer charge-trapping region 804 may have an abrupt interface between the first deuterated layer 824 and the first nitride layer 820. According to one embodiment, this is the first nitride layer 820. Alternatively, gradients of deuterium atom concentration ranging from a high deuterium concentration in the first deuterated layer 824 to a low deuterium concentration in the first nitride layer 820 may be formed. Thus, according to an alternative embodiment, the first nitride layer 820 is a partially deuterated layer, but has a deuterium concentration below the deuterium concentration of the first deuterated layer 824.

Substrate 808 and eventually channel region 812 may be made of any material suitable for semiconductor device fabrication. In one embodiment, the substrate 808 is a bulk substrate comprised of a material that may include (but is not limited to) silicon, germanium, silicon-germanium or III-V compound semiconductor materials. In another embodiment, the substrate 808 may be a bulk substrate having a top epitaxial layer of a material that may include silicon, germanium, silicon-germanium, III-V compound semiconductor materials and quartz, And a memory device 800 is fabricated thereon and thereon. The substrate 808 and eventually the channel region 812 may contain dopant impurity atoms. In a particular embodiment, the channel region 812 comprises polycrystalline silicon or polysilicon and is P-type doped, or alternatively N-type doped in an alternative embodiment. In another particular embodiment, the channel region 812 comprises recrystallized polysilicon and is P-type or N-type doped.

The source and drain regions 810 of the substrate 808 may be any regions having conductivity opposite the channel region 812. For example, in one embodiment, the source and drain regions 810 are N-type doped regions, while the channel region 812 is a P-type doped region. In one version of this embodiment, the substrate 808 and eventually the channel region 812 is comprised of boron-doped silicon with a boron concentration in the range of 1 x 10 ¹⁵ to 1 x 10 ¹⁹ atoms / cm ³ . Source and drain regions 810 are comprised of phosphorus-doped or arsenic-doped regions having a concentration of N-type dopants ranging from 5 x 10 ¹⁶ to 5 x 10 ¹⁹ atoms / cm ³ . In certain embodiments, the source and drain regions 810 have a depth in the range of 80 to 200 nanometers at the substrate 808. [ In an alternative embodiment, the source and drain regions 810 are P-type doped regions, while the channel region 812 is an N-type doped region.

The tunnel dielectric layer 814 may be made of any material and may be formed of any material that allows the charge carriers to migrate under the applied gate bias to the multilayer charge-trapping region 814, while maintaining a suitable barrier to leakage when the memory device 800 is un- Lt; RTI ID = 0.0 > 804 < / RTI > In one embodiment, the tunnel dielectric layer 814 is formed by a thermal oxidation process and consists of silicon dioxide or silicon oxynitride, or a combination thereof. In another embodiment, the tunnel dielectric layer 814 is formed by chemical vapor deposition or atomic layer deposition, and may be formed from silicon nitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, and lanthanum oxide But not limited to, a dielectric layer. In certain embodiments, the tunnel dielectric layer 814 has a thickness in the range of 1 to 10 nanometers. In certain embodiments, the tunnel dielectric layer 814 has a thickness of approximately 2 nanometers.

The blocking dielectric layer 816 may be of any material and may have any thickness suitable for maintaining a barrier to charge leakage without significantly reducing the capacitance of the gate stack 802. [ In one embodiment, the blocking dielectric layer 816 is formed by a chemical vapor deposition process and consists of silicon dioxide, silicon oxynitride, silicon nitride, or a combination thereof. In another embodiment, the blocking dielectric layer 816 is formed by atomic layer deposition and includes, but is not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, and lanthanum oxide. And a high-k dielectric layer. In certain embodiments, the blocking dielectric layer 816 has a thickness in the range of 1 to 20 nanometers.

The gate layer 818 may comprise any conductive or semiconductive material suitable for receiving a bias during operation of a SONOS-type transistor comprising doped polysilicon and a metal-containing material. In certain embodiments, the gate layer 818 has a thickness in the range of 1 to 20 nanometers.

8B, the multilayer charge-trapping region 804 includes an intermediate oxide comprising an oxide separating the first nitride layer 820 from the second nitride layer 822, or an anti- Gt; 828 < / RTI > During the erase of the memory device 800, the holes are moved toward the blocking dielectric layer 816, but most of the trapped hole charges are formed in the second nitride layer 822. [ The electron charge accumulates at the boundaries of the second nitride layer 822 after programming and thus there is less charge accumulation at the lower boundary of the first nitride layer 820. [ Moreover, due to the anti-tunneling layer 828, the probability of tunneling by the trapped electron charges of the second layer 822 is substantially reduced. This can result in lower leakage current than for conventional memory devices.

Although illustrated and described above as having two nitride layers, i.e., a first and a second layer, the present invention is not so limited, and the multilayer charge-trapping region includes a plurality (n) of nitride layers And all or any of the plurality of nitride layers may have oxygen, nitrogen and / or silicon of different stoichiometric compositions. In particular, multilayer charge storage structures having up to five and possibly more nitride layers, each of the nitride layers having different stoichiometric compositions, are contemplated. At least some of these layers may be separated from other layers by one or more relatively thin oxide layers. However, as will be appreciated by those skilled in the art, it is generally desirable to utilize as few layers as possible to achieve the desired result, thereby reducing the process steps required to create the device, thereby providing a simpler, more robust manufacturing process desirable. Moreover, utilizing as few of the layers as possible also results in higher yields, since it is simpler to control the dimensions and stoichiometric composition of the fewer number of layers.

A method of forming or fabricating a memory device comprising a fission multilayer charge-trapping region according to one embodiment will now be described with reference to the flow diagram of FIG.

Referring to FIG. 9, the method begins by forming a tunnel dielectric layer over a silicon-containing layer on the surface of a substrate (900). As noted above, in one embodiment, the tunnel dielectric layer comprises silicon dioxide (SiO ₂ ) and is formed to form a tunnel dielectric layer without ignition event to pyrolyze H ₂ and O ₂ A radical oxidation process in which hydrogen (H ₂ ) and oxygen (O ₂ ) gases are introduced into the process chamber to form radicals on the surface of the substrate to consume a portion of the substrate for the plasma oxidation process, an in- As shown in FIG.

Next, a first deuterated layer is formed on the surface of the tunneling dielectric layer (902). A first deuterated layer, a silicon source, For instance, the silane (SiH _4), chlorosilane (SiH ₃ Cl), dichlorosilane or DCS (SiH ₂ Cl _2), tetrachlorosilane (SiCl _4), or bis-tert butylamino silane (Bis-TertiaryButylAmino silane) (BTBAS ), oxygen source, temyeon this, the oxygen (O _2), or N ₂ O, and the nitrogen source-containing deuterium, temyeon this, deuterated-containing ammonia (ND ₃₎ Or may be formed or deposited in a low pressure CVD process using a process gas.

Next, a first nitride or nitride containing layer of a multilayer charge-trapping region is formed 904 on the surface of the first deuterated layer. In one embodiment, the first nitride layer comprises a silicon source, such as silane (SiH ₄ ), chlorosilane (SiH ₃ Cl), dichlorosilane or DCS (SiH ₂ Cl ₂ ), tetrachlorosilane (SiCl ₄ ) tertiary-butylamino silane (BTBAS), a nitrogen source, temyeon this, nitrogen (N _2), ammonia (NH _3), nitrogen trioxide (NO ₃₎ or nitrous oxide (N ₂ O), and an oxygen-containing gas, which For example, oxygen (O ₂ ) or N ₂ O is used to form or deposit in a low pressure CVD process. For example, the first nitride layer may be formed by maintaining the chamber at a pressure of about 5 mT (milliTorr) to about 500 mT for a period of about 2.5 minutes to about 20 minutes, In embodiments, the substrate may be deposited on the first deuterated layer by placing the substrate in a deposition chamber and introducing a process gas comprising N ₂ O, NH _3, and DCS, while maintaining the substrate at a temperature of at least about 760 ° C. In particular, the process gas comprises a first gas mixture of N ₂ O and NH ₃ mixed at a ratio of about 8: 1 to about 1: 8, and a second gas mixture of DCS and NH ₃ mixed at a ratio of about 1: 7 to about 7: Of the second gaseous mixture and may be introduced at a flow rate of from about 5 to about 200 sccm (standard cubic centimeters per minute). It has been found that the oxynitride layer produced or deposited under these conditions yields a silicon-rich oxygen-rich first nitride layer.

An anti-tunneling layer is then formed or deposited 906 on the surface of the first nitride layer. Like the tunneling oxide layer, the anti-tunneling layer can be formed or deposited by any suitable means including a plasma oxidation process, an In-Situ Steam Generation (ISSG) process or a radical oxidation process. In one embodiment, the radical oxidation process is performed by flowing hydrogen (H ₂ ) and oxygen (O ₂ ) gases into a batch-processing chamber or furnace to oxidize a portion of the first nitride layer Lt; RTI ID = 0.0 > anti-tunneling layer. ≪ / RTI >

Next, a second nitride layer of the multilayer charge-trapping region is formed 908 on the surface of the anti-tunneling layer. The second nitride layer may be deposited over a period of about 2.5 minutes to about 20 minutes at a substrate temperature of about 700 캜 to about 850 캜, and in certain embodiments at least about 760 캜, at a chamber pressure of about 5 mT to about 500 mT , Can be deposited on the anti-tunneling layer in a CVD process using a process gas comprising N ₂ O, NH _3, and DCS. In particular, the process gas comprises a first gas mixture of N ₂ O and NH ₃ mixed at a ratio of about 8: 1 to about 1: 8, and a second gas mixture of DCS and NH ₃ mixed at a ratio of about 1: 7 to about 7: Of the second gaseous mixture, and may be introduced at a flow rate of from about 5 to about 20 sccm. It has been found that the oxynitride layer produced or deposited under these conditions yields silicon-rich nitrogen-rich and oxygen-phosphorous second nitride layers.

In some embodiments, the second nitride layer is formed from BTBAS and ammonia mixed at a ratio of about 7: 1 to about 1: 7 to further include a selected concentration of carbon to increase the number of traps therein, It may be deposited over the tunneling layer in the anti-CVD process using a process gas containing (NH _3). The selected concentration of carbon in the second oxynitride layer may comprise a carbon concentration of about 5% to about 15%.

Optionally, when the multilayer charge-trapping region comprises a second deuterated layer, the method of fabricating the memory device further comprises forming (910) a second deuterated layer on the second layer of nitride . As with the first deuterated layer, the second deuterated layer can be a silicon source, such as silane (SiH ₄ ), chlorosilane (SiH ₃ Cl), dichlorosilane or DCS (SiH ₂ Cl ₂ ), tetrachlorosilane Ammonia (ND ₃ ), such as, for example, SiCl ₄ or bis tertiary butyl aminosilane (BTBAS), an oxygen source such as oxygen (O ₂ ) or N ₂ O and a nitrogen source Pressure CVD process using the process gas that it contains.

Next, a top or blocking dielectric layer is formed 912 on the surface of the second deuterated layer or the second nitride layer of the multilayer charge-trapping region. As noted above, the blocking dielectric layer may comprise any suitable dielectric material including a high-K dielectric, silicon dioxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer comprises a relatively thick SiO ₂ layer deposited or thermally grown using a CVD process. Generally, the process is performed in a deposition chamber at a pressure of from about 50 mT to about 1000 mT for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650 [deg.] C to about 850 [ , it temyeon, silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas to involve exposing, temyeon them, O ₂ or N ₂ O. Alternatively, as with the tunneling oxide layer, the blocking dielectric layer may be formed or deposited by any suitable means, including a plasma oxidation process, an In-Situ Steam Generation (ISSG) process or a radical oxidation process.

Finally, a gate layer is formed 914 on the surface of the blocking dielectric layer. In one embodiment, the gate layer is formed by a CVD process and is comprised of doped polysilicon. In another embodiment, the gate layer is formed by physical vapor deposition and is formed by depositing metal nitride, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, But are not limited to, metal-containing materials.

In another aspect, the present application is also directed to multi-gate or multi-gate-surface memory devices comprising charge trapping regions located on two or more sides of a channel region formed on or on a surface of a substrate, . Multi-gate devices include both planar and non-planar devices. A planar multi-gate device (not shown) typically includes a double-gate planar device, wherein a plurality of first layers are deposited to form a first gate beneath a channel region formed thereafter, A plurality of second layers are deposited thereon. Non-planar multi-gate devices generally include horizontal or vertical channel regions formed by or on the surface of a substrate and surrounded by gates on three or more sides.

10A illustrates an embodiment of a non-planar multi-gate memory device including a charge-trapping region. 10A, a memory device 1000, generally referred to as a finFET, is formed by depositing a layer of semiconducting material 1008 over a surface 1004 on a substrate 1006 that connects source 1008 and drain 1010 of a memory device. Layer or a thin film. The channel region 1002 is enclosed on three sides by a fin forming the gate 1012 of the device. The thickness of the gate 1012 (measured in the direction from source to drain) determines the effective channel length of the device.

According to the present disclosure, the non-planar multi-gate memory device 1000 of FIG. 10A may include a discrete charge-trapping region having one or more deuterated layers. 10B is a cross-sectional view of a portion of the non-planar memory device of FIG. 10A that includes a portion of a substrate 1006 and a channel stack 1002, a gate stack 1012 illustrating a multilayer charge-trapping region 1014. The gate 1012 further includes a gate layer 1020 and a blocking dielectric 1018 overlying the blocking layer to form the control gate of the memory device 1000 and a tunnel dielectric layer 1016 overlying the raised channel region 1002 . And is similar to the above-described embodiments. In some embodiments, the gate layer 1020 may comprise metal or doped polysilicon. Channel region 1002 and gate 1012 may be formed directly on substrate 1006 or on an insulating or dielectric layer 1022, such as a buried oxide layer, formed on or on the substrate.

Referring to FIG. 10B, in one embodiment, the multilayer charge-trapping region 1014 includes a first deuterated layer 1024 overlying a tunnel dielectric layer 1016, a first deuterated layer 1024 overlying the first deuterated layer 1024, A nitride layer 1026, and a second nitride layer 1028 disposed on or above the first nitride layer. Generally, the second nitride layer 1028 comprises a silicon-rich oxygen-phosphorus nitride layer and includes a plurality of charge traps that are distributed to a plurality of charge-trapping layers, while the first nitride layer 1026 includes Oxygen-rich nitride or silicon oxynitride and is oxygen-rich for the top charge-trapping layer to reduce the number of charge traps therein. Oxygen-rich means that the concentration of oxygen in the first charge-trapping layer 1026 is less than about 5% while the concentration of oxygen in the first nitride layer 1026 is between about 15% and about 40% .

In some embodiments, as shown, the multilayer charge-trapping region 1014 includes at least one thin, intermediate oxide or anti-tunneling (not shown) dielectric layer 1026 that separates the second nitride layer 1028 from the first nitride layer 1026 Layer 1030 as shown in FIG. As mentioned above, the anti-tunneling layer 1030 substantially reduces the probability of electron charge accumulating at the boundaries of the second nitride layer 1028 during programming from tunneling to the first nitride layer 1026 .

As with the embodiments described above, either or both of the first nitride layer 1026 and the second nitride layer 1028 can comprise silicon nitride or silicon oxynitride, and can be, for example, silicon- Can be formed by CVD processes that include N ₂ O / NH ₃ and DCS / NH ₃ gas mixtures at customized flow rates and in proportions to provide a rich and oxygen-rich oxynitride layer. A second nitride layer of the multilayer charge-trapping region is then formed on the intermediate oxide layer. The second nitride layer 1028 has a stoichiometric composition of oxygen, nitrogen, and / or silicon that is different from the stoichiometric composition of the first nitride layer 1026 and also has a silicon-rich oxygen-phosphorus second nitride layer 1028 and at a flow rate tailored to provide and use a process comprising a DCS / NH ₃ and N ₂ O / NH ₃ gas mixture in the gas ratio can be formed or deposited by a CVD process.

In those embodiments that include an anti-tunneling layer 1030 comprising an oxide, the anti-tunneling layer may be formed by oxidation of the first nitride layer 1026 to a selected depth using radical oxidation. The radical oxidation can be performed at temperatures of, for example, 1000 to 1100 占 폚 using a single wafer tool, or 800 to 900 占 폚 using a batch reactor tool. The mixture of H ₂ and O ₂ gases can be used for 1 to 2 minutes using a single wafer tool or 30 to 1 hour using a batch process for 10 to 15 Tor using a single steam tool, Lt; RTI ID = 0.0 > 500 Tor. ≪ / RTI >

In some embodiments as shown, the multilayer charge-trapping region 1014 is overlaid on a second nitride layer 1028, and a second deuterium-depletion layer (not shown) separating the second nitride layer from the blocking dielectric layer 1018 Layer (1032). As with the embodiments described above, the second deuterated layer 1032 has a deuterium concentration that is lower than the deuterium concentration of the first deuterated layer 1024.

11A and 11B, the memory device may include a nanowire channel formed with a thin film of a semi-conducting material overlying a surface on the substrate, connecting the source and drain of the memory device. A nanowire channel means a conductive channel region formed with a thin strip of crystalline silicon material having a maximum cross-sectional dimension of less than about 10 nanometers (nanometer), and more preferably less than about 6 nm. Optionally, the channel region may be formed to have a <100> surface crystalline orientation with respect to the long axis of the channel region.

11A, a memory device 1100 is formed of a layer or a thin film of a semi-conductive material on or above a surface of a substrate 1106, and connects a source 1108 and a drain 1110 of the memory device Lt; RTI ID = 0.0 &gt; 1102 &lt; / RTI &gt; In the illustrated embodiment, the device has a gate-all-around (GAA) structure in which the nanowire channel region 1102 is closed on all sides by the gate 1112 of the device. The thickness of the gate 1112 (measured in the direction from the source to the drain) determines the effective channel zone length of the device.

According to the present disclosure, the non-planar multi-gate memory device 1100 of FIG. 11A may comprise a split multi-layer charge-trapping region. 11B is a cross-sectional view of a portion of the non-planar memory device of FIG. 11A including a gate 1112 illustrating a fission multilayer charge-trapping region, a nanowire channel region 1102, and a portion of the substrate 1106. FIG. 11B, a gate 1112 is formed over the nanowire channel region 1102 to form a tunnel dielectric layer 1114 overlying the nanowire channel region 1102 to form the control gate of the memory device 1100, in addition to the fissioning multilayer charge- A blocking dielectric 1116 overlying the blocking layer, and a gate layer 1118. The gate layer 1118 may comprise a metal or doped polysilicon.

The split multi-layer charge-trapping region includes a first deuterated layer 1120 overlying a tunnel dielectric layer 1114, an internal or first nitride layer 1122 overlying the first deuterated layer 1120, Layer and an outer or second nitride layer 1124 overlying the first nitride layer 1122 or a layer comprising nitride. Generally, the second nitride layer 1124 includes a plurality of charge traps that include a silicon-rich oxygen-phosphorus nitride layer and are distributed in the split multi-layer charge-trapping region, whereas the first nitride layer 1122 Oxygen-rich nitride or silicon oxynitride, and is oxygen-rich with respect to the second nitride layer 1124 to reduce the number of charge traps therein.

In some embodiments as shown, the multilayer charge-trapping region includes at least one thin, intermediate oxide or anti-tunneling layer 1126 that separates the second nitride layer 1124 from the first nitride layer 1122, . As noted above, the anti-tunneling layer 1126 substantially reduces the probability of electron charge accumulating at the boundaries of the second nitride layer 1124 during programming from tunneling to the first nitride layer 1122 .

As with the embodiments described above, either or both of the first nitride layer 1122 and the second nitride layer 1124 may comprise silicon nitride or silicon oxynitride. The first layer of nitride 1122 may be formed, for example, at customized flow rates to provide a silicon-rich and oxygen-rich first nitride layer, and at rates of N ₂ O / NH ₃ and DCS / NH ₃ gas mixture Or the like. The second nitride layer 1124 has a stoichiometric composition of oxygen, nitrogen and / or silicon that differs from the stoichiometric composition of the first nitride layer 1122 and also provides a silicon-rich oxygen-phosphorous second nitride layer It may be formed or deposited by a CVD process in a customized flow, and using a process gas comprising DCS / NH ₃ and N ₂ O / NH ₃ gas mixture in the ratio.

In those embodiments that include an anti-tunneling layer 1126 comprising an oxide, the anti-tunneling layer may be formed by oxidation of the first nitride layer 1122 to a selected depth using radical oxidation. Radical oxidation may be performed at temperatures of, for example, 1000 to 1100 占 폚 using a single wafer tool, or 800 to 900 占 폚 using a batch reactor tool. The mixture of H ₂ and O ₂ gases can be used for 1 to 2 minutes using a single wafer tool, or for 30 minutes to 1 hour using a batch process, 10 to 15 Tor using a single steam tool, At a pressure of 300 to 500 Tor.

In some embodiments as shown, the multilayer charge-trapping region 1014 includes a second deuterium layer 1124 overlying the second nitride layer 1124 and separating the second nitride layer from the blocking dielectric layer 1116 (1128). As with the embodiments described above, the second deuterated layer 1128 has a deuterium concentration that is lower than the deuterium concentration of the first deuterated layer 1120.

11C illustrates a cross-sectional view of a vertical string of non-planar multi-gate devices 1100 of FIG. 11A arranged in a bit-cost scalable or BiCS architecture (Bit-Cost Scalable or BiCS architecture) 1130. FIG. The architecture 1130 consists of a vertical string or stack of non-planar multi-gate devices 1100, wherein each device or cell rests on a substrate 1106 and has a source and a drain And a channel region 1102 having a gate-all-around (GAA) structure in which the nanowire channel region 1102 is closed by all of the sides by a gate 1112. The BiCS architecture reduces the number of critical lithography steps compared to simple stacking of layers, resulting in reduced cost per memory bit.

In another embodiment, the memory device is a non-planar device comprising a vertical nanowire channel formed in or on a semi-conductive material that projects onto or onto a plurality of conductive, semi-conductive layers on a substrate, Device. In one version of this embodiment, which is shown cut-away in Figure 12A, the memory device 1200 includes a source of I / O 1204 and a source of drain 1206, And a nanowire channel region 1202. The channel region 1202 includes a tunnel dielectric layer 1208, a multilayer charge-trapping region 1210, a blocking layer 1212, and a gate layer (not shown) overlying the blocking layer to form the control gate of the memory device 1200 1214). The channel region 1202 may comprise an annular zone in the outer layer of a substantially solid cylinder of semi-conducting material, or it may comprise an annular layer formed on the cylinder of dielectric filler material. As with the horizontal nanowires described above, the channel region 1202 may comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel. Alternatively, if the channel region 1202 comprises crystalline silicon, the channel may be formed to have a <100> surface crystalline orientation with respect to the long axis of the channel.

12B, a multilayer charge-trapping region 1210 is formed over the first deuterated layer 1216, the first deuterated layer 1216 overlying the tunnel dielectric layer 1208, and the second deuterated layer 1216 overlying the tunnel dielectric layer 1208. In some embodiments, And a layer comprising at least an inner or first nitride layer 1218 or nitride that is deposited over the first nitride layer 1218 and an outer or second nitride layer 1220 or nitride overlying the first nitride layer 1218. [ Lt; / RTI &gt; Alternatively, as in the illustrated embodiment, the first and second nitride layers 1218 and 1220 may be separated by an intermediate oxide or anti-tunneling layer 1222. [

As with the embodiments described above, either or both of the first nitride layer 1218 and the second nitride layer 1220 may comprise silicon nitride or silicon oxynitride. The first layer of nitride 1218 may be formed at customized flow rates, for example, to provide a silicon-rich and oxygen-rich first nitride layer, and at N ₂ O / NH ₃ and DCS / NH ₃ gas mixtures May be formed by a CVD process, including The second nitride layer 1220 has a stoichiometric composition of oxygen, nitrogen, and / or silicon that is different from the stoichiometric composition of the first nitride layer 1218 and is customized to provide a silicon-rich oxygen-phosphorous second nitride layer and in the flow rate, and using a process including the DCS / NH ₃ and N ₂ O / NH ₃ gas mixture in the gas rate may also be formed or deposited by a CVD process.

In some embodiments as shown, the multilayer charge-trapping region 1210 is overlaid on a second nitride layer 1220, and a second deuterium-depletion region 1210, which separates the second nitride layer from the blocking dielectric layer 1212, Layer 1224. &lt; / RTI &gt; As with the embodiments described above, the second deuterated layer 1224 has a deuterium concentration that is lower than the deuterium concentration of the first deuterated layer 1216.

Thus, a non-volatile charge trap memory device has been disclosed. The device includes a substrate having a channel region and a pair of source and drain regions. The gate stack is between a pair of source and drain regions and above the substrate above the channel region. According to an embodiment of the present invention, the gate stack includes a multilayer charge-trapping region having a first deuterated layer. In one embodiment, the multilayer charge-trapping region further comprises a deuterium free charge-trapping layer. In an alternative embodiment, the multilayer charge-trapping zone comprises a partially deuterated charge-trapping layer having a deuterium concentration below the deuterium concentration of the first deuterated layer.

Claims (20)

As a charge trap memory device,
A substrate having a source region, a drain region, and a channel region for electrically connecting the source region and the drain region;
A tunnel dielectric layer disposed on the substrate over the channel region; And
A multi-layer structure comprising a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer, and a second nitride layer disposed on the first nitride layer, A multi-layer charge-trapping region
/ RTI &gt;
Charge trap memory device. The method according to claim 1,
Wherein the first deuterated layer comprises a deuterated derivative of a material used to form the first nitride layer.
Charge trap memory device. 3. The method of claim 2,
The first nitride layer is deuterated,
Wherein the deuterium concentration of the first nitride layer is less than the deuterium concentration of the first deuterated layer,
Charge trap memory device. The method of claim 3,
Wherein a gradient of deuterium atom concentration from the high deuterium concentration of the first deuterated zone to the low deuterium concentration of the first nitride layer is present,
Charge trap memory device. The method according to claim 1,
Wherein the first nitride layer comprises a substantially trap-free, oxygen-rich nitride layer,
Wherein the second nitride layer comprises a trap-dense, oxygen-lean nitride layer.
Charge trap memory device. The method according to claim 1,
A second deuterium layer disposed on the second nitride layer
&Lt; / RTI &gt;
Charge trap memory device. The method according to claim 1,
Wherein the channel region comprises recrystallized polysilicon,
Charge trap memory device. The method according to claim 1,
The multilayer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer.
Charge trap memory device. A charge trap memory device comprising:
A substrate having a source region, a drain region and a channel region, the channel region being formed on a surface of the substrate, the source region being formed of a thin film of a semi-conducting material electrically connecting the source and the drain;
A tunnel dielectric layer disposed over the substrate over the channel region; And
A multilayer charge-trapping region comprising a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer, and a second nitride layer disposed over the first layer,
/ RTI &gt;
Charge trap memory device. 10. The method of claim 9,
The first nitride layer is deuterated,
Wherein the deuterium concentration of the first nitride layer is less than the deuterium concentration of the first deuterated layer,
Charge trap memory device. 10. The method of claim 9,
A second deuterium layer disposed on the second nitride layer
&Lt; / RTI &gt;
Charge trap memory device. 10. The method of claim 9,
Wherein the channel region comprises polysilicon,
Charge trap memory device. 13. The method of claim 12,
Wherein the channel region comprises recrystallized polysilicon,
Charge trap memory device. A charge trap memory device comprising:
A vertical channel formed from a protrusion of a semi-conductive material extending from a first diffusion zone formed on a surface on the substrate to a second diffusion zone formed on the surface of the substrate, the vertical channel comprising a first diffusion zone, An electrical connection to the battery;
A tunnel dielectric layer adjacent the vertical channel;
A first deuterated zone adjacent the tunnel dielectric layer, a first nitride layer comprising an oxygen-rich nitride adjacent the first deuterated zone, and a silicon-rich oxygen-phosphorus nitride layer overlying the first nitride layer A multilayer charge-trapping region comprising a second nitride layer
/ RTI &gt;
Charge trap memory device. 15. The method of claim 14,
The first nitride is deuterated,
Wherein the deuterium concentration of the first nitride layer is less than the deuterium concentration of the first deuterated layer,
Charge trap memory device. 15. The method of claim 14,
The second deuterium layer overlying the second nitride layer
&Lt; / RTI &gt;
Charge trap memory device. 15. The method of claim 14,
Wherein the channel region comprises recrystallized polysilicon,
Charge trap memory device. 15. The method of claim 14,
The multilayer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer.
Charge trap memory device. 19. The method of claim 18,
Wherein the channel region comprises polysilicon,
Charge trap memory device. 20. The method of claim 19,
Wherein the channel region comprises recrystallized polysilicon,
Charge trap memory device.

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