KR20120031362A - Embedded pcb and manufacturing method for the same - Google Patents

Abstract

PURPOSE: An embedded printed circuit board and a manufacturing method thereof are provided to improve mounting density by connecting circuit devices with bumps and directly stacking the circuit devices. CONSTITUTION: A first circuit device is buried in a substrate. A second circuit device is overlapped with the first circuit device. A bump(610,630) electrically connects the first circuit device and the second circuit device. The first circuit device and the second circuit device comprise an active device and a capacitor(510,520) or register. An external circuit wiring layer is formed on a substrate surface. A via connects an external circuit wiring layer and a first capacitor.

Description

Embedded PCB and manufacturing method for the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to printed circuit board (PCB) technology, and more particularly, to an embedded printed circuit board and a manufacturing method for improving mounting density.

With the miniaturization of electronic devices, electronic components are becoming more functional and more compact. BACKGROUND ART With the advancement of digital networks, portable information terminal devices such as mobile phones and portable computers have become high performance and high functionality, and various functions have been fused and combined into one device. With the rapid increase in the amount of information, the information processing speed of the portable terminal device is also required to be rapidly improved. In addition, the substrate mounting technology for the organic connection with the logic element (LSI) for the high performance of digital devices is increasing.

As electronic devices become smaller and more functional, the number of component elements to be mounted on a printed circuit board is greatly increased, while the area of the substrate is required to be greatly reduced. In the case of a board used in a mobile phone, mounting of more component elements is required in a limited board area. In particular, since the substrate surface area is limited, a method of reducing the number of passive elements mounted on the substrate surface is required for mounting component elements for multi-function and high-performance operation on the substrate surface. While the reduction in the number of components to be mounted on the surface is required due to the limitation of the surface area of the substrate, the number of passive components to be mounted on the substrate is substantially increased for high performance operation of a portable terminal device such as a mobile phone. Thus, there is a need for development of a method that can mount more components despite limited substrate size and surface area.

The present invention intends to provide an embedded printed circuit board and a manufacturing method capable of improving the mounting density of component devices.

One aspect of the invention, a printed circuit board; A first circuit element embedded in the substrate; A second circuit element buried and superimposed on the first circuit element; And vertical bumps electrically connecting the first and second circuit elements.

The first and second circuit elements may be active elements, capacitors or resistors.

Another aspect of the invention, a printed circuit board; A first capacitor embedded in the substrate; A second capacitor buried in an overlapping manner with the first capacitor; And vertical bumps electrically connecting the first and second capacitors.

The bumps may connect the electrodes of the first and second capacitors facing each other to connect the first and second capacitors in parallel.

An outer circuit wiring layer formed on the substrate surface; And connection vias connecting the outer circuit wiring layer and the first capacitor.

A first register embedded in the substrate; A second register buried and partially overlapped with the first register; And a second bump positioned at a portion where the first and second registers partially overlap each other and connected in series with each other.

Another aspect of the invention, forming a first substrate buried in the surface of the first circuit element; Forming a second substrate in which a second circuit element opposed to the first circuit element is buried in a surface; Forming bumps on the second circuit element; Aligning the first substrate on the second substrate with an insulating layer interposed therebetween such that the first circuit element faces the bumps; And bonding the second substrate, the insulating layer, and the first substrate to each other by pressing each other, and allowing the bumps to be connected to the first circuit element through the insulating layer.

Another aspect of the invention, forming a first substrate buried in the surface of the first capacitor; Forming a second substrate having a second capacitor opposed to the first capacitor embedded in a surface thereof; Forming bumps on both electrodes of the second capacitor; Arranging the first substrate on the second substrate with an intermediate insulating layer interposed therebetween so that both electrodes of the first capacitor face the bumps; And adhering the second substrate, the insulating layer, and the first substrate to each other and bonding the bumps through the intermediate insulating layer to be connected to both electrodes of the first capacitor, thereby paralleling the first and second capacitors. An embedded printed circuit board manufacturing method including a step of connecting is provided.

Embedding a first register spaced apart from the first capacitor in the first substrate; And embedding a second register in the second substrate that is partially overlapped with the first register, wherein a second bump is connected together to connect the first and second registers in series when the bump is formed. Can be formed.

The bump may be formed in a pointed end that is opposite to the intermediate insulating layer.

The forming of the first substrate may include introducing a first insulating layer having first and second conductive layers formed on both surfaces thereof, respectively; Penetrating the first insulating layer to form a cavity in which the first capacitor is to be accommodated; Receiving the first capacitor in the cavity; Introducing a second insulating layer having a third conductive layer formed on one surface thereof so that the second insulating layer faces the first capacitor; And attaching the first capacitor to the second insulating layer by bonding the second insulating layer and the first insulating layer to each other.

Receiving the first capacitor in the cavity may include attaching an adhesive film having one surface exposed in the cavity on the first conductive layer; And adhering the first capacitor to a portion of the adhesive film exposed in the cavity.

The method may further include patterning each of the first to third conductive layers into circuit wiring layers, respectively.

According to the present invention, when a printed circuit board (PCB) is manufactured by embedding a circuit device such as a passive device or an active device in a substrate, the circuit device and the circuit device are directly stacked. stack density to improve mounting density. Since the circuit elements stacked on each other are connected by a connection bump, circuit wiring layers for connection of the circuit elements may be omitted, thereby improving mounting density.

Since bumps can directly connect circuit elements, in particular passive elements such as capacitors, to each other, capacitors stacked up and down can be directly connected in parallel to implement an increase in capacitance. Capacitors stacked up and down can be connected in parallel, so that while the area occupied by capacitors is limited to the size of a single capacitor, multiple capacitors can be connected in parallel to increase the mounting density of capacitors per substrate surface area and increase capacitance per substrate surface area. Can be implemented. In addition, when the capacitor and the capacitor are connected, a separate complicated circuit wiring layer is not interposed, and since the capacitors stacked up and down are directly connected through vertical bumps, the occurrence of noise can be suppressed by the complicated circuit wiring layer.

Since a separate circuit wiring layer connecting the embedded circuit elements may be omitted, noise may be reduced, thereby improving operation performance of the circuit elements. In addition, since the circuit elements can be connected in series or in parallel via bumps by vertical stacking directly, it is possible to overcome the limitation of the mounting density due to the limitation of the substrate surface area, and thus, the substrate surface area in the design design of the substrate. Can overcome the limitations of Since the connection path between circuit elements is shortened to the height of the vertical bump, it is possible to suppress the increase of the circuit noise caused by the increase of the connection path by the complicated long circuit wiring layer and to reduce the circuit noise, thereby improving the performance of the board. Can be.

1 to 8 are views illustrating an embedded printed circuit board and a manufacturing method according to an embodiment of the present invention.
9 and 10 illustrate the effects of an embedded printed circuit board and a manufacturing method according to an exemplary embodiment of the present invention.

Embodiments of the present invention propose a printed circuit board structure in which an embedded device or circuit elements embedded in a substrate are directly stacked on each other, and a manufacturing method therefor. The embedded circuit device may be a passive device or an active device, and in the case of a passive device, it may be a capacitor or a resistor.

When a printed circuit board is employed in a mobile terminal device or a digital device, power noise, reflection noise, or mutual disturbance of a logic element (LSI) due to low impedance at high frequency, In order to improve characteristics such as cross talk, higher capacitance is required. Capacitors account for about 60% of the total passive component parts mounted on mobile phone boards, and the number of capacitors mounted to secure capacitance is increasing. Nevertheless, since the size of the substrate is being reduced or limited, in order to ensure higher capacitance, embodiments of the present invention embed capacitor elements such as a multilayer ceramic capacitor (MLCC) in the substrate, A structure laminated directly up and down is shown.

Capacitors must be connected in parallel to ensure capacitance. When capacitors are mounted on the substrate surface, another capacitor must be surface mounted next to the surface mounted capacitor, so that the substrate surface area occupied by the capacitors increases rapidly in proportion to the number thereof. do. Since the surface area of the substrate is limited, the number of capacitors to be mounted on the substrate surface is limited. In order to overcome this, an embodiment of the present invention provides an embedded substrate structure in which a capacitor is embedded in a substrate, another capacitor is re-embedded at a position overlapped on the embedded capacitor, and repeatedly stacked to stack a plurality of capacitors. .

At this time, in order to secure a larger capacitance by connecting the capacitors in parallel, the electrodes of the stacked capacitors are vertically connected using a connection bump. Since the capacitors are directly stacked on top of each other, the increase in the substrate surface area required for the capacitor can be effectively suppressed even though the number of capacitors mounted on the substrate is increased. Accordingly, it is possible to increase the density mounted on the substrate, it is possible to realize a substrate size reduction effect of about 40% substantially.

Since the capacitor and the capacitor are directly connected by vertical bumps, a separate circuit wiring layer can be excluded to connect these capacitors. In order to connect the stacked capacitors through the circuit wiring layer, a through via and a tracer wiring layer extending to the via are required, but the electrodes of the capacitor stacked on the upper side and the capacitor stacked on the lower side through the vertical bumps are required. Since the electrodes are directly connected, i.e., capacitors are stacked in a direct lamination manner, a complicated circuit wiring layer can be omitted. Since the complicated circuit wiring layer has a long connection path due to the length of the wiring layer extending, the parasitic capacitance component and noise caused by the long connection path may be caused. In contrast, when the direct stacking through the connection bumps is limited, the connection path is limited to the bump height, and the path is simplified, so that parasitic capacitance components and noise can be effectively largely suppressed. Accordingly, the electrical characteristics and the reliability of the module including the substrate may be improved.

The embedded substrate structure by direct stacking of capacitors according to an embodiment of the present invention may be applied to a structure in which a resistor is stacked in a multilayer. Accordingly, miniaturization of the module can be effectively implemented.

1 to 8 show an embedded printed circuit board and a manufacturing method according to an embodiment of the present invention. 1 to 8 illustrate a process of implementing a printed circuit board having six circuit wiring layers, showing a substrate structure and a manufacturing method according to an exemplary embodiment of the present invention, but including the circuit wiring layers of six or more layers. Can be applied.

Referring to FIG. 1, a first copper clad laminate (CCL) 110 and a second copper laminate substrate 120 are formed for a circuit wiring layer of two and three layers (L2 / L3). The first and second copper laminated substrates 110 and 120 each have a first insulating layer 210 and a second insulating layer 220 of an insulating resin, and are formed by forming conductive layers on both surfaces thereof. For example, the first conductive layer 310 and the second conductive layer 320 of the copper layer are formed on both surfaces of the first insulating layer 210, and the third conductive layer 330 is formed on both surfaces of the second insulating layer 220. ) And a fourth conductive layer 340 are provided. The first to fourth conductive layers 310, 320, 330, and 340 are patterned into circuit wiring layers of two layers (L2), three layers (L3), four layers (L4), and five layers (L5) of the substrate. It is provided.

Referring to FIG. 2, an inner layer image transfer process on the first and second copper clad laminates 110 and 120 may be performed including photo exposure, development, and etching. The image transfer process is a process of patterning a circuit wiring layer according to a circuit diagram to be implemented by patterning a conductive layer. By performing such a first inner layer image transfer process on the first conductive layer 310 of the first copper laminated substrate 110, the first conductive layer 310 on the first insulating layer 210 is a first wiring. Patterned into layer pattern 311. In addition, a second inner layer image transfer process is performed on the fourth conductive layer 340 of the second copper-clad laminate 120, so that the fourth conductive layer 340 on the second insulating layer 220 is also a circuit wiring layer. Patterned into a four conductive layer pattern 341. The first conductive layer pattern 311 and the fourth conductive layer pattern 341 are provided as inner circuit wiring layer patterns positioned inside the substrate.

Subsequently, a first cavity 111 penetrating the first insulating layer 210 and the second conductive layer 320 is processed by using a processing method such as mechanical drilling or laser drilling. . In addition, the second cavity 121 penetrating the second insulating layer 220 and the third conductive layer 330 is processed. These first and second cavities 111 and 121 are formed to provide space for the circuit elements to be embedded in the substrate, for example passive elements such as capacitors.

Referring to FIG. 3, the first adhesive film 410 is adhered to the second conductive layer layer 320 on which patterning by image transfer is not performed, and the first cavity 111 is adhered to the first adhesive film 410. ) Accepts the first capacitor 510 as a circuit element to be embedded. Similarly, the second adhesive film 420 is adhered on the third conductive layer layer 330 on which the patterning by the image transfer is not performed, and the second cavity 121 is attached to the second cavity 121 to adhere to the second adhesive film 420. Accepts capacitor 520 as a circuit element to be embedded. This process may be applied to the process of embedding passive elements or active elements such as resistors 530 and 540 in addition to the capacitors 510 and 520. The first register 530 is accommodated in another first cavity 111 spaced apart from the first capacitor 510, and the second register 540 is spaced apart from the second capacitor 520. Can be accommodated within. At this time, the first capacitor 510 and the second capacitor 520 are accommodated in a position overlapping each other, the first register 530 is accommodated in a position where only the second register 540 and the connection portion partially overlap. Can be.

Referring to FIG. 4, the third copper-clad laminate substrate of the third insulating layer 230 in which the fifth conductive layer 350 for the circuit wiring layer of one layer L1 is formed on the surface of a conductive material such as a copper layer ( 130 is prepared, and the fourth copper-clad laminate substrate of the fourth insulating layer 240 having the sixth conductive layer 360 for the circuit wiring layer of the sixth layer L6 formed thereon with a layer of a conductive material such as a copper layer ( Prepare 140). In this case, the third insulating layer 230 and the fourth insulating layer 240 may be formed of an insulating resin forming a prepreg substrate that may be bonded to another substrate by a press.

The third copper laminated substrate 130 and the first copper laminated substrate 110 are pressed to bury the first conductive layer pattern 311 in the third insulating layer 230 of the third copper laminated substrate 130. To bond to each other. At this time, the adhesive may be made by applying heat when pressing the press. Similarly, the fourth copper laminated substrate 140 and the second copper laminated substrate 120 are pressed so that the fourth conductive layer pattern 341 is buried in the fourth insulating layer 240 of the fourth copper laminated substrate 140. press to bond to each other.

Referring to FIG. 5, the first and second adhesive films 410 and 420 are peeled off and removed, and an inner layer image transfer process is performed on each of the exposed second conductive layer 320 and the third conductive layer 330. This includes photographic exposure, development, and etching. The image transfer process is a process of patterning a circuit wiring layer according to a circuit diagram to be implemented by patterning a conductive layer. The third inner layer image transfer process is performed on the second conductive layer 320 to pattern the second conductive layer 320 on the first insulating layer 210 into the second conductive layer pattern 321 which is an inner circuit wiring layer. . In addition, a fourth inner layer image transfer process is performed on the third conductive layer 330 of the second copper-clad laminate 120 so that the third conductive layer 330 on the second insulating layer 230 is also an inner circuit wiring layer. Patterning is performed on the third conductive layer pattern 331.

Referring to FIG. 6, a conductive bump for electrical connection on the first electrode 521 and the second electrode 523 of the second capacitor 520 exposed adjacent to the third conductive layer pattern 331. : 600). In this case, the bump 600 may be formed in a shape having a pointed end such as a cone or a polygonal pyramid. The bump 600 may be formed on the first electrode 521 and the second electrode 523 by a printing method, for example, a screen print method. In this case, the bump 600 may also be formed on the electrode 541 of the second register 540 requiring the interlayer connection. Although the bump 600 is formed on the first electrode 521 and the second electrode 523 of the second capacitor 520, and the electrode 541 of the second register 540, the first electrode 521 is illustrated. The first electrode 511 and the second electrode 513 of the capacitor 510 may be formed on the electrode 531 of the first register 530.

After the bump 600 is formed, the third conductive layer pattern 331 and the second conductive layer pattern 321 face each other, that is, the first capacitor 510 and the second capacitor 520 face each other. In between, a substrate of the fifth insulating layer 250, for example, a prepreg substrate is introduced. Afterwards, the bump 600 is press-pressed to penetrate the fifth insulating layer 250 to bond the third conductive layer pattern 331 and the second conductive layer pattern 321 to the fifth insulating layer 250. Let's do it. Accordingly, the entire embedded printed circuit board 100 is configured.

Referring to FIG. 7, as the press 600 is pressed through the bump 600 through the fifth insulating layer 250, the first electrode 511 and the second capacitor 520 of the first capacitor 510 may be formed. A first bump 610 is provided to interconnect the first electrode 521, and the second electrode 513 of the first capacitor 510 and the second electrode 523 of the second capacitor 520 are interconnected. A second bump 630 is provided. The first and second capacitors 510 and 520 isolated by the fifth insulating layer 250 by the first bump 610 and the second bump 630 of the vertical shape are connected in parallel to each other.

Therefore, in order to implement separate circuit wiring layers for connecting the first and second capacitors 510 and 520 in parallel with each other, no intervening of a separate conductive layer is required. Since the first and second capacitors 510 and 520 may be connected in parallel with each other only by the first bump 610 and the second bump 630, the connection path may be shortened very short, thereby generating parasitic capacitance or noise. It can be effectively suppressed. Thus, it is possible to effectively increase the capacity of the total capacitance that can be realized by the capacitors. Since the capacitors 510 and 520 can be embedded in the substrate 100 by direct stacking, it is possible to mount a plurality of capacitors on the substrate 100 without increasing the surface area of the substrate 100 occupied by the capacitor.

The third bump 640 penetrating the fifth insulating layer 250 connects the electrode 531 of the first register 530 and the electrode 541 of the second register 540. Accordingly, the first register 530 and the second register 540 may be connected in series to implement an increased resistance capacitance.

Referring to FIG. 8, a laser drilled through a via hole exposing each of the first electrode 511 and the second electrode 513 of the first capacitor 510 through the third insulating layer 230. and a first connection via 352 and a second connection via 353 connected to the exposed first electrode 511 and the second electrode 513, respectively. In this case, a via hole exposing the other electrodes 532 and 542 of the first register 530 may also be formed, and third connection vias 354 and 362 connected thereto may be formed. These connecting vias electrically connect the embedded capacitor or resistor to the outer circuit wiring layer. Meanwhile, in order to electrically connect the fifth conductive layer 350 and the sixth conductive layer 360 which are exposed to both surfaces of the substrate 100 to face each other, a through hole penetrating the entire substrate 100 (not shown). And a through via (not shown) connecting the fifth conductive layer 350 and the sixth conductive layer 360 through the through hole. The connection via or the through via may be formed by extending the conductive layer into the via hole or the through hole by using a conductive layer forming method such as copper plating.

The fifth conductive layer pattern 351 and the sixth conductive layer pattern 361 are performed by performing an outer layer image transfer process on each of the fifth conductive layer 350 and the sixth conductive layer 360 exposed to the outside of the substrate 100. To form. The image transfer process is a process of patterning a circuit wiring layer according to a circuit diagram to be implemented by patterning a conductive layer. The first outer layer image transfer process is performed on the fifth conductive layer 350 to pattern the fifth conductive layer 350 into a fifth conductive layer pattern 351 as a circuit wiring layer. In addition, a second outer layer image transfer process is performed on the sixth conductive layer 360 to pattern the sixth conductive layer 360 into a sixth conductive layer pattern 361 which is also a circuit wiring layer. Subsequently, a solder mask 170 is formed to cover the fifth and sixth conductive layer patterns 351 and 361 to expose an exposed portion for connecting to an external device, for example, a connection pad or a land ( Only a portion of the land is selectively exposed and the remaining fifth and sixth conductive layer patterns 351 and 361 are covered and protected.

9 and 10 are views showing the effect of the embedded printed circuit board and the manufacturing method according to an embodiment of the present invention.

Referring to FIG. 9, an embedded printed circuit board according to an exemplary embodiment of the present invention repeats a process of accommodating a circuit element such as a capacitor and forming a bump, thereby forming a plurality of capacitors 501 and 502 in the substrate 100. , 503, 504, and 505 may be stacked to overlap each other, and may be directly connected through the bump 601. Although a plurality of capacitors 501, 502, 503, 504, 505 are directly stacked, each capacitor is electrically connected only to the bumps 601, and no separate wiring circuits are required for their connection.

Accordingly, the design design of the inner circuit wiring layer 301 can be simplified, so that the constraints are effectively reduced in the design of the substrate, thereby enabling various designs. Since the direct connection by the bump 601 is possible, it is not necessary to include separate complicated wiring circuits as the inner conductive layer pattern, and the operation performance of the device is lowered by inducing noise or parasitic capacitance by the conductive layer patterns. Can be effectively suppressed. Connection vias connected to the two electrodes of one capacitor 501, respectively, to connect capacitors 501, 502, 503, 504, 505 to another external circuit wiring layer, i.e., the outer circuit wiring layers 303, 304. Since only 305 is required, no complicated connection wiring structure is required for the electrical connection of capacitor 501.

Referring to FIG. 10, as a comparative example in contrast to the effect according to the exemplary embodiment of the present invention, the substrate 10 may be formed of the circuit wiring layers 31, 32, 33, 34, 35, 36, 37, 38, and 39, not bumps. Considering the case where the embedded capacitors 50 are connected to each other, a very complicated circuit wiring layer 31, 32, 33, 34, 35, 36, 37, 38, 39) The design and implementation of the structure is required.

In order to connect the electrodes 51 and 53 of the capacitor 50 in parallel, the structure of the circuit wiring layer connecting the first electrodes 51 and the structure of the circuit wiring layer connecting the second electrodes 53 are mutually different. It must be electrically isolated by the solder mask 17. Accordingly, the first through via 33 formed in the first connection via 31, the first outer layer circuit wiring 32, and the first through hole 11 so as to connect the first electrodes 51 to the first electrode 51 is connected thereto. A plurality of first inner layer circuit wires 34 are required. In addition, a second through via 37 formed in the second connection via 35, the second outer layer circuit wiring 36, and the second through hole 12 so as to interconnect the first electrodes 51. A plurality of second inner layer circuit wires 38 to be connected are required. In addition, internal connection vias 39 are also required for connecting the inner circuit wirings 34 and 38 to the electrodes of the capacitor 50 embedded inside the substrate 100. The parallel connection of the capacitors 50 requires the design and implementation of a very complex circuit wiring layer 31, 32, 33, 34, 35, 36, 37, 38, 39 structure.

In order to connect the capacitors 50 in parallel, a very complicated circuit wiring layer 31, 32, 33, 34, 35, 36, 37, 38, 39 structure is required, so a wide variety of constraints may arise in the design thereof. Design Design can be very difficult and the process of implementing it becomes very complex. In contrast, the embedded printed circuit board according to the exemplary embodiment of the present invention as shown in FIG. 9 may be implemented in a relatively simple structure, which is relatively easy in design, and the process of implementing the same may be relatively simplified. Furthermore, since the surface area of the substrate required for mounting the capacitors per capacitor to be mounted can be greatly reduced as compared to the case of mounting the capacitors side by side on the surface of the substrate, the embedded printed circuit board according to an embodiment of the present invention in various portable devices It can be applied effectively.

100: printed circuit board, 510, 520: capacitor,
610, 630: bump.

Claims (14)

Printed circuit board;
A first circuit element embedded in the substrate;
A second circuit element buried and superimposed on the first circuit element; And
And vertical bumps electrically connecting the first and second circuit elements.
The method of claim 1,
And the first and second circuit elements are active elements, capacitors or resistors.
Printed circuit board;
A first capacitor embedded in the substrate;
A second capacitor buried in an overlapping manner with the first capacitor; And
An embedded printed circuit board comprising vertical bumps electrically connecting the first and second capacitors.
The method of claim 3,
And the bumps connect electrodes of the first and second capacitors facing each other to connect the first and second capacitors in parallel.
The method of claim 3,
An outer circuit wiring layer formed on the substrate surface; And
The printed circuit board of claim 1, further comprising connecting vias connecting the outer circuit wiring layer and the first capacitor.
The method of claim 3,
A first register embedded in the substrate;
A second register buried and partially overlapped with the first register; And
And a second bump positioned at a portion where the first and second registers partially overlap each other and connected in series with each other.
Forming a first substrate with the first circuit element embedded in the surface;
Forming a second substrate in which a second circuit element opposed to the first circuit element is buried in a surface;
Forming bumps on the second circuit element;
Aligning the first substrate on the second substrate with an insulating layer interposed therebetween such that the first circuit element faces the bumps; And
And bonding the second substrate, the insulating layer, and the first substrate to each other by pressing each other, and allowing the bumps to be connected to the first circuit element through the insulating layer.
The method of claim 7, wherein
And the first and second circuit elements are introduced into an active element, a capacitor or a resistor.
Forming a first substrate having the first capacitor embedded in the surface;
Forming a second substrate having a second capacitor opposed to the first capacitor embedded in a surface thereof;
Forming bumps on both electrodes of the second capacitor;
Arranging the first substrate on the second substrate with an intermediate insulating layer interposed therebetween so that both electrodes of the first capacitor face the bumps; And
The second substrate, the insulating layer, and the first substrate are pressed and bonded to each other, and the bumps penetrate the intermediate insulating layer to be connected to both electrodes of the first capacitor, thereby connecting the first and second capacitors in parallel. Embedded printed circuit board manufacturing method comprising the step of.
10. The method of claim 9,
Embedding a first register spaced apart from the first capacitor in the first substrate; And
Embedding a second register in the second substrate, the second substrate being partially overlapped with the first register;
And forming a second bump to connect the first and second registers in series when the bump is formed.
10. The method of claim 9,
The bump is an embedded printed circuit board manufacturing method, characterized in that the end opposite to the intermediate insulating layer is formed in a pointed shape.
10. The method of claim 9,
Forming the first substrate is
Introducing first insulating layers each having first and second conductive layers formed on both surfaces thereof;
Penetrating the first insulating layer to form a cavity in which the first capacitor is to be accommodated;
Receiving the first capacitor in the cavity;
Introducing a second insulating layer having a third conductive layer formed on one surface thereof so that the second insulating layer faces the first capacitor; And
And bonding the second insulating layer and the first insulating layer to each other so that the first capacitor is adhered to the second insulating layer.
The method of claim 12,
Receiving the first capacitor in the cavity
Attaching an adhesive film having one surface exposed in the cavity on the first conductive layer; And
Adhering the first capacitor to a portion of the adhesive film exposed in the cavity.
The method of claim 13,
And patterning each of the first, second, and third conductive layers into circuit wiring layers, respectively.

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