KR20110072526A - Method of fabricating semiconductor apparatus - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to secure the operational margin regardless of the scale of patterns in the semiconductor device by connecting a bit line and a first bit-line contact without a separate pad or contact. CONSTITUTION: A first interlayer insulating film(304) is formed on a semiconductor substrate. An etching stop film(306) is formed on the first interlayer insulating film. A second interlayer insulating film is formed on the etching stop film. A first bit-line contact(312) and a second bit-line contact(314) in connection with the semiconductor substrate are formed. A trench is formed by partially etching the interlayer insulating film and the bit-line contact. A bit-line is formed in the trench. A metal contact is formed on the second bit-line contact.

Description

Manufacturing method of semiconductor device {METHOD OF FABRICATING SEMICONDUCTOR APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a transistor and a contact that operate stably in a highly integrated semiconductor memory device.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such a semiconductor is used to create a semiconductor device such as a transistor by adding impurities and connecting conductors. A device having various functions made using the semiconductor device is called a semiconductor device. A representative example of such a semiconductor device is a semiconductor memory device.

Recently, semiconductor memory devices are being developed to reduce power consumption while storing more data in a limited space. For this reason, the size of components included in the semiconductor memory device is decreasing, and the design rule in the process of manufacturing the semiconductor memory device is also decreasing. Recently, as the design rule is reduced to 100 nm or 50 nm or less, it is becoming difficult to form a large number of components included in a semiconductor memory device without defects.

Specifically, the semiconductor memory device may be divided into a core region including a unit cell composed of a capacitor and a transistor, and a peripheral region including a plurality of power supply circuits, a decoding circuit, an input / output circuit, and the like. In order to increase the integration density of semiconductor memory devices, many efforts have been made to form a smaller number of unit cells in a core area that occupies a large area. Pads and contacts with patterns of various shapes have been used. However, in recent years, due to the reduced design rules of not only the core area but also the peripheral area, there are many restrictions in forming various patterns.

1 is a plan view illustrating a peripheral area of a general semiconductor device.

As illustrated, the peripheral region of the semiconductor device may include a first bit line contact 110 connected to a source / drain region of an active region (not shown) and a bit line pad 120 formed on the first bit line contact 110. And a bit line 130 formed on the bit line pad 120. The bit line pad 120 may be added to prevent and minimize an electrical short between an adjacent gate pattern or a neighboring landing plug and a bit line when connecting the first bit line contact 110 and the bit line 130. It serves as a seam formed by.

However, in order to improve the degree of integration, the design rule is reduced to 30 nm or less, and is not a simple line-shaped pattern, but rather complicated as a polygon or a circle such as the conventional bit line 130 or the first bit line contact 110. It has become difficult to form a pattern of shapes.

The laminated structure composed of contacts and wirings formed on the active region defined in the semiconductor substrate should be prevented from increasing the resistance due to alignment errors that may be connected to each other or short circuiting of the contacts and wirings formed around the semiconductor device. The defect can be prevented. However, as design rules become smaller, the distance between adjacent wiring, gate patterns, or pads decreases, making contact formation for connecting multiple components formed on the active area to each other and electrically isolating the surrounding elements difficult. .

2 is a plan view illustrating an improved semiconductor device.

As shown, the semiconductor device includes a bit line 230 formed in a line shape. In addition, a first bit line contact 210 electrically connected to the bit line 230 is formed at a lower portion between the adjacent bit lines 230. When viewed in a vertical direction on a semiconductor substrate rather than a plane, a bit line pad formed in a complex pattern is removed due to a decrease in design rules, and the first bit line contact 210 and the bit line 230 are directly connected. . Here, the semiconductor device is characterized by simplifying the form of all the contacts and wirings by reducing the design rules.

Although the bit line 230 in the form of a line has an effect of increasing the process margin in patterning even with reduced design rules, the bit line pad is removed and the first bit line contact 210 and the bit line 230 are directly connected to each other. An electrical short occurs between the other bit line 230 and the first bit line contact 210. In addition, between the bit line 230 and the second bit line contact 240 formed between the contact connected to the power supply wiring and the like, not the bit line 230, and the source / drain region of the active region (not shown). There is a high possibility that an electrical short will occur because not enough distance is secured. As a result, it has succeeded in securing process margins due to the reduction of design rules, but it is difficult to prevent defects in the semiconductor device due to an electrical short circuit between the first bit line contact and the adjacent bit line formed on the active region. There is a problem that impairs the stability of the operation.

In order to solve the above-described conventional problems, the present invention provides a first bit line contact when forming a first bit line contact connected to a bit line and a second bit line contact connected to a wiring for supplying power in a peripheral area. Partial etching is performed to form a step line, and then a bit line is formed and a hard mask insulating film is formed on the bit line to secure process margin by preventing an electrical short circuit or short circuit between the wiring and the contact formed on the bit line and the bit line. A manufacturing method of a semiconductor device can be provided.

The present invention provides a method of forming an insulating film on a semiconductor substrate; Forming a first bit line contact and a second bit line contact penetrating the interlayer insulating layer to be connected to the semiconductor substrate; Forming a bit line in the trench formed by partially etching the interlayer insulating layer and the first bit line contact; And forming a metal contact on the second bit line contact.

Preferably, forming the interlayer insulating film on the semiconductor substrate comprises: forming a first interlayer insulating film on the semiconductor substrate; Forming an etch stop layer on the first interlayer insulating layer; And forming a second interlayer insulating layer on the etch stop layer.

Preferably, the etch stop film comprises a nitride film, characterized in that formed to a thickness of 10 kPa to 200 kPa.

Preferably, the first and second interlayer insulating films include an oxide film, the first interlayer insulating film is formed thicker than a height of a gate pattern, and the second interlayer insulating film is formed on the bit line and the bit line. And a thickness including the bit line hard mask layer.

Preferably, forming the first bit line contact and the second bit line contact through the interlayer insulating layer to be connected to the semiconductor substrate may include passing through the second interlayer insulating layer, the etch stop layer, and the first interlayer insulating layer. Forming a first trench; Forming a first spacer on sidewalls of the first trenches; Depositing a conductive material in the first trench; And planarizing until the second interlayer insulating film is exposed.

Preferably, the first spacer includes a nitride film and is formed to a thickness of 10 kPa to 90 kPa.

Preferably, the conductive material may include titanium (Ti) or cobalt (Co) constituting the metal barrier film and tungsten (W) constituting the metal layer.

The forming of the bit line in the trench formed by etching the interlayer insulating layer and the first bit line contact may include forming a first pattern by performing an exposure process using a mask defining a position of the bit line. step; Etching the first bit line contact, the second interlayer insulating layer, and the etch stop layer by using the first pattern as an etch mask to form a second trench; Forming a second spacer on a sidewall of the second trench; Depositing a conductive material in the second trench; Forming a hard mask film on the conductive material; And planarizing until the second bitline contact is exposed.

Preferably, the second spacer is formed to a thickness of 10 Å to 200 통해 through plasma etching after deposition of the nitride film.

Preferably, the conductive material comprises tungsten (W), characterized in that formed to a thickness of about 500 kPa.

Preferably, the hard mask film comprises a nitride film, characterized in that formed to a thickness of about 1200 kPa.

Advantageously, forming a metal contact on said second bit line contact comprises depositing a third interlayer insulating film over said interlayer insulating film and said bit line; Etching the third interlayer insulating film to form a third trench that exposes the second bit line contact; Forming a third spacer on a sidewall of the third trench; And depositing a conductive material on the third trench.

In addition, the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Forming a first bit line contact and a second bit line contact penetrating the interlayer insulating layer to be connected to the semiconductor substrate; Forming a bit line in the trench formed by partially etching the interlayer insulating layer and the first bit line contact; And forming a metal contact on the second bit line contact, wherein the height of the second bit line contact is equal to or higher than the height of the bit line. do.

Preferably, an etch stop layer is included between the bit line and the second bit line contact.

The present invention applies a damascene process for forming a bit line after forming a step in a first bit line contact formed with a metal contact, and applying the bit line contact adjacent to the bit line and the bit line and the upper part of the bit line. There is an advantage of preventing an electrical short between the metal wiring and the contact for supplying the formed power.

In addition, the present invention can use the mask process used in the prior art without additional mask process, and can connect the bit line and the first bit line contact without forming a separate pad or contact, even under the design rule of 30nm or less The process margin can be secured in forming the pattern.

The semiconductor device manufacturing method according to the present invention includes a wiring for supplying power and a first bit line contact connected to the bit line in a peripheral area in order to secure a process margin for forming the bit line even under a design rule of 30 nm or less; In the process of forming the second bit line contact to be connected, a bit line is formed by applying a damascene process of filling a conductive material after forming a step in the first bit line contact. As a result, the position where the bit line is formed is lowered as compared with the related art, and the vertical distance is secured instead of the horizontal distance with the second bit line contact, thereby ensuring electrical isolation from the contact adjacent to the bit line. Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a landing plug is formed after forming the interlayer insulating layers 304 and 308 on the semiconductor substrate 302. In detail, after the first interlayer dielectric 304 is deposited on the semiconductor substrate 302, an etch stop layer 306 is formed on the first interlayer dielectric 304. In this case, the etch stop film 306 includes a nitride film and is formed to a thickness of 10 kPa to 200 kPa. Thereafter, a second interlayer insulating layer 308 is formed on the etch stop layer 306.

Here, the first and second interlayer insulating films 304 and 308 include an oxide film, wherein the first interlayer insulating film 304 is formed thicker than the height of a gate pattern (not shown) formed on the semiconductor substrate 302. Is characteristic. In addition, the second interlayer insulating film 308 may be formed to a thickness including a bit line and a bit line hard mask film to be formed later.

Thereafter, a first bit line contact 312 and a second bit line contact 314 are formed through the first and second interlayer insulating layers 304 and 308 to be connected to the semiconductor substrate 302. Here, the first bit line contact 312 formed in the peripheral region of the semiconductor device is connected to the bit line, and the second bit line contact 314 is connected to the metal wire for supplying power through the contact. First, the second interlayer insulating layer 308, the etch stop layer 306, and the first interlayer insulating layer may be formed through an exposure process using a mask defining positions of the first bit line contact 312 and the second bit line contact 314. The 304 is etched to form trenches (not shown) that expose the semiconductor substrate 302. Thereafter, the first spacer 310 is formed on the sidewall of the trench. The first spacer 310 includes a nitride film and is formed to have a thickness of 10 kV to 90 kV.

A conductive material is filled in the trench between the first spacers 310 to complete the first bitline contact 312 and the second bitline contact 314. In this case, according to the embodiment, after forming a metal barrier film including titanium (Ti) or cobalt (Co) in the trench, a metal layer may be formed of tungsten (W). Thereafter, planarization is performed until the second interlayer insulating film 308 is exposed.

In the subsequent process, a bit line is formed through a damascene process of filling a conductive material by forming a step between the first bit line contact 312 and the second bit line contact 314.

Referring to FIG. 3B, an exposure process is performed using a mask defining a position at which a bit line is to be formed to form a first pattern 316. In this case, the first pattern 316 serves as an etching mask, and may be configured as a photoresist film, or may be configured as a separate hard mask film under the photoresist film.

Referring to FIG. 3C, using the first pattern 316 as an etching mask, the first bit line contact 312, the second interlayer insulating layer 308, and the etch stop layer are exposed until the first interlayer insulating layer 304 is exposed. 306 is etched to form second trench 318. Since the thickness of the bit line and the hard mask film to be formed in a subsequent process is formed in the deposition of the second interlayer insulating layer 308 described above, the first interlayer insulating layer 304 is formed to expose the second trench 318. You can control the depth.

Referring to FIG. 3D, the second spacer 320 is formed on the sidewall of the second trench 318. In this case, the second spacer 320 is formed to have a thickness of 10 kPa to 200 kPa through plasma etching after deposition of the nitride film.

Referring to FIG. 3E, the bit line 322 is formed by filling a conductive material in the second trench 320 and then performing an etch back process to adjust the thickness. Thereafter, a hard mask layer 324 is deposited on the bit line 322. Here, the bit line 322 includes tungsten (W), and is formed to a thickness of about 500 mW. The hard mask film 324 includes a nitride film and is formed to a thickness of about 1200 GPa. Thereafter, planarization is performed until the second bit line contact 314 is exposed.

Referring to FIG. 3F, the metallization contact 326 is formed on the second bit line contact 314. In detail, a third interlayer insulating layer 328 is deposited on the second interlayer insulating layer 308 and the hard mask layer 324 on the bit line 322. The third interlayer insulating layer 328 is etched to form a third trench (not shown) exposing the second bit line contact 314, and a third spacer 330 is formed on sidewalls of the third trench. Thereafter, the conductive material is deposited on the third trenches to complete the metallization contact 326.

Since the metallization contact 326 formed on the bit line 322 is wider than the first and second bit line contacts 312 and 314, it is likely to short-circuit with neighboring components. . However, in the present invention, in the process of exposing the second bit line contact 314 to form the metal wiring contact 326, the metal wiring is removed by removing an insulating film including a nitride film or the like on the second bit line contact 314. The contact resistance between the contact 326 and the second bit line contact 314 may be reduced. As a result, the bit line pad is not necessary, and the metal wire contact 326 and the second bit line contact 314 are connected to a position higher than the bit line 322 to form the metal wire contact 326. The necessary process margin is secured. In this process, a plasma etch method for removing the nitride film or a nitride film etching process using phosphoric acid may be performed. Unlike the related art, a thick hard mask film 324 is formed on the bit line 322 to generate an electrical short circuit. Can be suppressed.

Further, in the semiconductor device according to the exemplary embodiment of the present invention, the metallization contact 326 is formed to a height of about 20 KΩ or less. Accordingly, the etching process is performed for a long time to etch the third interlayer insulating layer 328 to form the third trench, and the hard mask layer 324 on the bit line 322 serves as an etch stop layer to prevent over-etching. You can also do

Although not shown, in a subsequent process, a metal wiring capable of supplying a high voltage, a power supply voltage, a core voltage, and the like may be formed in the semiconductor device on the metal wiring contact 326.

Conventionally, the bit line 322 is formed in the form of a line due to the reduction of design rules, and there is not enough margin for electrical isolation from the metallization contact 326 positioned between the adjacent bit lines 322. In the present invention, since the bit line 322 is formed at the height of the second bit line contact 314 below the metallization contact 326 through a damascene process, a margin that is not horizontally secured is vertically secured. It works. Through this, even in an environment where the design rule is 30 nm or less, process margins for patterning the bit lines 322 may be secured. In addition, since the bit line pads included in the conventional semiconductor device can be removed, and complicated patterns formed to prevent electrical shorts between the contacts are unnecessary, a number of mask processes can be reduced in the manufacturing process of the semiconductor device. Can be.

As described above, the method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an interlayer insulating film on a semiconductor substrate, a first bit line contact and a second bit line passing through the interlayer insulating film and connected to the semiconductor substrate. Forming a contact, forming a bit line in a trench formed by etching the interlayer insulating film and the first bit line contact, and forming a metal contact on the second bit line contact. A semiconductor device manufactured according to this manufacturing method is characterized in that the height of the second bit line contact is equal to or higher than the height of the bit line, and an etch stop layer is included between the bit line and the second bit line contact. .

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 is a plan view for explaining a general semiconductor device.

2 is a plan view for explaining the improved semiconductor device.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (14)

Forming an interlayer insulating film on the semiconductor substrate; Forming a first bit line contact and a second bit line contact penetrating the interlayer insulating layer to be connected to the semiconductor substrate; Forming a bit line in the trench formed by etching the interlayer insulating layer and the bit line contact; And Forming a metal contact on the second bitline contact Method for manufacturing a semiconductor device comprising a. The method of claim 1, Forming an interlayer insulating film on the semiconductor substrate Forming a first interlayer insulating film on the semiconductor substrate; Forming an etch stop layer on the first interlayer insulating layer; And And forming a second interlayer insulating film on the etch stop layer. The method of claim 2, The etch stop film includes a nitride film and is formed in a thickness of 10 kPa to 200 kPa. The method of claim 2, The first and second interlayer insulating films include an oxide film, the first interlayer insulating film is formed to be thicker than a height of a gate pattern, and the second interlayer insulating film is formed on the bit line and the bit line. A method of manufacturing a semiconductor device, which is formed by a thickness including a mask film. The method of claim 2, Forming a bit line contact and a second bit line contact penetrating the interlayer insulating layer to be connected to the semiconductor substrate; Forming a first trench penetrating the second interlayer insulating layer, the etch stop layer, and the first interlayer insulating layer; Forming a first spacer on sidewalls of the first trenches; Depositing a conductive material in the first trench; And And planarizing until the second interlayer insulating film is exposed. The method of claim 5, The first spacer includes a nitride film, and is formed in a thickness of 10 GPa to 90 GPa. The method of claim 5, The conductive material includes titanium (Ti) or cobalt (Co) constituting the metal barrier film and tungsten (W) constituting the metal layer. The method of claim 2, Forming a bit line in the trench formed by etching the interlayer insulating layer and the bit line contact. Forming a first pattern by performing an exposure process using a mask defining a position of the bit line; Etching the bit line contact, the second interlayer insulating layer, and the etch stop layer by using the first pattern as an etch mask to form a second trench; Forming a second spacer on a sidewall of the second trench; Depositing a conductive material in the second trench; Forming a hard mask film on the conductive material; And And planarizing until the second bit line contact is exposed. The method of claim 8, The second spacer is a method of manufacturing a semiconductor device, characterized in that formed after the deposition of the nitride film to a thickness of 10 ~ 200 Å through plasma etching. The method of claim 8, The conductive material includes tungsten (W) and is formed in a thickness of about 500 GPa. The method of claim 8, The hard mask film includes a nitride film and is formed to a thickness of about 1200 GPa. The method of claim 1, Forming a metal contact on the second bit line contact Depositing a third interlayer insulating film over the interlayer insulating film and the bit line; Etching the third interlayer insulating film to form a third trench that exposes the second bit line contact; Forming a third spacer on a sidewall of the third trench; And And depositing a conductive material in the third trench. The semiconductor device of claim 1, wherein the height of the second bit line contact is equal to or higher than the height of the bit line. The method of claim 13, And a etch stop layer is disposed between the bit line and the second bit line contact.

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