KR20110026049A - Input buffer for semiconductor apparatus - Google Patents

Input buffer for semiconductor apparatus Download PDF

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Publication number
KR20110026049A
KR20110026049A KR1020090083769A KR20090083769A KR20110026049A KR 20110026049 A KR20110026049 A KR 20110026049A KR 1020090083769 A KR1020090083769 A KR 1020090083769A KR 20090083769 A KR20090083769 A KR 20090083769A KR 20110026049 A KR20110026049 A KR 20110026049A
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KR
South Korea
Prior art keywords
input buffer
semiconductor device
resistance value
frequency
differential
Prior art date
Application number
KR1020090083769A
Other languages
Korean (ko)
Inventor
양지연
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090083769A priority Critical patent/KR20110026049A/en
Publication of KR20110026049A publication Critical patent/KR20110026049A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)

Abstract

An input buffer of a semiconductor device capable of buffering input signals of various frequency bands is disclosed. The input buffer of the semiconductor device for this purpose includes a frequency detector for detecting the frequency of the input signal; And a plurality of resistors selectively activated according to the detection result of the frequency detector, wherein amplification gain is adjusted according to an internal resistance value ratio of the activated resistor unit to output a differential output signal corresponding to the input signal. An amplifier part is provided.

Description

Input buffer of semiconductor device {INPUT BUFFER FOR SEMICONDUCTOR APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique for configuring an input buffer.

In general, a semiconductor device buffers an input signal applied from an external source and provides it to an internal circuit.

1 is a block diagram of an input buffer of a semiconductor device of the prior art.

Referring to FIG. 1, an input buffer of a semiconductor device according to the related art includes a first differential amplifier 11 and a second differential amplifier 12.

The first differential amplifier 11 determines the input signal IN based on the reference voltage VREF and generates differential output signals OUT1 and OUT1B. In addition, the second differential amplifier 12 amplifies the differential output signals OUT1 and OUT1B and outputs the final output signals DIFF_OUT and DIFF_OUTB of the differential type. That is, the input buffer is configured in the form of a multistage amplifier circuit.

The first differential amplifier 11 includes resistors R1 and R2 connected between the power supply voltage terminal VDD and the differential output terminals N1 and N2. The first differential amplifier 11 includes resistors R1 and R2. Therefore, amplification gain is determined. The resistance values of the first resistor element R1 and the second resistor element R2 constituting the resistor portions R1 and R2 are fixed. Therefore, when the frequency band of the applied input signal IN is changed, the input buffer must be redesigned to obtain the desired amplification gain. That is, the input buffer of the semiconductor device of the prior art is inflexible to the change in operating conditions after the design.

The present invention has been proposed to solve the above-mentioned conventional problems, and an object thereof is to provide an input buffer of a semiconductor device capable of buffering input signals of various frequency bands.

In addition, another object of the present invention is to provide an input buffer of a semiconductor device capable of buffering an input signal of various frequency bands and adjusting a duty ratio.

According to an aspect of the present invention for achieving the above technical problem, a frequency detector for detecting the frequency of the input signal; And a plurality of resistors selectively activated according to the detection result of the frequency detector, wherein amplification gain is adjusted according to an internal resistance value ratio of the activated resistor unit to output a differential output signal corresponding to the input signal. An input buffer of a semiconductor device having an amplifier is provided.

In addition, according to another aspect of the invention, the frequency detection unit for detecting the frequency of the input signal to output a frequency detection code; And first and second resistance group groups in which the corresponding resistance unit selected by the frequency detection code is activated, and the amplification gain and duty ratio are adjusted according to the internal resistance value ratio of the activated resistance unit. An input buffer of a semiconductor device having a first differential amplifier for outputting a differential output signal corresponding to a signal is provided.

The input buffer of the semiconductor device to which the present invention is applied can buffer input signals of various frequency bands with desired amplification gain. Therefore, even if the frequency of the applied input signal is changed, it is possible to generate an output signal having a desired amplification gain without changing the design.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. For reference, in the drawings and detailed description, terms, symbols, symbols, etc. used to refer to elements, blocks, etc. may be represented by detailed units as necessary, and therefore, the same terms, symbols, symbols, etc. are the same in the entire circuit. Note that it may not refer to.

2 is a configuration diagram of an input buffer of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, an input buffer of a semiconductor device includes a frequency detector 21 for detecting a frequency of an input signal IN and a plurality of resistors 200 selectively activated according to a detection result of the frequency detector 21. Amplification gain is adjusted according to the ratio of the internal resistance value of the activated resistors R_A <i> · R_B <i> to output differential output signals OUT1 and OUT1B corresponding to the input signal IN. The first differential amplifier 22 is provided for.

For reference, as shown in the present embodiment, the input buffer of the semiconductor device amplifies the differential output signals OUT1 and OUT1B to output the final output signals DIFF_OUT and DIFF_OUTB in differential form. It may be further configured in the form of a multi-stage amplification circuit. The second differential amplifier 23 operates by controlling the enable signal EN1 and receives the differential output signals OUT1 and OUT1B through the differential input units MN4 and MN5 to the differential output terminals N3 and N4. Outputs the amplified differential type final output signals (DIFF_OUT, DIFF_OUTB).

The detailed configuration and main operations of the input buffer of the semiconductor device configured as described above are as follows.

The frequency detector 21 detects the frequency of the input signal IN and outputs a frequency detection code R_CODE <1: N> corresponding to the detected frequency.

In addition, the first differential amplifier 22 includes a plurality of resistor units 200, differential input units MN1 and MN2, and biasing units MN3 and R3. The biasing units MN3 and R3 provide a bias current in response to the enable signal EN1, and the differential input units MN1 and MN2 receive a reference voltage VREF and an input signal IN. A plurality of resistor portions R_A <1>, R_B <1>, SW <1>, ..., R_A <N-1>, R_B <N-1>, SW <N-1>, R_A <N>, R_B < N> SW <N>, 200 are selectively activated in response to the frequency detection code R_CODE <1: N> output from the frequency detection section 21. That is, the plurality of resistor units 200 are divided into a first resistor unit group 201 and a second resistor unit group 202, and the first resistor unit selected by the frequency detection code R_CODE <1: N>. The resistance part of the group 201 and the resistance part of the second resistance part group 202 are simultaneously activated. Each resistor unit includes a plurality of resistors R_A <i> and R_B <i> and a switch SW <i>. The first resistor element R_A <i> and the second resistor element R_B <i> The ratio of the internal resistance value is determined based on the differential output terminals N1 and N2 according to the resistance value of. In the present embodiment, the plurality of resistor parts R_A <1>, R_B <1>, SW <1>, ..., R_A <N-1>, R_B <N-1>, SW <N-1>, and R_A <N > · R_B <N> · SW <N>, 200 all have the same resistance value, but the internal resistance value ratio is different depending on the resistance value of the internal resistance element. The amplification gain of the first differential amplifier 22 is determined according to the ratio of the internal resistance value. When the frequency band of the input signal IN is changed, the internal resistance is determined by the frequency detection code R_CODE <1: N>. Since the value ratio can be changed, flexibility in changing the frequency band can be obtained.

N R_A (N) R_B (N) Freq. 3 dB [GHz] Zero dB Freq. [GHz] One 100 3900 2.70 4.66 2 200 3800 2.76 4.57 3 300 3700 2.82 4.48 4 400 3600 2.88 4.39 5 500 3500 2.94 4.29 6 600 3400 3.00 4.18 7 700 3300 3.07 4.07 8 800 3200 3.14 3.96 9 900 3100 3.21 3.85 10 1000 3000 3.29 3.72 11 1100 2900 3.36 3.59 12 1200 2800 3.45 3.45 13 1300 2700 3.53 3.30 14 1400 2600 3.62 3.13 15 1500 2500 3.72 2.95 16 1600 2400 3.82 2.75 17 1700 2300 3.92 2.52 18 1800 2200 4.03 2.26 19 1900 2100 4.15 1.94 20 2000 2000 4.27 1.46

Table 1 shows the expected bandwidth according to the internal resistance ratio.

Referring to Table 1, when the resistance value of the resistor unit is 4KΩ, the ratio of the internal resistance value and the bandwidth according to the resistance value of the resistance element are shown.

For reference, in the present embodiment, the ratio of the internal resistance value of the resistance portion of the first resistance portion group 201 and the resistance portion of the second resistance portion group 202 activated by the frequency detection code R_CODE <1: N>. The internal operation is explained assuming that is the same. However, the first resistor group 201 and the second resistor group 202 are controlled through the respective frequency detection codes, or the resistor and the second resistor group of the first resistor group 201 are activated at the same time. The resistance of 202 may be arranged to have different internal resistance ratios, thereby controlling the duty ratio of the differential output signals OUT1 and OUT1B. In addition, the first differential amplifier 22 is configured to determine the input signal IN based on the reference voltage VREF, but when the input signal IN is applied in a differential form, the first differential amplifier 22 Differential inputs MN1 and MN2 may be buffered by receiving the differential input signal IN.

In the above, the specific description was made according to the embodiment of the present invention. Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

For example, although not directly related to the technical spirit of the present invention, in order to explain the present invention in more detail, an embodiment including an additional configuration may be illustrated. In addition, the configuration of an active high or an active low for indicating an activation state of a signal and a circuit may vary according to embodiments. In addition, the configuration of the transistor may be changed as necessary to implement the same function. That is, the configurations of the PMOS transistor and the NMOS transistor may be replaced with each other, and may be implemented using various transistors as necessary. Such a change in the circuit is too many cases, and the change can be easily inferred by a person skilled in the art, so the enumeration thereof will be omitted.

1 is a block diagram of an input buffer of a semiconductor device of the prior art.

2 is a configuration diagram of an input buffer of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

22: first differential amplifier

23: second differential amplifier

200: a plurality of resistance parts

201: first resistance group

202: second resistance unit group

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (4)

A frequency detector for detecting a frequency of an input signal; And A first differential amplification for outputting a differential output signal corresponding to the input signal by including a plurality of resistors selectively activated according to a detection result of the frequency detector and adjusting amplification gain according to an internal resistance value ratio of the activated resistors; part An input buffer of a semiconductor device having a. The method of claim 1, And a second differential amplifier for amplifying and outputting the differential output signal. The method according to claim 1 or 2, Each of the plurality of resistors, An input buffer of a semiconductor device having a plurality of resistance elements, the internal resistance value ratio is determined according to the resistance value of the provided resistance element. The method according to claim 1 or 2, The plurality of resistors, An input buffer of a semiconductor device having the same resistance value as each other, wherein each resistor unit includes a plurality of resistance elements to determine an internal resistance value ratio according to the resistance value of the resistance element.
KR1020090083769A 2009-09-07 2009-09-07 Input buffer for semiconductor apparatus KR20110026049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090083769A KR20110026049A (en) 2009-09-07 2009-09-07 Input buffer for semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090083769A KR20110026049A (en) 2009-09-07 2009-09-07 Input buffer for semiconductor apparatus

Publications (1)

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KR20110026049A true KR20110026049A (en) 2011-03-15

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