KR20100065992A - Layout for semiconductor device - Google Patents

Layout for semiconductor device Download PDF

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Publication number
KR20100065992A
KR20100065992A KR1020080124604A KR20080124604A KR20100065992A KR 20100065992 A KR20100065992 A KR 20100065992A KR 1020080124604 A KR1020080124604 A KR 1020080124604A KR 20080124604 A KR20080124604 A KR 20080124604A KR 20100065992 A KR20100065992 A KR 20100065992A
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KR
South Korea
Prior art keywords
region
transistors
gate
transistor
drain
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Application number
KR1020080124604A
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Korean (ko)
Inventor
서광유
Original Assignee
주식회사 동부하이텍
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Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080124604A priority Critical patent/KR20100065992A/en
Publication of KR20100065992A publication Critical patent/KR20100065992A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout of a semiconductor device, the layout of first and second transistors of a semiconductor device comprising a gate region, a drift region, a drain region and a source region in the drift region, wherein the first and second transistors Is arranged in a vertical matching structure in a vertical direction so as to face each other with respect to the gate area. Therefore, it is possible to prevent the carrier penetration phenomenon occurring between the two transistors due to the change in the channel length as well as the channel width of the transistor.

Description

Layout of Semiconductor Device {LAYOUT FOR SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a layout of a semiconductor device capable of preventing carrier penetration between transistors.

The circuits used in driving LSIs for flat panel displays such as LCDs, PDPs and OLEDs, automotive LSIs, OA and peripheral LSIs, and motor-driven LSIs, which have recently expanded the market, integrate high voltage devices and low voltage devices in one chip. have. Such a circuit is called a high voltage integrated circuit, and in order to design a high voltage integrated circuit, a model for a high voltage MOS device as well as a low voltage CMOS circuit is required.

1 illustrates a layout of a general high voltage semiconductor device, and FIG. 2 is a cross-sectional view illustrating the high voltage semiconductor device of FIG. 1.

1 and 2, the transistors 70 and 80 of the semiconductor device include a gate region 40, a drain region 60a and a source region 60b in the drift region 50, each of The region is in contact with the metals connected to the circuit via at least one contact 12, 14, 16 based on a design rule.

After defining the active regions on the semiconductor substrate 10 of FIG. 2, a shallow trench process (STI) 36 formed to isolate the active regions, the gate electrode 40, the gate insulating layer 38, and both sides of the gate electrode are formed. Transistors including sidewall spacers 42 formed in the wall are horizontally arranged in parallel and compare matching characteristics between transistors.

In the high voltage transistor, N-drift or P-drift process is performed according to the transistor type to increase the operating voltage.The rapid thermal annealing (RTA) process and the shallow trench process (STI) surface energy are performed. Carrier diffusivity varies according to the state, and carrier penetration occurs between the two transistors 70 and 80 (A).

Here, the two transistors 70 and 80 are used to characterize the difference between the values of the current Id and the voltage Vt, and the N-drift or P-drift region increases as the channel width W of the transistor increases. In addition, the transistor 50 becomes large in proportion to the channel width W. In the high voltage transistor, since the operating voltage is large, interference occurs between the two transistors 70 and 80, resulting in poor transistor characteristics.

3 is a graph showing the overall matching tendency according to the size by calculating the matching between transistors of each size having a plurality of transistor sizes. Specifically, it can be seen that the slope is changed as the channel width W is changed in the NMOS of 25V in the 0.18 μm process. That is, the match characteristics of the two transistors vary depending on the channel width W, and as the channel width W increases, the match characteristic worsens.

An object of the present invention is to provide a layout of a semiconductor device capable of preventing carrier penetration between two transistors.

The layout of the semiconductor device according to the embodiment of the present invention for achieving the above object is in the layout of the first and second transistors of the semiconductor device including a gate region, a drift region, a drain region and a source region in the drift region. The first and second transistors may be arranged in a vertical matching structure in a vertical direction so as to face each other with respect to the gate region.

The layout of a semiconductor device according to an embodiment of the present invention has the following effects.

By arranging transistors to be vertically symmetrical about the gate region, carrier penetration due to changes in channel length (L) and channel width (W) can be reduced to a minimum without changing process conditions, and all transistor types (NMOS, PMOS) ) And a transistor structure (symmetric, metric) can be applied to both.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

4 is a diagram illustrating a layout of a high voltage transistor according to the present invention.

FIG. 4 illustrates a method in which a carrier penetration phenomenon occurs according to a change in a channel width (W) and a channel length (L) of a transistor in a symmetrical structure of a high voltage transistor, thereby minimizing the actual transistor mismatching value of the channel width ( It is a matching structure arranged so as not to affect the change of W) and channel length (L).

Specifically, the transistors 170 and 180 of the semiconductor device include the gate region 140, the drain region 160a and the source region 160b in the drift region 150, and each region has a design rule. contacting metals connected to the circuit via at least one contact 112, 114, 116 on the basis of a rule).

In addition, a shallow trench process (STI) is formed on the semiconductor substrate to define the active regions and to isolate the active regions.

The gate region 140 is connected to a gate terminal (not shown) through the gate contact hole 116, and the drain region 160a is connected to a drain terminal (not shown) through the drain contact hole 114. In the source region 160b, a source terminal (not shown) is connected through the source contact hole 112.

In the high voltage transistor, in order to increase the operating voltage, an N-drift or P-drift process is performed according to the type of the transistor. In other words, an N-drift region or a P-type impurity is implanted by implanting N-type impurities into an active region of a semiconductor substrate. To form a P-drift region.

In this case, when the channel width W of the transistors 170 and 180 increases, the drift region 150 also increases in the vertical axis direction I, which is the channel width W direction, according to a design rule. It grows in proportion. Therefore, when the two transistors 170 and 180 are arranged in the horizontal direction as in the related art, carrier penetration between the two transistors 170 and 180 may occur due to an increase in the vertical axis direction I of the drift region 150. By arranging the two transistors 170 and 180 in a vertical matching structure in a vertical direction so as to face each other with respect to the gate contact hole 116 of the gate region 140, the transistors 170 and 180 become larger even if the channel width W becomes large. This does not affect the carrier penetration between the two.

In addition, even if the size of the channel length L of the transistors 170 and 180 is changed, the direction of the channel length L of the gate region 140 becomes long, and the drift region 150 between the two transistors 170 and 180 is increased. The horizontal axis direction J which is the channel length direction of is fixed and does not change. Therefore, the carrier penetration phenomenon occurring between the two transistors 170 and 180 with respect to the change in the channel length L as well as the channel width W can be prevented.

The horizontal axis direction J of the drift region 150 is formed to be fixed at a width of 4 μm to 6 μm.

Since the matching structure of the transistors 170 and 180 of the symmetric structure has the same source and drain patterns, if any one is designated as a source according to the surrounding circuit form, the opposite side becomes a drain. In FIG. 4, a source is arbitrarily designated as the right region of the gate region and a drain is designated as the left region of the gate.

FIG. 5 is a view routed with a metal pickup of a transistor matching structure with a symmetric structure according to FIG. 4.

Referring to FIG. 5, the two transistors 170 and 180 of the vertical matching structure have a symmetrical structure in which the source and drain regions 160a and 160b and the drift region 150 are symmetrical to each other.

The gate contact holes 116 of the gate regions 140 of the two transistors 170 and 180 are formed to face each other, and the common gate terminal 146 is the gate contact hole 116 of the two transistors 170 and 180. ) Are connected to each other in common.

The drain region 160a of the first transistor 170 is connected to the first drain terminal 140 through the drain contact hole 114, and the drain contact hole 114 is connected to the drain region 160a of the second transistor 180. The first and second transistors 170 and 180 are respectively driven by being connected to the second drain terminal 142 through.

The first and second transistors 170 may be formed through the source contact hole 112 of the source region 160b of the first transistor 170 and the source contact hole 112 of the source region 160b of the second transistor 180. The source region 160b of 180 is connected to the common source terminal 144 to commonly connect the source regions 160b of the first and second transistors 170 and 180.

The common source terminal 144 for commonly connecting the source regions 160b of the first and second transistors 170 and 180 is formed to overlap the common gate terminal 146 in a different layer.

As such, by forming the common gate terminal 146 and the common source terminal 144 connecting the first and second transistors 170 and 180 in common, the process may be simplified and the semiconductor device area may be minimized.

In the metal pickup of the matching structure, the size of the routing area of the metal terminals between the two transistors 170 and 180 is the same, thereby making the size of the voltage drop generated in the metal resistance the same. For example, if the area of the first drain terminal 140 and the second drain terminal 142 is changed, the resistance is changed according to the area of the metal, so that the resistances of the two transistors 170 and 180 are changed, so that the matching characteristics are different. Is lowered. Therefore, the area of each terminal of the two transistors 170 and 180 is formed to be the same to improve matching characteristics.

As described above, the vertical matching structure in which the two transistors 170 and 180 are arranged to be symmetrical in the vertical direction to face each other with respect to the gate region 140 is not only a symmetric structure but also a transistor having an symmetric (asymmetric) structure as shown in FIG. 6. The same applies to the matching structure.

In the transistor matching structure having the asymmetric structure of FIG. 6, only one of the N-drift region and the P-drift region exists, and the remaining structure is the same as that of FIG. 5, and thus will be omitted.

As described above, the matching structure of the transistors 170 and 180 arranged so as to be vertically symmetric about the gate region 140 minimizes carrier penetration caused by the change in the channel length L and the channel width W without changing the process conditions. It can be reduced to all transistor types (NMOS, PMOS) and transistor structure (symmetric, assisted).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a diagram illustrating a layout of a general high voltage semiconductor device.

FIG. 2 is a cross-sectional view illustrating the high voltage semiconductor device of FIG. 1.

3 is a graph showing the overall matching tendency according to the size having a plurality of transistor sizes and calculating matching between transistors for each size.

4 is a diagram illustrating a layout of a high voltage transistor according to the present invention.

5 is a view routed with a metal pickup of the transistor matching structure with the symmetric structure according to FIG. 4.

6 is a view routed with a metal pickup of a transistor matching structure with an asymmetric structure according to FIG. 4.

<Description of Symbols for Main Parts of Drawings>

112, 114, 116: contact hole 140: gate area

150: drift region 160a, 160b: source, drain region

170: first transistor 180: second transistor

Claims (6)

In the layout of the first and second transistors of the semiconductor device comprising a gate region, a drift region, a drain region and a source region in the drift region, And the first and second transistors are arranged in a vertical matching structure in a vertical direction so as to face each other with respect to the gate region. The method of claim 1, The drifted region is a layout of a semiconductor device, characterized in that the transverse width in the channel length direction of the transistor is fixed to a width of 4㎛ 6㎛. The method of claim 1, And the first and second transistors are symmetrically formed with a drift region around the gate region. The method of claim 1, And the first and second transistors are asymmetrically formed with a drift region around the gate region. The method of claim 1, A gate contact hole formed in the gate region; A drain contact hole formed in the drain region; And a source contact hole formed in the source region. The method of claim 5, A common gate terminal for commonly connecting the gate regions of the first and second transistors through the gate contact holes of the first and second transistors; A first drain terminal connected to the drain region of the first transistor through the drain contact hole of the first transistor; A second drain terminal connected to the drain region of the second transistor through the drain contact hole of the second transistor; And a common source terminal for connecting the source regions of the first and second transistors in common through the source contact holes of the first and second transistors.
KR1020080124604A 2008-12-09 2008-12-09 Layout for semiconductor device KR20100065992A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110211987A (en) * 2018-12-12 2019-09-06 友达光电股份有限公司 Light-emitting-diode panel
CN110337724A (en) * 2017-02-20 2019-10-15 斯兰纳亚洲有限公司 Connection arrangement for integrated horizontal proliferation field effect transistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110337724A (en) * 2017-02-20 2019-10-15 斯兰纳亚洲有限公司 Connection arrangement for integrated horizontal proliferation field effect transistor
CN110337724B (en) * 2017-02-20 2023-11-07 斯兰纳亚洲有限公司 Connection arrangement for integrated laterally diffused field effect transistors
CN110211987A (en) * 2018-12-12 2019-09-06 友达光电股份有限公司 Light-emitting-diode panel
CN110211987B (en) * 2018-12-12 2021-08-06 友达光电股份有限公司 Light emitting diode panel

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