KR20090106153A - Method for manufacturing semiconductor device with vertical gate - Google Patents

Abstract

PURPOSE: A manufacturing method of a semiconductor device including a vertical gate is provided to simplify a process by excluding a separate mask. CONSTITUTION: A plurality of active pillars(62) having a recessed sidewall is formed on a substrate(61). A conductive film is formed on a whole surface including the active pillar. The conductive film is etched by using a protecting film in which carbon component is contained as an etching barrier. A vertical gate(69) surrounds the recessed sidewall of the active pillar. A buried type bit line(70A,70B) is formed by injecting an ion on the substrate. A sacrificial pattern covers the sidewall of the vertical gate, the protecting film, and the active pillar.

Description

Method of manufacturing semiconductor device having vertical gates {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH VERTICAL GATE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a vertical gate (VG).

Recently, a semiconductor device having a sub 50 nm or less class is required to improve integration. In the case of a semiconductor device having a planar channel or a recess channel, scaling to less than 40 nm is very difficult. There is. Therefore, there is a demand for a semiconductor device capable of improving the integration degree by 1.5 to 2 times in the same scaling. Accordingly, a semiconductor device having a vertical gate has been proposed.

The vertical gate is a round type gate that wraps around an active pillar extending vertically on a substrate, and a channel is formed in a vertical direction by the vertical gate.

A memory device having such a vertical gate forms a buried bit line (BBL) through ion implantation, and performs a trench process to separate neighboring buried bit lines.

1A is a perspective view of a semiconductor device having a vertical gate according to the related art, and FIG. 1B is a cross-sectional view taken along the line X-X 'of FIG. 1A.

1A and 1B, an active pillar 12 having a recessed sidewall is formed on the substrate 11, and a vertical gate 14 is formed surrounding the recessed sidewall of the active pillar 12. . In the substrate 11, buried bit lines 15A and 15B by ion implantation are formed. The buried bit lines 15A and 15B are separated from each other by the trench 16. A gate insulating layer 17 is provided between the vertical gate 14 and the recessed sidewall of the active pillar 12, and a protective layer 13 is provided on the active pillar 12 to protect the active pillar when forming the trench. . The protective film 13 includes a nitride film.

In the above-described conventional technology, the buried bit lines 15A and 15B are formed through ion implantation, and the adjacent buried bit lines 15A and 15B are separated through the trench 16. The mask PR is used to form the trench 16. This mask is also known as a BBL mask.

1C is a plan view of a BBL mask according to the prior art, wherein the BBL mask for forming the trench 16 is a line pattern in the bit line direction.

However, the related art requires not only complicated steps such as using a BBL mask to separate neighboring buried bit lines 15A and 15B, but also due to misalignment which is inevitably involved in the BBL mask process. There is a problem that is not easy to separate.

In addition, in the related art, since the protective film 13 is a nitride film, there is a problem that the active pillar 12 is damaged due to not having high selectivity during the etching process for forming the trench.

The present invention has been made to solve the above problems of the prior art, a vertical gate that can simplify the complexity of the etching process for separation of the buried bit line, and can prevent the problem due to misalignment during the BBL mask process at the source It is an object of the present invention to provide a method for manufacturing a semiconductor device having a.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device having a vertical gate that can prevent the active pillar from being damaged during the trench process for separation of the buried bit line.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of active pillars having a sidewall recessed on the substrate; Forming a conductive film on the entire surface including the active pillars; Etching the conductive layer using the protective film containing the carbon component as an etch barrier to form a vertical gate surrounding the recessed sidewall of the active pillar; Forming a buried bit line through ion implantation in the substrate; Forming a sacrificial layer pattern covering sidewalls of the active pillar, the passivation layer, and the vertical gate; And forming a trench separating the buried bit line by etching the substrate to be self-aligned with the sacrificial layer pattern on the sidewall of the active pillar. Preferably, the etching of the substrate for forming the trench is characterized in that the progress to the blanket etch (Blanket etch). Preferably, the protective film is characterized in that it comprises a material containing silicon (Si) and carbon (Carbon), the protective film is characterized in that it comprises any one selected from SiC, SiCN or SiCO, the protective film Silver is characterized in that it comprises any one selected from carbides, carbides or carbide oxides.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming a plurality of active pillars having a recessed sidewall by etching the substrate with an etching barrier at least a protective film containing a carbon component; Forming a vertical gate surrounding the recessed sidewall of the active pillar; Forming a buried bit line in the substrate; Forming a sacrificial layer pattern covering sidewalls of the active pillar, the passivation layer, and the vertical gate; And forming a trench separating the buried bit line by etching the substrate to be self-aligned with the sacrificial layer pattern on the sidewall of the active pillar. Preferably, the etching of the substrate for forming the trench is characterized in that the progress to the blanket etch (Blanket etch). Preferably, the protective film is formed of a laminated structure of a nitride film and a carbon-containing film, the carbon-containing film comprises a material containing silicon (Si) and carbon (Carbon), the carbon-containing film is any selected from SiC, SiCN or SiCO Characterized by including one. The sacrificial film pattern may include a nitride film.

In the present invention described above, since the trench process for separating the buried bit line is a blanket etching and a self-aligning etching method is applied, a separate mask does not need to be used, thereby simplifying the process and not considering misalignment. In addition, since the protective film is a material having high selectivity, the active pillars are not damaged.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

FIG. 2A is a perspective view of a semiconductor device having a vertical gate in accordance with an embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along the X-X 'direction and the Y-Y' direction of FIG. 2A.

2A and 2B, a plurality of active pillars 22 having recessed sidewalls are formed on the substrate 21. The active pillar 22 is composed of a neck pillar 22B and a head pillar 22A, and a side wall recessed by the neck pillar 22B is provided. A pillar spacer 24 may be provided on the sidewall of the head pillar 22A of the active pillar 22. A gate insulating film 25 is formed on the recessed sidewall of the active pillar 22, that is, on the surface of the neck pillar 22B and the substrate 21. Vertical gates 27 are formed which surround the recessed sidewalls of the active pillar 22. The buried bit lines 28A and 28B are formed in the board | substrate 21, and the buried bit lines 28A and 28B are isolate | separated by the trench 30. As shown in FIG.

The semiconductor device as described above may be implemented by the following three methods.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a vertical gate according to a first embodiment of the present invention. In the Y-Y 'direction, the spacing between neighboring active pillars is narrow, and in the X-X' direction, the spacing between neighboring active pillars is wide.

As shown in FIG. 3A, a plurality of active pillars 22 having recessed sidewalls are formed on the substrate 21.

The active pillar 22 is a cylindrical pillar structure arranged in a matrix form. The active pillar 22 is composed of a neck pillar 22B and a head pillar 22A, and the recessed sidewall is provided by the neck pillar 22B. The neck pillar 22B is formed by an isotropic etching process, and isotropic etching is also called a pillar trimming process. By isotropic etching, the sidewalls are recessed to about 150 Å to form the neck pillars 22B. The active pillar 22 may be doped with impurities to function as a channel region.

The passivation layer 23 is formed on the active pillar 22. The protective layer 23 may be formed of a material having high selectivity not only during the etching process for forming the active pillar 22 but also during the subsequent trench process.

The passivation layer 23 includes a carbon-containing layer, and the carbon-containing layer includes a material containing silicon (Si) and carbon. Preferably, the protective film 23 includes carbide, carbide nitride or carbide oxide. More preferably, the protective film 23 includes any one of SiC, SiCN or SiCO. The carbon-containing film has higher selectivity than the nitride film when etching the silicon substrate.

The substrate 21 includes a silicon substrate. In addition, the substrate 21 may include a silicon germanium substrate.

In order to prevent the side wall of the head pillar 22A from being damaged, an etching process for forming the neck pillar 22B may be performed after the pillar spacer 24 is formed on the side wall of the head pillar 22A. The pillar spacers 24 are also formed on the sidewalls of the protective film 23. The pillar spacer 24 is formed by depositing a silicon nitride film and then etching back.

As shown in FIG. 3B, a gate insulating film 25 is formed on the exposed surfaces of the neck pillars 22B and the substrate 21. The gate insulating film 25 may include a silicon oxide film, and the gate insulating film 25 may be formed to have a thickness of 50 kHz by a deposition process or an oxidation process. Preferably, it is formed by an oxidation process. Since the sidewalls of the head pillars 22A are covered by the pillar spacers 24, no gate insulating film is formed.

The conductive film 26 is formed on the entire surface of the structure in which the gate insulating film 25 is formed. At this time, the conductive film 27 is formed to have a thin thickness (150 to 300 micrometers), and at least the thickness filling the recessed sidewall of the neck pillar 22B may be satisfied. That is, since the recess amount of the active pillar is 150 kV, the conductive film 27 may be thicker than 150 kPa. Therefore, since it is not necessary to deposit very thick more than necessary, what is necessary is just to satisfy the thickness of 300 GPa or less.

The conductive film 26 includes a polysilicon film deposited by chemical vapor deposition (CVD). The polysilicon film may include N-type impurities such as phosphorus (Ph), arsenic (As), or P-type impurities such as boron (Boron).

As shown in FIG. 3C, the conductive layer 26 is etched back to form a vertical gate 27 that surrounds the recessed sidewall of the active pillar 22. During the etch back process for forming the vertical gate 27, the protective layer 23 may remain with a constant thickness because of the high selectivity.

As shown in FIG. 3D, ion implantation is performed on the substrate 21 to form an impurity region 28 to be used as a buried bit line. The impurity region 28 also serves as a source (drain) region of the transistor. Therefore, the impurity region 28 may be ion implanted with N-type impurities or P-type impurities. N-type impurities include phosphorus (P) or arsenic (As), and P-type impurities include boron.

As shown in FIG. 3E, a sacrificial layer 29 is formed on the entire surface. The sacrificial film 29 includes a nitride film and is deposited to a thickness of 150 to 300 Å. The sacrificial layer 29 is formed to cover the upper portion of the passivation layer 23 while filling the active pillars 22 in the Y-Y 'direction. In the X-X 'direction, the gap between the active pillars 22 is wide so as not to fill the gaps between the active pillars. Since the gap between the active pillars in the Y-Y 'direction is narrow, the sacrificial layer 29 fills the gaps between the active pillars.

As shown in FIG. 3F, the trench 30 process is performed to form the buried bit lines 28A and 28B.

The first embodiment omits the mask (formerly BBL mask) process for the trench process and forms the trench 30 by a blanket etch method. At this time, the protective film 23 serves as an etching barrier. Preferably, etching is performed using a high selectivity ratio between the protective film 23 and the substrate 21. That is, the carbon-containing film used as the protective film 23 has a high selectivity when etching the substrate 21 which is a silicon substrate. Thus, when the trench 21 is formed by etching the substrate 21, the substrate 21 serves as an etching barrier.

In detail, the sacrificial layer 29 on the surface of the substrate 21 is etched by the blanket etching, and then the exposed substrate 21 is etched to a predetermined depth to form the trench 30. Since the blanket etching is a straight etching, both the sacrificial films on the upper surface of the passivation layer 23 and the surface of the substrate 21 are etched in the X-X 'direction, and the sacrificial layer pattern 29A remains only on the sidewalls of the active pillar and the second passivation layer. On the other hand, in the Y-Y 'direction, the sacrificial film pattern 29B remains in the form of gap filling between the active pillars. This is because in the Y-Y 'direction, the sacrificial layer is thickly interposed between the active pillars, so that the amount of etching of the sacrificial layer is small. Therefore, the trench 30 is not formed in the Y-Y 'direction. The sacrificial layer patterns 29A and 29B have a partial mesh structure surrounding all sidewalls of the active pillars.

In the XX 'direction, the substrate 21 is self-aligned etched by the sacrificial film pattern 29A to form the trench 30, and the etching is prevented by the sacrificial film pattern 29B in the YY' direction. do. The sacrificial layer patterns 29A and 29B cover sidewalls of the active pillar, the passivation layer, and the vertical gate.

As described above, the etching process for forming the trench 30 is a blanket etching without using a separate mask and is self-aligned with the passivation layer 23 and the sacrificial layer patterns 29A and 29B to etch the substrate 21. Self-aligned etching method.

By the trench 30, the impurity regions 28 become buried bit lines 28A and 28B, and neighboring buried bit lines 28A and 28B are separated from each other by the trench 30. The trench 30 is formed deeper than the buried bit lines 28A and 28B to separate between neighboring buried bit lines.

As shown in FIG. 3G, the remaining sacrificial films 29A and 29B are removed. The sacrificial films 29A and 29B are removed through a plasma strip. Since the sacrificial films 29A and 29B are nitride films, the sacrificial films 29A and 29B are removed through a strip using CF ₄ plasma. When removing the sacrificial layers 29A and 29B, the pillar spacers 24 may be partially removed.

The protective film 23 can also be removed. The passivation layer 23 is removed through a plasma strip. Since the protective film 23 contains a carbon component, it is removed through a strip using oxygen plasma.

According to the first embodiment described above, since the trench 30 process for separating the buried bit lines 28A and 28B is a blanket etching and a self-aligned etching method is applied, a separate mask does not need to be used, thereby simplifying the process. The misalignment does not need to be considered. In addition, since the protective film is a material having high selectivity, the active pillars are not damaged.

4A through 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a vertical gate in accordance with a second embodiment of the present invention. In the Y-Y 'direction, the spacing between neighboring active pillars is narrow, and in the X-X' direction, the spacing between neighboring active pillars is wide.

As shown in FIG. 4A, a plurality of active pillars 42 having recessed sidewalls are formed on the substrate 41.

The active pillar 42 is a cylindrical pillar structure arranged in a matrix form. The active pillar 42 is composed of a neck pillar 42B and a head pillar 42A, and the recessed sidewall is provided by the neck pillar 42B.

The active pillar 42 is formed through several etching processes using the first and second passivation layers 43 and 44. First, the head pillars 42A are formed by anisotropically etching the substrate 41 using the first and second passivation layers 43 and 44 as etch barriers, and further, anisotropic etching and isotropic etching are sequentially performed to form a neck pillar ( 42B). By isotropic etching, the neck pillar 42B is formed with a recessed sidewall under the head pillar 42A.

The substrate 41 includes a silicon substrate. Since the substrate 41 is a silicon substrate, the anisotropic etching proceeds by using Cl ₂ or HBr gas alone, or by using a mixed gas of Cl ₂ and HBr gas. Isotropic etching uses wet etching or chemical dry etching (CDE). Wet etching may use potassium hydroxide (KOH) solution or hydrochloric acid (HCl) solution. Chemical dry etching may be performed using a mixed gas of Cl ₂ , HBr, and SF ₆ . SF ₆ gas is known to isotropically etch silicon substrates. The isotropic etching process is called a pillar trimming process, and the sidewalls are recessed by about 150 microseconds by the isotropic etching to form the neck pillar 42B.

On the other hand, in order to prevent damage to the side wall of the head pillar 42A, after forming the pillar spacer 45 on the side wall of the head pillar 42A, an etching process for forming the neck pillar 42B may be performed. The pillar spacers 45 are also formed on sidewalls of the first and first passivation layers 43 and 44. The pillar spacer 45 is formed by depositing a silicon nitride film and then etching back.

The first passivation layer 43 and the second passivation layer 44 serve as an etching barrier in addition to the protection layer for protecting the active pillar 42 in a subsequent etching process. Accordingly, the first protective layer 43 and the second protective layer 44 may be formed of a material having high selectivity not only during the etching process for forming the active pillar 42 but also during the subsequent trench process. The first protective film 43 may be formed of a silicon nitride film (Si ₃ N ₄ ), and may have a thickness of 2000 GPa.

The second passivation layer 44 may be formed of a material having high selectivity during subsequent trench etching. In addition, the second passivation layer 44 preferably has a higher selectivity than the first passivation layer 43 during subsequent trench etching. Only the first protective film 43, which is a nitride film material, is difficult to obtain high selectivity in the subsequent trench process, and thus, the active pillars are easily attacked.

The second passivation layer 44 includes a carbon-containing film and also includes a material containing silicon (Si) and carbon. Preferably, the second passivation layer 44 includes carbide, carbide nitride or carbide oxide. More preferably, the second protective film 44 includes any one of SiC, SiCN or SiCO.

Although not shown, a buffer layer may be further provided between the first passivation layer 43 and the head pillar 42A to relieve stress caused by the first passivation layer 43. The buffer film includes a silicon oxide film.

As shown in FIG. 4B, a gate insulating film 46 is formed on the exposed surfaces of the neck pillars 42B and the substrate 41. The gate insulating film 46 may include a silicon oxide film, and the gate insulating film 46 may be formed to have a thickness of 50 μs by a deposition process or an oxidation process. Preferably, it is formed by an oxidation process. Since the sidewalls of the head pillars 42A are covered by the pillar spacers 45, no gate insulating film is formed.

The conductive film 47 is formed on the entire surface of the structure in which the gate insulating film 46 is formed. At this time, the conductive film 47 is formed to have a thin thickness (150 to 300 mW), and at least the thickness filling the recessed sidewall of the neck pillar 42B is satisfied. That is, since the recess amount of the active pillar is 150 kV, the conductive film 47 may be thicker than 150 kPa. Therefore, since it is not necessary to deposit very thick more than necessary, what is necessary is just to satisfy the thickness of 300 GPa or less.

The conductive film 47 includes a polysilicon film deposited by chemical vapor deposition (CVD). The polysilicon film may include N-type impurities such as phosphorus (Ph), arsenic (As), or P-type impurities such as boron (Boron).

As shown in FIG. 4C, the conductive film 47 is etched back to form a vertical gate 48 that surrounds the recessed sidewall of the active pillar 42. In the etch back process for forming the vertical gate 48, the second passivation layer 44 remains with a constant thickness because of the high selectivity.

As shown in FIG. 4D, ion implantation is performed on the substrate 41 to form an impurity region 49 to be used as a buried bit line. The impurity region 49 also serves as a source (drain) region of the transistor. Therefore, the impurity region 49 may be ion implanted with N-type impurities or P-type impurities. N-type impurities include phosphorus (P) or arsenic (As), and P-type impurities include boron.

As shown in FIG. 4E, a sacrificial layer 50 is formed on the entire surface. The sacrificial film 50 includes a nitride film and is deposited to a thickness of 150 to 300 Å. The sacrificial layer 31 is formed to cover the upper portion of the second passivation layer 44 while filling the active pillars 42 in the Y-Y 'direction. In the X-X 'direction, the gap between the active pillars 42 is wide so as not to fill between the active pillars. Since the gap between the active pillars in the Y-Y 'direction is narrow, the sacrificial layer 31 fills the gaps between the active pillars.

As shown in FIG. 4F, the trench 51 process for forming the buried bit lines 49A and 49B is performed.

The second embodiment omits the mask (formerly BBL mask) process for the trench process and forms the trench 51 by a blanket etch method. In this case, the second passivation layer 44 serves as an etching barrier. Preferably, etching is performed using a high selectivity ratio between the second protective film 44 and the substrate 41. That is, the carbon-containing film used as the second protective film 44 has a high selectivity when etching the substrate 41 which is a silicon substrate. Therefore, when the substrate 41 is etched to form the trench 42, the substrate 41 serves as an etching barrier.

In detail, the sacrificial layer 50 on the surface of the substrate 41 is etched by the blanket etching, and then the exposed substrate 41 is etched to a predetermined depth to form the trench 51. Since the blanket etching is a straight etching, in the X-X 'direction, both the top surface of the second passivation layer 44 and the sacrificial layer on the surface of the substrate 41 are etched, and the sacrificial layer 50A remains only on the sidewalls of the active pillar and the second passivation layer. On the other hand, in the Y-Y 'direction, the sacrificial film 50B remains in the form of gap filling between the active pillars. This is because in the Y-Y 'direction, the sacrificial layer is thickly interposed between the active pillars, so that the amount of etching of the sacrificial layer is small.

Therefore, the trench 51 is not formed in the Y-Y 'direction. The sacrificial layer patterns 50A and 50B have a partial mesh structure surrounding all sidewalls of the active pillars.

In the XX 'direction, the substrate 41 is self-aligned etched by the sacrificial film pattern 50A to form the trench 51, and the etching is prevented by the sacrificial film pattern 50B in the YY' direction. do. The sacrificial layer patterns 50A and 50B cover sidewalls of the active pillar, the passivation layer, and the vertical gate.

As described above, the etching process for forming the trench 51 is a blanket etching without using a separate mask and is self-aligned with the second passivation layer 44 and the sacrificial layer patterns 50A and 50B so that the substrate 41 is formed. It is a self-aligned etching method that is etched.

By the trench 51, the impurity regions 49 become buried bit lines 49A and 49B, and adjacent buried bit lines 49A and 49B are separated from each other by the trench 51. The trench 51 is formed deeper than the buried bit lines 49A and 49B to separate between neighboring buried bit lines.

As shown in FIG. 4G, after the remaining sacrificial films 50A and 50B are removed, the second protective film 44 is removed. The second passivation layer 44 and the sacrificial layers 50A and 50B are removed through a plasma strip.

Since the second protective film 44 contains a carbon component, the second protective film 44 is removed through a strip using oxygen plasma. Since the sacrificial films 50A and 50B are nitride films, the sacrificial films 50A and 50B are removed through a strip using CF ₄ plasma. When the sacrificial layers 50A and 50B are removed, some of the pillar spacers 45 may be removed. The first protective layer 43 serves to protect and insulate the active pillars from subsequent processes.

According to the second embodiment described above, since the trench process for separating the buried bit line is a blanket etching and a self-aligned etching method is applied, a separate mask does not need to be used, and thus the process is simplified and misalignment is not considered. In addition, since the second protective film is a material having high selectivity, the active pillars are not damaged.

5A through 5H are cross-sectional views illustrating a method of manufacturing a semiconductor device having a vertical gate in accordance with a third embodiment of the present invention.

As shown in FIG. 5A, a plurality of active pillars 62 having recessed sidewalls are formed on the substrate 61. In the Y-Y 'direction, the spacing between neighboring active pillars is narrow, and in the X-X' direction, the spacing between neighboring active pillars is wide.

The active pillar 62 is a cylindrical pillar structure arranged in a matrix form. The active pillar 62 is composed of a neck pillar 62B and a head pillar 62A, and the recessed sidewall is provided by the neck pillar 62B.

The active pillar 62 is formed through several etching processes using the first passivation layer 63. First, the head pillar 62A is formed by anisotropically etching the substrate 61 using the first passivation layer 63 as an etch barrier, and further, the neck pillar 62B is formed by sequentially performing anisotropic etching and isotropic etching. . By isotropic etching, the neck pillar 62B is formed with a recessed sidewall under the head pillar 62A.

The substrate 61 includes a silicon substrate. Since the substrate 61 is a silicon substrate, the anisotropic etching proceeds by using Cl ₂ or HBr gas alone or by using a mixed gas of Cl ₂ and HBr gas. Isotropic etching uses wet etching or chemical dry etching (CDE). Wet etching may use potassium hydroxide (KOH) solution or hydrochloric acid (HCl) solution. Chemical dry etching may be performed using a mixed gas of Cl ₂ , HBr, and SF ₆ . SF ₆ gas is known to isotropically etch silicon substrates. The isotropic etching process is called a pillar trimming process, and the sidewalls are recessed by about 150 microseconds by the isotropic etching to form the neck pillar 62B.

In order to prevent damage to the sidewall of the head pillar 62A, the pillar spacer 64 may be formed on the sidewall of the head pillar 62A, and then an etching process for forming the neck pillar 62B may be performed. The pillar spacers 64 are also formed on the sidewalls of the first passivation layer 63. The pillar spacer 64 is formed by etching back the nitride film. The pillar spacer 64 includes a silicon nitride film.

The first protective film 63 may be formed of a silicon nitride film (Si ₃ N ₄ ), and may have a thickness of 2000 GPa. Although not shown, a buffer layer may be further provided between the first passivation layer 63 and the head pillar 62A to relieve stress caused by the first passivation layer 63. . The buffer film includes a silicon oxide film (SiO ₂ ).

As shown in FIG. 5B, a gate insulating film 65 is formed on the exposed surfaces of the neck pillars 62B and the substrate 61. The gate insulating layer 65 may include a silicon oxide layer (SiO ₂ ), and may be formed to a thickness of 50 μs by a deposition process or an oxidation process. Preferably, the gate insulating film 65 is not formed because the sidewalls of the head pillars 62A are covered by the pillar spacers 64.

The conductive film 66 is formed on the entire surface of the structure in which the gate insulating film 65 is formed. At this time, the conductive film 66 is formed on the entire surface so as to gap-fill between the active pillars 62. The conductive film 66 includes a polysilicon film deposited by using chemical vapor deposition (CVD). The polysilicon film may include N-type impurities such as phosphorus (Ph), arsenic (As), or P-type impurities such as boron (Boron). Since the conductive film 66 later becomes a vertical gate, impurities may be adjusted according to the characteristics of the transistor.

The conductive layer 66 is partially etched back to expose the surface of the first passivation layer 63. The conductive film 66 may be left only by the height of the active pillar 62 by the partial etch back.

As shown in FIG. 5C, a vertical gate mask (VG Mask) process 68 is performed. The present invention further forms a second passivation layer 67 before proceeding with the vertical gate mask 68 process.

The second passivation layer 67 is a material having high selectivity in subsequent trench etching. The second protective film 67 includes a carbon containing film. The second passivation layer 67 may include a material containing silicon (Si) and carbon. Preferably, the second passivation layer 67 includes carbide, carbide nitride or carbide oxide. More preferably, the second protective film 67 includes any one of SiC, SiCN or SiCO. The second passivation layer 67 is formed to have a thickness of 100 to 500 Å, which is relatively thinner than the first passivation layer 63 but has a high selectivity in subsequent trench etching.

After the vertical gate mask 68 is formed on the second protective film 67 formed using the photoresist film, the second protective film 67 is etched using the vertical gate mask 68 as an etch barrier. The vertical gate mask 68 is a circular pattern in plan view. This is because the vertical gate has a round structure surrounding the sidewall of the neck pillar. The vertical gate mask 68 may be a circular pattern having a diameter of at least the sum of the active pillars 62 and the pillar spacers 64. That is, the vertical gate mask 68 is a circular pattern covering not only the active pillar 62 but also the pillar spacer 64.

As shown in FIG. 5D, the conductive layer 66 is etched using the vertical gate mask 68 as an etch barrier to form a vertical gate 69 that surrounds the recessed sidewall of the active pillar 62.

The photoresist used as the vertical gate mask 68 may not remain during the vertical gate 69 formation. Even so, the second protective film 67 has high selectivity and remains with a certain thickness.

As shown in FIG. 5E, ion implantation is performed on the substrate 61 to form an impurity region 70 to be used as a buried bit line. The impurity region 70 also acts as a source (or drain) region of the transistor. Therefore, the impurity region 70 may be ion implanted with N-type impurities or P-type impurities. N-type impurities include phosphorus (P) or arsenic (As), and P-type impurities include boron.

As shown in FIG. 5F, a sacrificial layer 71 is formed on the entire surface. The sacrificial film 71 includes a nitride film and is deposited to a thickness of 150 to 700 Å. The sacrificial layer 71 covers the upper portion of the first passivation layer 63 while filling the active pillars 62 in the Y-Y 'direction. In the X-X 'direction, the gap between the active pillars 62 is wide so as not to fill the gaps between the active pillars. Since the gap between the active pillars in the Y-Y 'direction is narrow, the sacrificial layer 71 fills the gaps between the active pillars.

As shown in FIG. 5G, a trench 72 process is performed to form buried bit lines 70A and 70B.

The third embodiment omits the mask (formerly BBL mask) process for the trench process and forms the trench 72 by the blanket etch method. In this case, the second passivation layer 67 serves as an etching barrier. Preferably, etching is performed using a high selectivity ratio between the second protective film 67 and the substrate 61. That is, the carbon-containing film used as the second protective film 67 has a high selectivity when etching the substrate 61 which is a silicon substrate. Thus, when the substrate 61 is etched to form the trench 72, the substrate 61 serves as an etching barrier.

In detail, the sacrificial layer 71 on the surface of the substrate 61 is etched by the blanket etching, and then the exposed substrate 61 is etched to a predetermined depth to form the trench 72. Since the blanket etching is a straight etching, both the sacrificial film on the upper surface of the first passivation layer and the surface of the substrate 61 are etched in the X-X 'direction, and the sacrificial layer 71A remains only on the sidewalls of the active pillar and the first passivation layer. On the other hand, in the Y-Y 'direction, the sacrificial film 71B remains in the form of gap filling between the active pillars. This is because in the Y-Y 'direction, the sacrificial layer is thickly interposed between the active pillars, so the etching amount of the sacrificial layer is small. Therefore, the trench 72 is not formed in the Y-Y 'direction.

Therefore, the trench 72 is not formed in the Y-Y 'direction. The sacrificial layer patterns 71A and 71B have a partial mesh structure surrounding all sidewalls of the active pillars.

In the XX 'direction, the self-aligned etching of the substrate 61 proceeds to form the trench 72 by the sacrificial film pattern 71A, and the etching is prevented by the sacrificial film pattern 71B in the YY' direction. do. The sacrificial layer patterns 71A and 71B cover sidewalls of the active pillar, the passivation layer, and the vertical gate.

As described above, the etching process for forming the trench 72 is a blanket etching without using a separate mask and is self-aligned with the second passivation layer 67 and the sacrificial layer patterns 71A and 71B so that the substrate 61 may be formed. It is a self-aligned etching method that is etched.

The trench 72 forms the impurity regions 70 as buried bit lines 70A and 70B, and the adjacent buried bit lines 70A and 70B are separated from each other by the trench 72. The trench 72 is formed deeper than the buried bit lines 70A and 70B to separate between neighboring buried bit lines.

As shown in FIG. 5H, after the remaining sacrificial films 71A and 71B are removed, the second protective film 67 is removed. The second passivation layer 67 and the sacrificial layers 71A and 71B are removed through a plasma strip.

Since the second protective film 67 contains a carbon component, the second protective film 67 is removed through a strip using oxygen plasma. Since the sacrificial films 71A and 71B are nitride films, the sacrificial films 71A and 71B are removed through a strip using CF ₄ plasma. When removing the sacrificial layers 71A and 71B, the pillar spacers 64 may be partially removed.

6 is a plan view illustrating a result after the trench process according to the first to third embodiments of the present invention.

Referring to FIG. 6, when the trenches 29, 51, and 72 are formed, the sacrificial layer pattern of the partial mesh structure on the sidewalls of the active pillars 22, 42, and 62 may surround the sidewalls of the active pillars 29A, 50A, and 71A. And embedded portions 29B, 50B, 71B between the active pillars. By the sacrificial layer pattern, etching is performed in a self-aligning manner.

The semiconductor device shown in the first to third embodiments described above has a cell architecture (minimum feature size) of 4.8F ² . Therefore, the unit cell is formed to have an area of 4.8F ² , and the transistors, bit lines, and word lines constituting the unit cell are located within this area. The 4.8F ² cell architecture can achieve 1.5 to ² times greater integration at the same scaling than the 8F ² or 6F ² cell architecture.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a perspective view of a semiconductor device having a vertical gate according to the prior art.

FIG. 1B is a cross-sectional view taken along the line X-X 'of FIG. 1A;

1C is a plan view of a BBL mask according to the prior art.

2A is a perspective view of a semiconductor device having a vertical gate according to a first embodiment of the present invention.

FIG. 2B is a sectional view taken along the line X-X 'and Y-Y' of FIG. 2A; FIG.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a vertical gate according to a first embodiment of the present invention.

4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a vertical gate in accordance with a second embodiment of the present invention.

5A through 5H are cross-sectional views illustrating a method of manufacturing a semiconductor device having vertical gates in accordance with a third embodiment of the present invention.

6 is a plan view showing the result after the trench process according to the first to third embodiments of the present invention.

* Explanation of symbols for the main parts of the drawings

41 substrate 42 active pillar

43: first protective film 44: second protective film

45: pillar spacer 46: gate insulating film

48: vertical gate 49A, 49B: buried bit line

51: trench

Claims (18)

Forming a plurality of active pillars having recessed sidewalls on the substrate; Forming a conductive film on the entire surface including the active pillars; Etching the conductive layer using the protective film containing the carbon component as an etch barrier to form a vertical gate surrounding the recessed sidewall of the active pillar; Forming a buried bit line through ion implantation in the substrate; Forming a sacrificial layer pattern covering sidewalls of the active pillar, the passivation layer, and the vertical gate; And Etching the substrate to self-align the sacrificial layer pattern on the sidewall of the active pillar to form a trench separating the buried bit line A semiconductor device manufacturing method comprising a. The method of claim 1, The etching of the substrate for forming the trench, the semiconductor device manufacturing method proceeds by blanket etching (Blanket etch). The method of claim 1, The protective film is a semiconductor device manufacturing method comprising a material containing silicon (Si) and carbon (Carbon). The method of claim 1, The protective film is a semiconductor device manufacturing method comprising any one selected from SiC, SiCN or SiCO. The method of claim 1, The passivation layer includes any one selected from carbides, carbides, and carbide oxides. According to the first, The sacrificial layer pattern includes a nitride layer. The method of claim 6, And the sacrificial film pattern is formed to a thickness of 150 to 300 GPa. According to the first, Forming the plurality of active pillars, And forming the substrate by etching the substrate with at least a nitride film as an etch barrier. The method of claim 1, The method of claim 1, wherein the plurality of active pillars has a narrow gap between adjacent active pillars in a first direction, and a large gap between adjacent active pillars in a second direction crossing the first direction. Forming a plurality of active pillars having recessed sidewalls by etching the substrate using at least a protective film containing a carbon component as an etch barrier; Forming a vertical gate surrounding the recessed sidewall of the active pillar; Forming a buried bit line in the substrate; Forming a sacrificial layer pattern covering sidewalls of the active pillar, the passivation layer, and the vertical gate; And Etching the substrate to self-align the sacrificial layer pattern on the sidewall of the active pillar to form a trench separating the buried bit line A semiconductor device manufacturing method comprising a. The method of claim 10, The etching of the substrate for forming the trench, the semiconductor device manufacturing method proceeds by blanket etching (Blanket etch). The method of claim 10, And the protective film is formed in a stacked structure of a nitride film and a carbon containing film. The method of claim 12, The carbon-containing film is a semiconductor device manufacturing method comprising a material containing silicon (Si) and carbon (Carbon). The method of claim 12, The carbon-containing film is a semiconductor device manufacturing method comprising any one selected from SiC, SiCN or SiCO. The method of claim 12, And the carbon-containing film includes any one selected from carbide, carbide nitride and carbide oxide. The method according to claim 10, The sacrificial layer pattern includes a nitride layer. The method of claim 16, And the sacrificial film pattern is formed to a thickness of 150 to 300 GPa. The method of claim 10, The method of claim 1, wherein the plurality of active pillars has a narrow gap between adjacent active pillars in a first direction, and a large gap between adjacent active pillars in a second direction crossing the first direction.

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