KR20090055970A - Plasma display panel device - Google Patents

Abstract

A plasma display panel device is provided to reduce a bright point and misdicahrge by applying sustain signal having different width to a scan electrode and a wall charge of a sustain electrode. A plasma display panel is composed of a plurality of address electrodes, a plurality of scan electrodes, and a plurality of address electrodes. The highest voltage of a rest signal supplied to a first subfield is higher than that of a reset supplied to a second subfield. At least more than two signal of a plurality of sustain signals have different timings at a sustain period where a plurality of sustain signals are supplied to the scan electrode and a sustain electrode.

Description

Plasma display panel device

The present invention relates to a plasma display device, and more particularly, to a method of driving a plasma display panel.

The plasma display panel (hereinafter referred to as PDP) displays an image by excitation and emitting phosphors by vacuum ultraviolet rays (VUV) generated when the inert gas is discharged.

Such a PDP is not only large in size and thin in thickness, but also has a simple structure and is easy to manufacture, and has a high luminance and high luminous efficiency compared to other flat display devices. In particular, the AC surface-discharge type 3-electrode plasma display panel has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge to protect the electrodes from sputtering caused by the discharge.

The plasma display panel drives time division into a reset section for initializing all cells, an address section for selecting cells, and a sustain section for generating display discharge in the selected cells in order to realize gray levels of an image. do.

If all the electrodes are not initialized to the wall charge state for addressing during the reset period, weak discharge may occur in the sustain period, and thus, bright spots may occur, thereby degrading the quality of the display image.

An object of the present invention is to provide a plasma display apparatus capable of stably driving the plasma display panel by effectively initializing the wall charges of the sustain electrode and the scan electrode before addressing.

A plasma display apparatus according to the present invention includes a plasma display panel including a plurality of scan electrodes and sustain electrodes formed on an upper substrate, and a plurality of address electrodes formed on a lower substrate; And a driving unit supplying a driving signal to the plurality of electrodes, wherein the maximum voltage of the reset signal supplied from the first subfield among the plurality of subfields constituting one frame is the reset signal supplied from the second subfield. At least two of the plurality of sustain signals have different widths in a sustain period in which a plurality of sustain signals are supplied to the scan electrode and the sustain electrode in the second subfield.

The plasma display device according to the present invention can improve mis-discharge of the plasma display panel by applying a sustain signal having a different width in the sustain period between the wall charges of the scan electrode and the sustain electrode of the discharge cell. It is possible to reduce the possibility of bright spot discharge caused by long-term use.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view illustrating a structure of a plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode 12, and an address electrode 22 formed on the lower substrate 20, which are pairs of sustain electrodes formed on the upper substrate 10. do.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. ) May be formed of a metal such as silver (Ag), chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the first embodiment of the present invention, the sustain electrode pairs 11 and 12 have not only a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also without the transparent electrodes 11a and 12a. Only the bus electrodes 11b and 12b may be constituted. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the first embodiment of the present invention is formed on the upper substrate 10. The first black matrix 15 and the transparent electrodes 11a and 12a are formed at positions overlapping the partition wall 21. ) And second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, and may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are physically separated.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases the emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, a lower dielectric layer 24 and a partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 24 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape to physically distinguish the discharge cells, and prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells.

In the first embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in the first embodiment of the present invention, although each of the R, G, and B discharge cells is illustrated and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular but also various polygonal shapes such as pentagon and hexagon.

In addition, the phosphor layer 23 emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

2 is a layout view illustrating an electrode arrangement of a plasma display panel according to a first exemplary embodiment of the present invention.

Referring to FIG. 2, it is preferable that a plurality of discharge cells constituting the plasma display panel are arranged in a matrix form. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since only the first embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating a method of time-division driving by dividing one frame into a plurality of subfields according to the first embodiment of the present invention.

Referring to FIG. 3, a unit frame may be divided into a predetermined number, for example, eight subfields SF1,..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to the first embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to the weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

FIG. 4 is a timing diagram illustrating a first embodiment of a drive signal for driving a plasma display panel with respect to one divided subfield shown in FIG. 3.

Referring to FIG. 4, the subfield includes a pre-reset period for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. A reset section for initializing the discharge cells of the entire screen using the wall charge distribution formed by the reset section, an address section for selecting the discharge cells, and a sustain for maintaining the discharge of the selected discharge cells. ) Section.

The reset section is composed of a setup section and a setdown section. In the setup section, rising ramp waveforms (Ramp-up) are simultaneously applied to all scan electrodes to generate fine discharge in all discharge cells. As a result, wall charges are generated. In the set-down period, a falling ramp waveform (Ramp-down) that falls at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all the scan electrodes (Y), so that erase discharge is generated in all the discharge cells. Generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, the negative scan signal scan is sequentially applied to the scan electrode, and at the same time, the data signal data having the positive voltage Va is applied to the address electrode X. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall voltage generated during the reset period, thereby selecting the cell. Meanwhile, a signal for maintaining a sustain voltage is applied to the sustain electrode during the set down period and the address period.

In the sustain period, a sustain pulse having a sustain voltage Vs is alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The driving waveforms shown in FIG. 4 are a first embodiment of signals for driving the plasma display panel according to the present invention, and the present invention is not limited by the waveforms shown in FIG. 4. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary. After the sustain discharge is completed, an erase signal for erasing wall charge may be applied to the sustain electrode. May be authorized. In addition, the single sustain drive driving the sustain signal may be applied to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

5 is a timing diagram illustrating waveforms of panel driving signals according to a first exemplary embodiment of the present invention.

Referring to FIG. 5, in the reset period, a setup signal that gradually rises to the sustain voltage Vs is supplied to the scan electrode Y, the sustain voltage Vs is maintained for a predetermined time, and then lowered to the ground voltage. A reset signal is provided that includes a set down signal that gradually falls from the voltage to the negative positive voltage.

In the reset section, the setup signal gradually rising up to the sustain voltage Vs is supplied to prevent afterglow erroneous discharge. However, as the signal gradually rising up to the sustain voltage Vs is supplied to the scan electrode Y in the reset period, the scan electrode Y and the sustain electrode Z are accumulated in the sustain period of the previous subfield. The wall charges are not sufficiently erased and weakly discharged in the next sustain section to generate an afterimage bright spot.

Therefore, the plasma display apparatus of the present invention erases the wall charges accumulated in the scan electrode Y and the sustain electrode Z in the reset period in the sustain period of the previous subfield to generate weak discharge in the sustain period of the next subfield. Do not

In the plasma display device according to the present invention, as shown in FIG. 5, a plurality of sustain signals are supplied to the scan electrode Y and the sustain electrode Z in the sustain period.

The sustain period may include a first sustain period p1, a second sustain period p2, and a third sustain period p3, and the scan electrode Y and the sustain electrode may be disposed in the third sustain period p3. The time timing of the last sustain signals Y_L and Z_L of the plurality of sustain signals supplied to Z) is shortened to erase wall charges accumulated in at least one of the scan electrode Y and the sustain electrode Z. In addition, it is possible to prevent the occurrence of the bright spot false discharge due to the change of the discharge characteristics.

According to the first embodiment of the present invention, the sustain period is supplied with the first sustain signal of the plurality of sustain signals supplied to the scan electrode (Y) and the sustain electrode (Z) in the first sustain period (p1), A predetermined number of sustain signals are supplied from the plurality of sustain signals for determining the number of times the discharge cells are discharged in the second sustain period p2, and the scan electrode Y and the sustain electrode Z are provided in the third sustain period p3. The last sustain signal of the plurality of sustain signals is supplied to erase the wall charges accumulated in the wall.

Here, the time timing of the third sustain period p3 is smaller than the time timing of the first sustain period p1 and larger than the time timing of the second sustain period p2.

That is, the time timing of the third sustain period p3 is preferably 7us to 9us. When the setup signal rises to the sustain voltage Vs in the reset period of the next subfield period, the setdown signal goes to the scan electrode Y. When supplied, the Z-bias voltage (Vzb) of the sustain electrode (Z) is supplied so that weak discharge does not occur between the scan electrode (Y) and the sustain electrode (Z), and wall charges such that no bright point discharge occurs in the sustain period. Can accumulate.

Accordingly, the scan electrode Y and the sustain electrode Z in the third sustain period p3 may erase wall charges by adjusting the timing of the last sustain signals Y_L and Z_L among the plurality of sustain signals. .

6 is a timing diagram illustrating waveforms of panel driving signals according to a second exemplary embodiment of the present invention.

Referring to FIG. 6, the reset signal supplied to the scan electrode Y may include a setup period s1 gradually rising from the reset period to the sustain voltage Vs, a sustain period s2 for maintaining the sustain voltage Vs, and It may include a set-down period (s3) sequentially falling from the sustain voltage (Vs) to the ground voltage (GND), and gradually falling from the ground voltage.

In the setup section s1, a reset signal that gradually rises to the sustain voltage Vs is supplied to prevent afterglow erroneous discharge. However, in the setup period s1, as a signal gradually rising up to the sustain voltage Vs is supplied to the scan electrode Y, the signal is accumulated in the scan electrode Y and the sustain electrode Z in the sustain period of the previous subfield. The accumulated wall charges are not sufficiently erased and weakly discharged in the sustain section, resulting in afterimage bright spots.

Therefore, in the plasma display apparatus of the present invention, the signal gradually decreasing to the negative voltage in the set-down period s3 of the reset period is supplied to the sustain electrode Z in the first period A, which is supplied to the scan electrode Y. By supplying a voltage that gradually falls, the wall charge of the sustain electrode Z is reduced so that weak discharge does not occur in the sustain section.

More specifically, during the set-down period s3, a signal that gradually descends to the scan electrode Y is supplied and a positive bias voltage Vzb is supplied to the sustain electrode Z, wherein the scan electrode S and the sustain are supplied. Since the voltage between the electrodes Z does not rise to the discharge start voltage, no discharge occurs, and by applying a voltage that gradually falls to the sustain electrode Z, the wall charge is reduced to prevent the bright spot mis-discharge.

In the plasma display device according to the present invention, as shown in FIG. 6, the voltage supplied to the sustain electrode Z is gradually reduced in the first section A of the set down section s3 in the set down section s3. It is possible to reduce the amount of discharge generated, thereby preventing the occurrence of bright spot discharge due to a change in discharge characteristics.

According to the second embodiment of the present invention, the sustain electrode Z is floated in the first section A of the set-down section s3 to be supplied to the sustain electrode Z in the first section A. FIG. The voltage can be gradually reduced.

When the sustain electrode Z is floated as described above, the falling slope of the voltage supplied to the sustain electrode Z in the first section A is lower than the falling slope of the reset signal supplied to the scan electrode. It may be the same according to the time timing of one section (A).

The surface discharge and the counter discharge may occur simultaneously near the end of the set-down period s3, and thus the possibility of bright spot discharge occurring near the end of the set-down period s3 according to the change of the surface discharge characteristic and the counter discharge characteristic. This is less.

Therefore, the first section A may be located at the second half of the set down section s3 to include an end point of the set down section s3.

In order to prevent excessive discharge during the set-down period as described above, the bias voltage Vzb supplied to the sustain electrode Z is equal to or lower than the sustain voltage Vs, and thus, in the first period a1. It is preferable that the lowest voltage supplied to the sustain electrode Z is lower than the sustain voltage Vs.

However, the voltage difference between the scan electrode Y and the sustain electrode Z is maintained at a predetermined voltage or more during the set-down period s3 so that the sustain voltage Vs is supplied to the scan electrode Y in the setup period s1. desirable.

The sustain period includes a first sustain period p1, a second sustain period p2, and a third sustain period p3, and the scan electrode Y and the sustain electrode Z are disposed in the third sustain period p3. The time timing of the last sustain signal (Y_L, Z_L) of the plurality of sustain signals supplied to the circuit is shortened to erase wall charges accumulated in at least one of the scan electrode (Y) and the sustain electrode (Z), It is possible to prevent the occurrence of bright spot discharge due to the change of discharge characteristics.

In the sustain period, the first sustain signal is supplied from the plurality of sustain signals supplied to the scan electrode Y and the sustain electrode Z in the first sustain period p1, and the discharge cell is supplied in the second sustain period p2. A predetermined number of sustain signals are supplied from among the plurality of sustain signals for determining the number of discharges, and to erase wall charges accumulated in the scan electrode Y and the sustain electrode Z in the third sustain period p3. The last sustain signal is supplied from the plurality of sustain signals.

Here, the time timing of the third sustain period p3 is smaller than the time timing of the first sustain period p1 and larger than the time timing of the second sustain period p2.

That is, the time timing of the third sustain period p3 is preferably 7us to 9us. When the setup signal rises to the sustain voltage Vs in the reset period of the next subfield period, the setdown signal goes to the scan electrode Y. When supplied, the Z-bias voltage (Vzb) of the sustain electrode (Z) is supplied so that weak discharge does not occur between the scan electrode (Y) and the sustain electrode (Z), and wall charges such that no bright point discharge occurs in the sustain period. Can accumulate.

Accordingly, the scan electrode Y and the sustain electrode Z in the third sustain period p3 adjust time timings of the last sustain signals Y_L and Z_L among the plurality of sustain signals to erase wall charges.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made to the branches. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

1 is a perspective view illustrating a structure of a plasma display panel according to a first embodiment of the present invention.

2 is a layout view illustrating an electrode arrangement of a plasma display panel according to a first exemplary embodiment of the present invention.

3 is a timing diagram illustrating a method of time-division driving by dividing one frame into a plurality of subfields according to the first embodiment of the present invention.

FIG. 4 is a timing diagram illustrating a first embodiment of a drive signal for driving a plasma display panel with respect to one divided subfield shown in FIG. 3.

5 is a timing diagram illustrating waveforms of panel driving signals according to a first exemplary embodiment of the present invention.

6 is a timing diagram illustrating waveforms of panel driving signals according to a second exemplary embodiment of the present invention.

Claims (5)

A plasma display panel including a plurality of scan electrodes and sustain electrodes formed on the upper substrate, and a plurality of address electrodes formed on the lower substrate; And a driving unit supplying a driving signal to the plurality of electrodes. The maximum voltage of the reset signal supplied from the first subfield among the plurality of subfields constituting one frame is greater than the maximum voltage of the reset signal supplied from the second subfield, And at least two or more of the plurality of sustain signals have different time timings in a sustain period in which a plurality of sustain signals are supplied to the scan electrode and the sustain electrode in the second subfield. The method of claim 1, wherein the sustain period, A first sustain period to which the sustain signal having a first time timing is supplied; A second sustain period to which the sustain signal having a second time timing is supplied; And And a third sustain period to which the sustain signal having a third time timing is supplied. The method of claim 2, wherein the third time timing, And a plasma display device shorter than the first width and longer than the second time timing. The method of claim 1, wherein the voltage of the sustain signal, A plasma display device which is a scan voltage. The method of claim 2, wherein the third time timing, 7us to 9us plasma display device.

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