KR20090022665A - Method for fabricating contact plug in semiconductor device - Google Patents

Method for fabricating contact plug in semiconductor device Download PDF

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KR20090022665A
KR20090022665A KR1020070088212A KR20070088212A KR20090022665A KR 20090022665 A KR20090022665 A KR 20090022665A KR 1020070088212 A KR1020070088212 A KR 1020070088212A KR 20070088212 A KR20070088212 A KR 20070088212A KR 20090022665 A KR20090022665 A KR 20090022665A
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forming
conductive layer
layer
contact plug
semiconductor device
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KR1020070088212A
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Korean (ko)
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이민석
김원규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a contact plug in a semiconductor device is provided to improve the electrical characteristic of the semiconductor device by filling the gap between the conductive patterns with the conductive layer. A formation method of the contact plug of the semiconductor device comprises a step for forming a conductive pattern(102) on a substrate(101); a step for forming the first insulating layer; a step for exposing the substrate; a step for forming an epitaxial layer(105A); a step for forming a conductive layer; a step for selectively removing the conductive layer; and a step for forming the second insulating layer(108). The first insulating layer is formed on the top of the substrate in order to cover the conductive pattern.

Description

반도체 소자의 콘택플러그 형성방법{METHOD FOR FABRICATING CONTACT PLUG IN SEMICONDUCTOR DEVICE}Method for forming contact plug of semiconductor device {METHOD FOR FABRICATING CONTACT PLUG IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 형성방법에 관한 것으로, 특히 콘택플러그(Contact Plug)를 형성하는 방법에 관한 것이다. The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a contact plug.

일반적으로 반도체소자 제조시 트랜지스터의 소오스 및 드레인에 콘택플러그(Contact Plug)를 먼저 형성한 다음, 캐패시터 및 비트라인을 플러그에 콘택 시키므로서, 소오스 및 드레인과 비트라인 등을 연결하고 있다. 이러한 콘택플러그 형성시, 공정 마진을 확보하기 위하여 자기정렬콘택(Self Aligned Contact; 이하 SAC) 공정을 진행하고 있다.In general, when a semiconductor device is manufactured, a contact plug is first formed in a source and a drain of a transistor, and then a capacitor and a bit line are contacted with a plug, thereby connecting the source, drain, and bit line. In forming the contact plug, a self aligned contact (SAC) process is performed to secure a process margin.

종래기술에 따른 콘택플러그(Contact Plug) 형성방법을 설명하면, 반도체기판상에 도전층 및 하드마스크질화막의 순서로 적층 되는 복수의 도전패턴을 형성하고, 식각정지용 질화막을 형성한 다음, 도전패턴 사이를 채우는 층간절연막을 형성한다.A method of forming a contact plug according to the prior art will be described. A plurality of conductive patterns stacked in the order of a conductive layer and a hard mask nitride film are formed on a semiconductor substrate, a nitride film for etching stop is formed, and then a conductive pattern is formed between the conductive patterns. An interlayer insulating film is formed to fill the gap.

이어서, 하드마스크질화막을 정지막으로 하여 층간절연막을 화학적기계적연마(Chemical Mechanical Polishing; 이하 CMP)의 방법으로 평탄화한다.Subsequently, the interlayer insulating film is planarized by a chemical mechanical polishing (CMP) method using the hard mask nitride film as a stop film.

다음으로, 평탄화된 층간절연막상에 콘택 예정지역을 오픈할 식각마스크를 형성하고 식각공정을 진행하여 콘택플러그(Contact Plug)가 형성될 지역의 기판을 노출시킨다.Next, an etching mask is formed on the planarized interlayer insulating film to open the contact predetermined region, and the etching process is performed to expose the substrate of the region where the contact plug is to be formed.

다음으로, 콘택플러그(Contact Plug) 지역의 오픈부를 충분히 매립하도록 결과물 전면에 폴리실리콘을 증착한 후, CMP공정을 진행하여 콘택플러그(Contact Plug)를 형성한다.Next, polysilicon is deposited on the entire surface of the resultant product to sufficiently fill the open portion of the contact plug region, and then a contact plug is formed by performing a CMP process.

그러나, SAC 방법에 의한 콘택플러그 형성은, 식각에 의한 콘택플러그(Contact Plug)오픈시 하드마스크질화막의 손실을 발생시킨다. 때문에, 오픈된 지역(Open area)과 밀폐된 지역(Closed area)간 하드마스크질화막의 두께 차이가 발생한다. 따라서, 후속 콘택플러그(Contact Plug) 분리를 위한 CMP시에 하드마스크질화막의 연마량을 늘려야하고, 이로 인한 공정 마진확보를 위하여 하드마스크질화막의 두께는 증가 될 수밖에 없다. 그러나 패턴의 미세화 진행 및 높아진 패턴의 종횡비로 인하여, 패턴의 리닝(Leaning) 현상, SAC 콘택 페일 및 콘택 낫오픈과 같은 문제점이 발생하게 된다. 또한 높아진 종횡비는 콘택플러그형성을 위한 폴리실리콘 매립에도 어려움을 주고 있다. However, contact plug formation by the SAC method causes loss of the hard mask nitride film when the contact plug is opened by etching. Therefore, there is a difference in the thickness of the hard mask nitride film between the open area and the closed area. Therefore, the polishing amount of the hard mask nitride film should be increased during the CMP for subsequent contact plug separation, and the thickness of the hard mask nitride film can be increased to secure the process margin. However, due to the miniaturization of the pattern and the increased aspect ratio of the pattern, problems such as a lining phenomenon of the pattern, a SAC contact fail, and a contact knock open may occur. In addition, the increased aspect ratio also has difficulty in embedding polysilicon for forming contact plugs.

본 발명은 상기 종래기술의 문제점을 해결하기 위해 제안된 것으로, 도전패턴의 리닝(Leaning) 현상, SAC 콘택 페일, 콘택 낫오픈, 콘택매립 불량등의 문제를 방지할 수 있는 반도체 소자의 콘택플러그 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art, the formation of a contact plug of a semiconductor device that can prevent problems such as the phenomenon (Leaning) of the conductive pattern, SAC contact fail, contact open, poor contact filling The purpose is to provide a method.

상기의 목적을 달성하기 위한 본 발명의 콘택플러그 형성방법은, 자신의 상부에 하드마스크막을 갖는 복수의 도전패턴을 기판상에 형성하는 단계; 상기 기판 및 도전패턴 표면을 덮는 스페이서용 절연막을 형성하는 단계; 상기 스페이서용 절연막을 식각하여 기판을 오픈시키는 단계; 상기 오픈된 기판상에 에피텍셜층을 형성하는 단계; 상기 에피텍셜층 상에 상기 도전패턴들 사이를 매립하는 도전층을 형성하는 단계; 예정된 콘택영역을 제외한 상기 도전층을 선택적으로 식각하는 단계;및 상기 도전층이 식각된 영역을 절연막으로 매립하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming a contact plug, the method including: forming a plurality of conductive patterns on a substrate having a hard mask film thereon; Forming an insulating film for a spacer covering the surface of the substrate and the conductive pattern; Etching the spacer insulating film to open the substrate; Forming an epitaxial layer on the open substrate; Forming a conductive layer filling the epitaxial layer between the conductive patterns; Selectively etching the conductive layer except for a predetermined contact region; and filling a region in which the conductive layer is etched with an insulating layer.

본 발명은, 자기정렬콘택 식각 방법을 배제하고 선택적 실리콘 단결정 성장(Selective Silicon Epitaxial Growth) 및 폴리실리콘 증착의 방법으로 콘택플러그를 형성한다. 이로 인해 SAC 공정시 발생할 수 있는 콘택 페일의 문제점을 피할 수 있다. 또한 일정부분 높이까지 실리콘 단결정 성장으로 콘택플러그를 형성하므로 폴리실리콘의 매립을 용이하게 할 수 있다. 또한 게이트 하드마스크의 두께를 줄여 패턴의 종횡비를 낮출 수 있어 리닝현상 및 로딩에의한 ID-바이어스(ID-Bias) 현상 개선이 가능하다.The present invention forms a contact plug by a method of selective silicon epitaxial growth and polysilicon deposition excluding the self-aligned contact etching method. This avoids the problem of contact fail that may occur during the SAC process. In addition, since the contact plug is formed by growing silicon single crystal to a certain height, it is possible to facilitate the embedding of polysilicon. In addition, by reducing the thickness of the gate hard mask, the aspect ratio of the pattern can be lowered, thereby improving ID-bias due to lining and loading.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체소자의 콘택플러그 형성방법을 도시한 도면이다.1A to 1E illustrate a method of forming a contact plug in a semiconductor device according to an embodiment of the present invention.

기판(101)상에 하드마스크막(103) 및 스페이서(104)를 갖는 복수의 도전패턴(102)을 형성한다. 여기서 도전패턴(102)은 게이트패턴이 될 수도 있고, 비트라인패턴 될 수도 있다. 도전패턴(102)이 게이트패턴일 경우 기판(101) 사이에 게이트 절연막을 도시 하여야 하나 본 도면에서는 생략하였다. 게이트패턴이 되는 경우, 지역(A)는 소오스 또는 드레인 영역이고, 지역(B)는 소자분리막 영역이다. 소오스/드레인의 형성은 선행된 게이트패턴 형성 과정에서 이온주입을 통하여 형성하거나, 후속 랜딩플러그 형성 과정에서 불순물을 기판으로 확산시키는 방법으로 형성 가능하다. 도전패턴(102)이 비트라인 패턴일 경우, 지역(A)는 하부전극이 위치하고 있는 지역이 되고, 지역(B)는 전극이 없는 절연막 부분이 된다. 여기서 하부 전극은 후속 에피텍셜성장에 의해 콘택플러그가 형성되어야 하기 때문에, 실리콘 공유결합을 가질 수 있는 물질, 예를 들면 폴리실리콘으로 형성하는 것이 바람직하 다.A plurality of conductive patterns 102 having a hard mask film 103 and a spacer 104 are formed on the substrate 101. The conductive pattern 102 may be a gate pattern or a bit line pattern. When the conductive pattern 102 is a gate pattern, a gate insulating film must be shown between the substrates 101, but it is omitted in this drawing. In the case of a gate pattern, region A is a source or drain region, and region B is an isolation layer region. The source / drain may be formed by ion implantation in the previous gate pattern formation process or by diffusing impurities into the substrate in the subsequent landing plug formation process. When the conductive pattern 102 is a bit line pattern, the region A becomes a region where the lower electrode is located, and the region B becomes an insulating film portion having no electrode. The lower electrode is preferably formed of a material capable of having a silicon covalent bond, for example polysilicon, since the contact plug must be formed by subsequent epitaxial growth.

기존의 SAC 방법의 콘택플러그 형성에서 하드마스크(103)는 층간 절연 물질로 쓰이는 산화막 계열의 물질과 식각 선택비를 가지기 위해 질화막이 사용되었다. 그러나, 본 발명에서는 SAC공정을 사용하지 않고 콘택플러그를 형성하기 때문에, 하드마스크(103)는 질화막 또는 산화막 계열 등의 다양한 물질이 사용 가능하다. 또한 종래의 SAC 공정에서는 하드마스크(103)의 손실을 감안하여 두껍게 형성하였으나 본 발명을 적용할 경우 기존에 비해 낮은 500Å~1500Å에서 그 증착 두께를 결정할 수 있다. In the formation of the contact plug of the conventional SAC method, the hard mask 103 is formed of a nitride film to have an etch selectivity with an oxide-based material used as an interlayer insulating material. However, in the present invention, since the contact plug is formed without using the SAC process, the hard mask 103 may use various materials such as a nitride film or an oxide film series. In addition, in the conventional SAC process, the thickness was formed in consideration of the loss of the hard mask 103, but when the present invention is applied, the deposition thickness thereof may be determined at 500 Å to 1500 낮은, which is lower than that of the conventional SAC process.

이어서, 주변회로 지역을 마스크로 보호하며(도면에서는 도시 생략), 스페이서용 절연막을 전면 건식 식각 하여 기판의 지역(A) 및 지역(B)를 오픈시킨다. 스페이서(104)는 후속 플러그 형성 전 세정을 BOE(BUFFERED OXIDE ETCHANT)를 사용하여 실시할 경우 BOE에 식각 저항성이 있는 물질, 예컨데 질화막 계열을 사용하여 형성함이 바람직하다. 습식 세정에서 HF를 사용하면 지역(A)에 하이드로젠 패시베이션(Hydrogen Passivation)이 발생하여, 후속 실리콘 에피텍셜 성장이 원활히 이루어지지 않는다.Subsequently, the peripheral circuit area is protected with a mask (not shown in the figure), and the insulating film for the spacer is dry-etched on the entire surface to open the area A and the area B of the substrate. The spacer 104 may be formed by using a BOE (BUFFERED OXIDE ETCHANT) for subsequent cleaning before forming the plug using a material that is etch resistant to the BOE, such as a nitride film series. The use of HF in wet scrubbing results in Hydrogen Passivation in area (A), resulting in poor silicon epitaxial growth.

한편, 플러그 형성 전 세정으로 건식 세정(Dry Cleaning)의 방법도 사용 가능하다. 따라서, 건식 세정을 실시할 경우에는 산화막, SiCN, SiBN 및 SiBCN과 같은 절연막을 스페이서(104)로 사용할 수 있다. On the other hand, a method of dry cleaning can also be used by cleaning before plug formation. Therefore, when dry cleaning is performed, insulating films such as oxide film, SiCN, SiBN and SiBCN can be used as the spacer 104.

이어서, 도 1b에 도시된 바와 같이, 선택적 에피텍셜 성장방법(Selective Epitaxial Growth; SEG)을 이용하여 지역(A)에 에피텍셜성장층(105)을 형성한다. 이때 불순물을 포함시켜 전극으로서의 도전성을 확보할 수 있다. 에피텍셜성장은 산화막 계열인 지역(B)에 비해, 실리콘 공유 결합이 가능한 지역(A)에서 활발하게 이루어 지기 때문에 선택적 성장이 가능하다. 또한 질화막 계열인 스페이서(104)의 측면에도 성장이 원활하지 않기 때문에 에피텍셜성장층(105)은 지역(A)의 바닥부터 성장하게 된다. 여기서 에피텍셜 성장의 두께만큼 도전패턴의 종횡비는 낮아지게 되어 후속 폴리실리콘 증착 매립조건이 개선된다. 또한 에피텍셜 성장에의한 실리콘 단결정은 도전성 및 콘택 저항 특성이 폴리실리콘보다 우수하므로, 패턴 미세화에 따른 콘택플러그의 저항 증가를 감소시키는데 도움이 된다.Subsequently, as shown in FIG. 1B, the epitaxial growth layer 105 is formed in the region A using the selective epitaxial growth (SEG) method. At this time, impurities can be included to ensure conductivity as an electrode. Epitaxial growth is more active in the area (A) where silicon covalent bonds are possible than in the area (B), which is an oxide film series, and thus selective growth is possible. In addition, since the growth is not smooth on the side of the spacer 104 which is a nitride film series, the epitaxial growth layer 105 grows from the bottom of the area A. Here, the aspect ratio of the conductive pattern is lowered by the thickness of the epitaxial growth, so that the subsequent polysilicon deposition buried conditions are improved. In addition, the silicon single crystal by epitaxial growth is superior to polysilicon in terms of conductivity and contact resistance properties, and thus helps to reduce the increase in resistance of the contact plug due to the pattern miniaturization.

다음으로, 도 1c에 도시된 바와 같이 에피텍셜성장층(105) 및 기판 전체에 폴리실리콘(106)을 매립한다. 도전패턴(102)의 간격을 모두 메울 수 있게, 500Å~3000Å의 두께로 매립하는 것이 바람직하다. Next, as shown in FIG. 1C, the polysilicon 106 is embedded in the epitaxial growth layer 105 and the entire substrate. It is preferable to fill in the thickness of 500 micrometers-3000 micrometers so that the space | interval of the conductive pattern 102 can be filled.

이어서, 폴리실리콘(106)과 하드마스크(103)와의 선택비를 가지는 슬러리를 이용하여 화학적기계적연마(Chemical Mechanical Polishing)를 실시하여, 하드마스크(103)가 드러나도록 평탄화시킨다.Subsequently, chemical mechanical polishing is performed using a slurry having a selectivity between the polysilicon 106 and the hard mask 103 to flatten the hard mask 103 to be exposed.

이어서, 도 1d에서 도시된 바와 같이, 콘택예정지역을 덮는 마스크(107)를 형성하고 이를 베리어로 하여 폴리실리콘(106)을 건식 식각으로 제거한다. 질화막 계열의 스페이서(104)와 폴리실리콘(106)과의 식각 선택비를 고려하여, Cl2, Hbr, Ar, O2, N2, He, CxFy(x,y는 자연수) 및 CxHyFz(x,y,z는 자연수)로 이루어진 그룹으로부터 선택된 가스의 조합을 사용하여 건식 식각 하는 것이 바람직하다. 이어서, 식각 베리어로 사용된 마스크(107)를 제거하면, 콘택예정지역의 에피텍셜성장층(105A)과 폴리실리콘(106A)이 남게 되어 콘택플러그가 형성되게 된다.Subsequently, as shown in FIG. 1D, a mask 107 is formed to cover the region to be contacted and the polysilicon 106 is removed by dry etching as a barrier. Considering the etching selectivity between the nitride film-based spacer 104 and polysilicon 106, Cl 2 , Hbr, Ar, O 2 , N 2 , He, CxFy (x, y is a natural number) and CxHyFz (x, It is preferable that dry etching be performed using a combination of gases selected from the group consisting of y and z are natural numbers). Subsequently, when the mask 107 used as the etching barrier is removed, the epitaxial growth layer 105A and the polysilicon 106A of the region to be contacted remain to form a contact plug.

도전패턴(102)이 게이트패턴일 경우 상기 콘택플러그는 랜딩플러그콘택(Landing Plug Contact; LPC)이 되며, 비트라인패턴일 경우 콘택플러그는 스토리지노드콘택(Storage Node Contact; SNC)이 됨을 알 수 있다.When the conductive pattern 102 is a gate pattern, the contact plug becomes a landing plug contact (LPC), and when the bit line pattern, the contact plug becomes a storage node contact (SNC). .

다음으로, 도 1e에서 도시된 바와 같이, 결과물 전체 구조상에 층간절연막(108)을 증착한다. 매립특성이 우수한 물질, 예를 들면 BPSG(Boron Phosphorus Silicate Glass), HDP 옥사이드(High Density Plasma Oxide), Polyimide, PAE(Poly Arylene Ether), HSQ(Hydrogen SilsesQuioxane), MSQ(Methyl SisesQuioxane), SiLK(Silica low-k), PHPS(Perhydropolysilazane), SOD(Spin On Dielectric)에서 선택된 어느 하나를 절연막(108)으로 사용하는 것이 바람직하다. Next, as shown in FIG. 1E, an interlayer insulating film 108 is deposited on the entire structure of the resultant. Substances with excellent buried properties, such as Boron Phosphorus Silicate Glass (BPSG), High Density Plasma Oxide (HDP), Polyimide, Poly Arylene Ether (PAE), Hydrogen SilsesQuioxane (HSQ), Methyl SisesQuioxane (MSQ), SiLK (Silica) low-k), PHPS (Perhydropolysilazane), SOD (Spin On Dielectric) is preferably used as the insulating film 108.

이어서 폴리실리콘(106A)과 상기 매립특성이 우수한 물질중 선택된 절연막(108)과의 선택비를 가지는 슬러리를 이용하여 화학적기계적연마(Chemical Mechanical Polishing)를 실시하여, 폴리실리콘(106A)이 드러나도록 평탄화시키면, LPC 또는 SNC 형성 과정이 완료된다.Subsequently, chemical mechanical polishing is performed using a slurry having a selectivity between the polysilicon 106A and the insulating film 108 selected from the materials having excellent buried characteristics, thereby flattening the polysilicon 106A to be exposed. Then, the LPC or SNC formation process is completed.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술분야의 통상의 전문가라면 본 발명의 기술사상의 범위내의 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

도 1a 내지 도 1e는 본 발명의 일 실시예에 따른 콘택플러그 형성방법을 도시한 도면.1A to 1E illustrate a method for forming a contact plug according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명** Explanation of symbols for the main parts of the drawings *

101 : 기판 102 : 도전패턴    101: substrate 102: conductive pattern

103 : 하드마스크 104 : 스페이서    103: hard mask 104: spacer

105A : 에피텍셜성장층 106A : 폴리실리콘    105A: epitaxial growth layer 106A: polysilicon

Claims (12)

자신의 상부에 하드마스크막을 갖는 복수의 도전패턴을 기판상에 형성하는 단계;Forming a plurality of conductive patterns having a hard mask film thereon on the substrate; 상기 기판 및 도전패턴 표면을 덮는 스페이서용 절연막을 형성하는 단계;Forming an insulating film for a spacer covering the surface of the substrate and the conductive pattern; 상기 스페이서용 절연막을 식각하여 기판을 오픈시키는 단계;Etching the spacer insulating film to open the substrate; 상기 오픈된 기판상에 에피텍셜층을 형성하는 단계;Forming an epitaxial layer on the open substrate; 상기 에피텍셜층 상에 상기 도전패턴들 사이를 매립하는 도전층을 형성하는 단계;Forming a conductive layer filling the epitaxial layer between the conductive patterns; 예정된 콘택영역을 제외한 상기 도전층을 선택적으로 식각하는 단계;및Selectively etching the conductive layer except for a predetermined contact region; and 상기 도전층이 식각된 영역을 절연막으로 매립하는 단계Filling a region in which the conductive layer is etched with an insulating layer 를 포함하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.Contact plug forming method of a semiconductor device comprising a. 제 1항에 있어서,The method of claim 1, 상기 도전패턴은 비트라인패턴 또는 게이트패턴인 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.And wherein the conductive pattern is a bit line pattern or a gate pattern. 제 1항에 있어서,The method of claim 1, 상기 도전층을 형성하는 단계는,Forming the conductive layer, 상기 도전층을 증착하는 단계; 및Depositing the conductive layer; And 상기 도전층을 상기 하드마스크막이 드러나도록 화학적기계적연마하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.And chemical mechanical polishing the conductive layer to expose the hard mask layer. 제 1항에 있어서,The method of claim 1, 상기 도전층은 폴리실리콘인 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.The conductive layer is a method for forming a contact plug of a semiconductor device, characterized in that the polysilicon. 제 1항에 있어서,The method of claim 1, 상기 예정된 콘택영역을 제외한 상기 도전층을 선택적으로 식각하는 단계는,Selectively etching the conductive layer except for the predetermined contact region, 예정된 콘택영역을 보호하는 마스크를 형성하는 단계;Forming a mask protecting a predetermined contact region; 상기 마스크를 베리어로하여 상기 도전층을 식각하는 단계; 및Etching the conductive layer using the mask as a barrier; And 상기 마스크를 제거하는 단계를 포함하는 반도체 소자의 콘택플러그 형성방법.Removing the mask; and forming a contact plug of the semiconductor device. 제 5항에 있어서,The method of claim 5, 상기 도전층의 식각은 건식식각 방법으로 수행하며, Cl2, Hbr, Ar, O2, N2, He, CxFy(x,y는 자연수) 및 CxHyFz(x,y,z는 자연수)로 이루어진 그룹으로부터 선택된 가스의 조합을 사용하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.Etching of the conductive layer is performed by a dry etching method, a group consisting of Cl 2 , Hbr, Ar, O 2 , N 2 , He, CxFy (x, y is a natural number) and CxHyFz (x, y, z is a natural number). A method of forming a contact plug for a semiconductor device, characterized by using a combination of gases selected from. 제 1항에 있어서,The method of claim 1, 상기 도전층이 식각된 영역을 절연막으로 매립하는 단계는,The step of filling the region in which the conductive layer is etched with the insulating film, 절연막을 증착하는 단계; 및Depositing an insulating film; And 상기 예정된 콘택영역의 도전층이 드러나도록 상기 절연막을 화학적기계적연마하는 단계Chemical mechanical polishing the insulating film to expose the conductive layer of the predetermined contact region 를 포함하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.Contact plug forming method of a semiconductor device comprising a. 제 7항에 있어서,The method of claim 7, wherein 상기 절연막은 BPSG, HDP옥사이드, Polymide, PAE, HSQ, MSQ, SiLK, PHPS, SOD중에서 선택된 어느 하나인 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.The insulating film is a contact plug forming method of a semiconductor device, characterized in that any one selected from BPSG, HDP oxide, Polymide, PAE, HSQ, MSQ, SiLK, PHPS, SOD. 제 1항에 있어서,The method of claim 1, 상기 하드마스크막은 500Å~1500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.The hard mask film is a contact plug forming method of the semiconductor device, characterized in that formed in a thickness of 500 ~ 1500Å. 제 1항에 있어서,The method of claim 1, 상기 스페이서용 절연막은 질화막, 산화막, SiCN, SiBN 및 SiBCN 으로 이루어진 그룹으로 부터 선택된 어느 하나인 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법.And the insulating film for spacers is any one selected from the group consisting of a nitride film, an oxide film, SiCN, SiBN, and SiBCN. 제 1항에 있어서,The method of claim 1, 상기 스페이용 절연막의 식각은 전면 건식 식각으로 하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법. The method of claim 1, wherein the etching of the space insulating layer is performed by dry etching over the entire surface. 제 1항에 있어서,The method of claim 1, 상기 하드마스크막은 질화막 또는 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 콘택플러그 형성방법. And the hard mask layer is formed of a nitride layer or an oxide layer.
KR1020070088212A 2007-08-31 2007-08-31 Method for fabricating contact plug in semiconductor device KR20090022665A (en)

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