KR20070098229A - A method for skew compensation and an apparatus using the method - Google Patents

Abstract

A method for skew compensation and a semiconductor memory test apparatus having a skew compensation function are provided to compensate skew of the test apparatus without comprising a compensation apparatus of the test apparatus. According to a method for skew compensation, skew of a sample memory is acquired(S100). A test valid period and the position of a center position of each pin is searched by mounting the sample memory in a test apparatus(S102,S104). The time when the center position in the valid period of each pin becomes is acquired. The skew compensation is performed by applying the skew value of the sample memory when the center position in the valid period becomes. The compensation value obtained by applying the skew value of the sample memory when the center position in the valid period becomes is stored in a storing part of the test apparatus(S106).

Description

Semiconductor memory test equipment with skew compensation method and skew compensation function {A method for skew compensation and an apparatus using the method}

1 is a prior art diagram of a tester correction system utilizing an oscilloscope,

2 is a prior art diagram of a tester correction system using a short board;

3 is a diagram of a tester correction system according to the present invention;

4 is a detailed view of the TPG board of FIG.

5 is a view showing the installation shape of the tester correction system for implementing the present invention,

6 is a diagram of a test correction method according to a preferred embodiment of the present invention;

7A is a diagram of a sample memory skew measurement,

7b is a diagram regarding a valid section measurement of a TPG board;

7C is a diagram of actual signal processing applying a skew value of a sample memory;

The present invention relates to a memory test equipment, and more particularly to a semiconductor memory test equipment having a skew correction method and a skew correction function of the semiconductor memory test equipment.

To successfully test the device under test (DUT), the signals applied to the device pins along each transmission line must arrive at the correct timing for each other. Transmission lines that transmit tester signals to the DUT typically vary in length, which means that the delay times vary with respect to each other.

Therefore, in order to accurately control the signal timing, the delay degree for each channel must be measured, and the correction considering the delay must be preceded before the timing correction process.

Such a memory test system is a combination of a computer and various test devices, and controls test hardware by executing an instruction set of a test program.

The memory test system periodically corrects various parameters necessary for the test before the test in order to measure the test results accurately and reliably and reliably.

Correction work is an important element in memory test. In general, an external dedicated parameter correction device is built and a signal of each parameter is input to determine a valid section of each signal.

Such a system is expensive to build external calibration equipment, and takes a long time to calibrate. In addition, the calibration process must be performed at regular intervals to ensure the accuracy and stability of the system. Being calibrated periodically means that the test takes a long time.

In test systems that require periodic calibrations, the test device's test productivity is very low.

A conventional test equipment calibration system will be described with reference to the drawings.

1 is a prior art diagram of a tester correction system utilizing an oscilloscope. Referring to FIG. 1, a signal generated by the tester 2 is used by using a general-purpose interface such as a general purpose interface bus (GPIB) while a separate board 3 is placed on a socket so that a signal can be measured at the far end. To the oscilloscope (1).

After measuring the signal generated by the tester (2) using the oscilloscope (1), the skew can be adjusted.The device under test (hereinafter referred to as 'DUT') or a specific pin is used as a reference for the entire pin. Calibration will be performed. This method is highly accurate because it can be applied to any object to be measured. On the other hand, since each pin must proceed sequentially, it takes a long time and wastes manpower for this.

2 is a prior art diagram of a tester correction system utilizing a short board. Referring to FIG. 2, a short circuit board 11 in which all signals except for a power pin are shorted is placed on a socket board 12, and the same signal is sent through all drivers so that the overlapped signals are used as reference signals. The skew is adjusted by comparison difference compared to other signals.

This method has an effect of shortening the time since all the memory devices under test can be calibrated. However, when the short circuit board is manufactured, if the printed circuit board (PCB) pattern length or impedance does not match, there is a disadvantage that the precision is lowered.

The test system developed to date has to build external calibration equipment separately, and even if there is a calibration equipment, there is a problem that it takes a long time if the precision is excellent, or that the precision falls if the time is shortened. Is being requested.

The present invention is to solve this problem, to provide a skew correction method and a semiconductor memory test equipment having a skew correction function of the semiconductor memory test equipment that can correct the skew of the test equipment without having the calibration equipment of the test equipment There is a purpose.

In addition, by storing the skew value corresponding to each pin of the sample memory in the test equipment, another object of the test equipment is to provide a test equipment that does not need to be calibrated for every test object.

Skew correction method of the semiconductor memory test equipment according to the present invention for achieving this object comprises the steps of obtaining a skew of the sample memory; Mounting the sample memory to the test equipment to retrieve the test valid interval and the position of the center position of each pin; Acquiring a time point at which a center position within an effective period of each of the pins is obtained; Correcting by applying a skew value of the sample memory to a time point at which the center position within the valid period is reached; And storing a value corrected by applying a skew value of the sample memory to a time point at which the center position is within the valid interval, in the storage unit of the test equipment.

The method is characterized in that the repetition is performed for each pin to be tested.

The step of acquiring the skew of the sample memory may be performed by repeatedly experimenting with each channel before mounting the sample memory to obtain a skew value.

The test memory section search and the position of the center position of each pin by mounting the sample memory may be performed by delaying the test channel at a predetermined interval until the time point at which the center position is located within the valid section is found. It is characterized by.

In the step of correcting by applying a skew value of the sample memory to the time point at which the center position within the effective period, the viewpoint is corrected by subtracting the skew value from the time point for the effective section and the center position.

In addition, the semiconductor memory test equipment having a skew correction function according to the present invention for achieving the above object includes a test board for processing an electrical / physical signal for testing a memory device; A sample memory is mounted on the test board to obtain a time point at which the center position is within an effective period of each pin of the sample memory, and a value corrected by the skew value of the sample memory is stored in a storage unit, and stored for each memory to be tested. Timing Pattern Generator (TPG) board for testing by applying a skew value stored in the; And a computer that transmits a skew value of a sample memory to the TPG board, receives a normal / bad status for each channel tested in the TPG board, and provides a program for testing.

The sample memory is characterized in that the measurement process is performed in advance before the test to obtain a skew value generated according to the memory characteristics.

The test board includes at least one device under test (DUT) board for mounting a plurality of memories.

The TPG board comprises a pattern generator for generating a test pattern signal; A sequential controller for controlling a sequence of signals; A storage unit for storing a skew value for each channel of the sample memory; A control unit outputting a control signal to process a signal of each channel by correcting the skew value for each channel stored in the storage unit; And relay unit for transmitting the on / off for the signal applied for each channel, each relay unit is characterized in that it comprises a driver and a comparator for performing the signal transmission and detection, respectively.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. In the description of the embodiments, the same components are designated by the same reference numerals for the convenience of understanding, even though shown in different drawings.

3 is a diagram of a tester correction system according to the present invention. Referring to FIG. 3, a tester correction system according to the present invention includes a test board for processing an electrical / physical signal for testing a memory device, and a timing pattern generator (TPG) for testing an operation by applying an electrical signal to the memory device. A board 200, a personal computer 300 for overall control of the memory test equipment, a power supply unit 410 for supplying power, and a cooler 405 for cooling heat of the TPG board are provided.

In addition, the test board includes at least one device under test (DUT) board 100 for mounting a plurality of memories.

Before the test is performed, the skew of the memory itself is measured in advance and processed into sample memory.

It is preferable to use a sample memory that is determined to be accurate by repeating experiments for each channel.

4 is a detailed view of the TPG board of FIG. Referring to FIG. 4, the TPG board 200 includes a pattern generator ALPG 201 for generating a test pattern signal, a sequential controller 204 for controlling a sequence of signals, and skew for each channel of a sample memory. EEPROM 205 for storing the value, the control unit 210 for controlling the overall signal processing of the TPG board 200 and the relay unit 203 for transmitting the on / off for the signal applied for each channel It consists of.

Each of the relay units 203 further includes a driver (DR) / comparator (CP) 202 for performing signal transmission and detection. A DPS 211 for digital signal processing and an analog processing unit for processing an analog signal are further included.

In the state implemented as described above, a command is transmitted from the PC 300 to the TPG board 200 through an interface board. The command is applied to the ALPG 201 and the sequential control unit 204 in the TPG board 200, and a test pattern is generated. The test pattern is converted to meet the specifications of the DUT in the driver 202 and transferred to the DUT through the relay unit 203.

The signal generated from the DUT by the test pattern is transmitted to the comparator 202 through the relay unit 203 and finally transferred to the PC to determine whether the DUT is normal or defective.

Even in the above-described state, since a high amount of current is required for the electrical signals applied to the driver and the memory, there is a possibility that the skew may vary due to time or various factors.

That is, even if the signal to be applied / measured should be normal, there is a possibility that it is determined to be defective.

The present invention is to ensure the reliability of the test by matching the skew between the signal to be applied / measured through the equipment calibration process in the memory test system.

5 is a view showing the installation shape of the tester correction system for implementing the present invention. Referring to FIG. 5, no additional equipment is added to the socket for calibrating the tester. Only the sample device is installed so that only the skew of the sample device can be measured.

The tester correction method after the skew of the sample device is measured according to the form shown in FIG. 5 will now be described.

6 is a diagram of a test calibration method according to a preferred embodiment of the present invention. Referring to FIG. 6, when sample device skew measurement is performed (S100), a test valid interval is searched for / RAS, / CAS, / WE, DQ, etc. of each pin (S102). Subsequently, the actual center position of the measured valid interval of the current memory test system is determined by applying the measured skew value of the known sample device in advance (S104), and the skew data is stored in the EEPROM of the TPG board (S106).

The method will be described in detail with reference to the timing relationship diagram (Fig. 7).

FIG. 7A is a diagram illustrating a sample memory skew measurement, FIG. 7B is a diagram illustrating a valid section measurement of a TPG board, and FIG. 7C is a diagram illustrating actual signal processing applying a skew value of the sample memory.

In FIG. 7A, a skew value of an arbitrary signal measured in advance is shown. The effective section is 200-400ps and a 30ps difference occurs with the center of the valid section between the reference signal and an arbitrary signal. That's 30 ps of skew.

7B shows arbitrary signals and reference signals measured using a sample memory device on the TPG board of the current system to be calibrated. The effective section is searched for with a delay at a predetermined time (for example, 10 ps).

In FIG. 7C, the center position is determined by compensating for the difference between the reference signal known from FIG. 7A and the center of the effective section.

Although the present invention has been described above with reference to its preferred embodiments, those skilled in the art will variously modify the present invention without departing from the spirit and scope of the invention as set forth in the claims below. And can be practiced with modification. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

As described above, the memory test system according to the present invention automatically corrects using a sample memory device itself without using external measuring equipment during calibration to ensure important stability and reliability in simultaneously testing a large amount of memory. To increase reliability, stability and precision. In addition, there is no dependence on external equipment generated during calibration, which reduces the development time and significantly reduces the development cost.

Claims (9)

Obtaining a skew of the sample memory; Mounting the sample memory to the test equipment to retrieve the test valid interval and the position of the center position of each pin; Acquiring a time point at which a center position within an effective period of each of the pins is obtained; Correcting by applying a skew value of the sample memory to a time point at which the center position within the valid period is reached; And And applying a skew value of the sample memory to a time point at which the center position is within the valid period, and storing the corrected value in the storage unit of the test equipment. The method of claim 1, wherein the steps The skew correction method of the semiconductor memory test equipment, characterized in that performed for each pin to be tested. The method of claim 1, Acquiring a skew of the sample memory Skew correction method of a semiconductor memory test equipment, characterized in that to obtain a skew value by repeated experiments for each channel before mounting the sample memory. The method of claim 1, Mounting the sample memory to search for the test valid interval of each pin and the location of the center position is A method for correcting skew of a semiconductor memory test apparatus, characterized by delaying and searching for a channel to be tested at a predetermined interval until a time point at which a center position is located within an effective section is found. The method of claim 1, Correcting by applying a skew value of the sample memory to a time point at which the center position within the valid period is reached; A skew correction method of a semiconductor memory test equipment, characterized in that the timing is corrected by subtracting a skew value with respect to a valid period and a point of time of a center position. Test boards that process electrical and physical signals for testing memory devices; A sample memory is mounted on the test board to obtain a time point at which the center position is within an effective period of each pin of the sample memory, and a value corrected by the skew value of the sample memory is stored in a storage unit, and stored for each memory to be tested. A test pattern generator (TPG) board for testing by applying a skew value stored in the test board; And A semiconductor memory test having a skew correction function comprising a computer for transmitting a skew value of a sample memory to the TPG board, receiving a normal / bad status for each channel tested in the TPG board, and providing a program for testing. equipment. The method of claim 6, The sample memory is a semiconductor memory test equipment having a skew correction function, characterized in that the measurement process is performed in advance before the test to obtain a skew value generated according to the memory characteristics. The method of claim 6, The test board At least one device under test (DUT) board for mounting a plurality of memory, semiconductor memory test equipment having a skew correction function characterized in that it comprises. The method of claim 6, The TPG board A pattern generator which generates a test pattern signal; A sequential controller for controlling a sequence of signals; A storage unit for storing a skew value for each channel of the sample memory; A control unit outputting a control signal to process a signal of each channel by correcting the skew value for each channel stored in the storage unit; And It includes a relay unit for transmitting on / off for the signal applied for each channel, And each of the relay units includes a driver and a comparator for performing signal transmission and detection, respectively.

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