KR20070080324A - Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength - Google Patents

Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength Download PDF

Info

Publication number
KR20070080324A
KR20070080324A KR1020060011539A KR20060011539A KR20070080324A KR 20070080324 A KR20070080324 A KR 20070080324A KR 1020060011539 A KR1020060011539 A KR 1020060011539A KR 20060011539 A KR20060011539 A KR 20060011539A KR 20070080324 A KR20070080324 A KR 20070080324A
Authority
KR
South Korea
Prior art keywords
polyimide layer
semiconductor chip
chip
wafer
semiconductor
Prior art date
Application number
KR1020060011539A
Other languages
Korean (ko)
Inventor
김상영
문태호
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020060011539A priority Critical patent/KR20070080324A/en
Publication of KR20070080324A publication Critical patent/KR20070080324A/en

Links

Images

Classifications

    • A—HUMAN NECESSITIES
    • A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
    • A01M—CATCHING, TRAPPING OR SCARING OF ANIMALS; APPARATUS FOR THE DESTRUCTION OF NOXIOUS ANIMALS OR NOXIOUS PLANTS
    • A01M29/00—Scaring or repelling devices, e.g. bird-scaring apparatus
    • A01M29/06—Scaring or repelling devices, e.g. bird-scaring apparatus using visual means, e.g. scarecrows, moving elements, specific shapes, patterns or the like
    • A01M29/10—Scaring or repelling devices, e.g. bird-scaring apparatus using visual means, e.g. scarecrows, moving elements, specific shapes, patterns or the like using light sources, e.g. lasers or flashing lights
    • A—HUMAN NECESSITIES
    • A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
    • A01M—CATCHING, TRAPPING OR SCARING OF ANIMALS; APPARATUS FOR THE DESTRUCTION OF NOXIOUS ANIMALS OR NOXIOUS PLANTS
    • A01M29/00—Scaring or repelling devices, e.g. bird-scaring apparatus
    • A01M29/16—Scaring or repelling devices, e.g. bird-scaring apparatus using sound waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Life Sciences & Earth Sciences (AREA)
  • Birds (AREA)
  • Engineering & Computer Science (AREA)
  • Insects & Arthropods (AREA)
  • Pest Control & Pesticides (AREA)
  • Wood Science & Technology (AREA)
  • Zoology (AREA)
  • Environmental Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Die Bonding (AREA)

Abstract

A method for attaching and stacking a semiconductor chip using a polyimide layer is provided to simplify an attachment process and a stacking process by attaching the semiconductor chip on a package substrate or stacking the semiconductor chip to another semiconductor chip. A supplying process is performed to supply a wafer(110). The wafer includes a plurality of semiconductor chips. The semiconductor chips are arranged on an upper surface of the wafer. A polyimide layer with adhesive strength is formed on each of the semiconductor chips. The semiconductor chips are separated from each other by cutting the wafer(120). A package substrate preparation process is performed to prepare a package substrate(130). The semiconductor chips are mounted on the package substrate. The semiconductor chips are attached through the polyimide layer onto the package substrate(140). The polyimide layer is cured(150).

Description

접착력이 있는 폴리이미드층을 이용한 반도체 칩의 접착 및 적층 방법{ATTACHING AND STACKING METHOD OF SEMICONDUCTOR CHIP USING POLYIMIDE LAYER WITH ADHESIVE STRENGTH} ATTACHING AND STACKING METHOD OF SEMICONDUCTOR CHIP USING POLYIMIDE LAYER WITH ADHESIVE STRENGTH}

도 1은 종래기술에 따른 반도체 칩의 접착 방법을 나타내는 순서도이다. 1 is a flowchart illustrating a method of bonding a semiconductor chip according to the prior art.

도 2는 종래기술에 따른 반도체 칩의 적층 방법을 나타내는 순서도이다. 2 is a flowchart illustrating a method of stacking a semiconductor chip according to the related art.

도 3은 본 발명의 실시예에 따른 반도체 칩의 접착 방법을 나타내는 순서도이다. 3 is a flowchart illustrating a method of bonding a semiconductor chip according to an embodiment of the present invention.

도 4 내지 도 6은 본 발명의 실시예에 따른 반도체 칩의 접착 방법의 각 단계를 나타내는 도면들이다.4 to 6 are diagrams illustrating each step of a method of bonding a semiconductor chip according to an embodiment of the present invention.

도 7은 본 발명의 실시예에 따른 반도체 칩의 접착 방법에 의해 제조된 반도체 패키지를 나타내는 단면도이다. 7 is a cross-sectional view illustrating a semiconductor package manufactured by a method of bonding a semiconductor chip according to an embodiment of the present invention.

도 8은 본 발명의 다른 실시예에 따른 반도체 칩의 접착 방법에 의해 제조된 반도체 패키지를 나타내는 단면도이다. 8 is a cross-sectional view illustrating a semiconductor package manufactured by a method of bonding a semiconductor chip according to another embodiment of the present invention.

도 9는 본 발명의 실시예에 따른 반도체 칩의 적층 방법을 나타내는 순서도이다. 9 is a flowchart illustrating a method of stacking semiconductor chips in accordance with an embodiment of the present invention.

도 10은 본 발명의 실시예에 따른 반도체 칩의 적층 방법에 의해 제조된 적층 칩 패키지를 나타내는 단면도이다. 10 is a cross-sectional view illustrating a stacked chip package manufactured by a method of stacking semiconductor chips according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 웨이퍼(wafer)1: wafer

2 : 웨이퍼 몸체(wafer body)2: wafer body

3 : 칩 절단 영역(scribe line)3: scribe line

4, 74 : 반도체 칩(semiconductor chip)4, 74: semiconductor chip

5, 75 : 칩 몸체(chip body)5, 75: chip body

6, 76 : 칩 패드(chip pad)6, 76: chip pad

7, 77 : 폴리이미드층(polyimide layer)7, 77: polyimide layer

10, 80 : 인쇄회로기판(printed circuit board)10, 80: printed circuit board

11 : 기판 몸체(board body)11: board body

12 : 윈도우(window)12: window

13 : 금속 배선층(metal wiring layer)13 metal wiring layer

14, 84 : 기판 패드(board pad)14, 84: board pad

15, 85 : 단자 패드(terminal pad)15, 85: terminal pad

16 : 포토 솔더 레지스트층(photo solder resist layer)16: photo solder resist layer

40 : 리드 프레임(lead frame)40: lead frame

41 : 내부 리드(inner lead)41: inner lead

42 : 외부 리드(outer lead)42: outer lead

21, 51, 91 : 본딩 와이어(bonding wire)21, 51, 91: bonding wire

22, 52, 92 : 수지 봉합부(resin molding portion)22, 52, 92: resin molding portion

23, 93 : 솔더 볼(solder ball)23, 93: solder ball

94 : 접착층(adhesive layer)94: adhesive layer

30, 60, 100 : 반도체 패키지(semiconductor package)30, 60, 100: semiconductor package

본 발명은 반도체 칩의 접착 및 적층 방법에 관한 것으로, 더욱 상세하게는 반도체 칩을 패키지 기판에 접착시키거나 복수개의 반도체 칩들을 적층할 수 있는 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 접착 및 적층 방법에 관한 것이다. The present invention relates to a method of adhering and stacking semiconductor chips, and more particularly, to adhering and laminating semiconductor chips using an adhesive polyimide layer capable of adhering a semiconductor chip to a package substrate or stacking a plurality of semiconductor chips. It is about a method.

일반적으로, 반도체 소자의 제조에 있어서, 칩 접착 공정(chip attaching process)은 반도체 칩을 리드 프레임, 인쇄회로기판 또는 테이프 배선기판(tape circuit board) 등과 같은 패키지 기판(package board)에 접착하는 공정을 말한다. In general, in the manufacture of semiconductor devices, a chip attaching process is a process of adhering a semiconductor chip to a package board such as a lead frame, a printed circuit board, or a tape circuit board. Say.

종래기술에 따른 반도체 칩의 접착 방법은, 도 1에 도시된 바와 같이, 웨이퍼 제공 단계(210), 반도체 칩 분리 단계(220), 패키지 기판 준비 단계(230), 접착 수단 개재 단계(235), 접착 단계(240) 및 경화 단계(250)를 포함하여 구성된다. 즉, 패키지 기판에 접착 수단을 개재한 다음, 접착 수단을 매개로 반도체 칩을 패키지 기판에 접착시킨다. As shown in FIG. 1, the method for bonding a semiconductor chip according to the related art includes a wafer providing step 210, a semiconductor chip separating step 220, a package substrate preparing step 230, and an adhesion means interposing step 235. It comprises a bonding step 240 and a curing step 250. In other words, the semiconductor chip is adhered to the package substrate via the bonding means, and then the semiconductor chip is adhered to the package substrate.

또한, 접착 수단은 반도체 칩을 패키지 기판에 접착시키는 경우 뿐만 아니라, 반도체 칩을 3차원으로 적층하는 경우에도 사용된다. In addition, the bonding means is used not only for bonding the semiconductor chip to the package substrate but also for stacking the semiconductor chip in three dimensions.

종래기술에 따른 반도체 칩의 적층 방법은, 도 2에 도시된 바와 같이, 하부 웨이퍼 제공 단계(260), 상부 웨이퍼 제공 단계(270), 상하부 반도체 칩 분리 단계(280), 접착 수단 개재 단계(285), 접착 단계(290) 및 경화 단계(300)를 포함하여 구성된다. 즉, 접착 수단을 하부 반도체 칩 상에 개재한 다음, 접착 수단을 매개로 상부 반도체 칩을 하부 반도체 칩에 접착시킨다. As shown in FIG. 2, the semiconductor chip stacking method according to the related art includes a lower wafer providing step 260, an upper wafer providing step 270, an upper and lower semiconductor chip separating step 280, and a bonding means interposing step 285. ), An adhesive step 290 and a curing step 300. That is, the bonding means is interposed on the lower semiconductor chip, and then the upper semiconductor chip is bonded to the lower semiconductor chip through the bonding means.

이 때, 종래의 칩 접착 및 적층 공정에 사용되는 접착 수단으로는 은-에폭시(Ag-epoxy)나 은-글래스(Ag-glass) 또는 솔더(solder)와 같은 전도성인 액상 접착제나 에폭시(epoxy)나 실리콘(silicon) 계열의 비전도성인 액상 접착제 또는 필름(film) 형태의 비전도성인 접착 테이프가 있다. At this time, the adhesive means used in the conventional chip bonding and lamination process is a conductive liquid adhesive or epoxy, such as silver-epoxy, silver-glass or solder Or silicone-based non-conductive liquid adhesives or film-type non-conductive adhesive tapes.

그런데, 이러한 접착 수단은 고가(高價)이기 때문에, 접착 수단을 이용하여 반도체 칩을 접착 또는 적층하는 공정에 고비용이 소요되는 문제가 발생된다. However, since such bonding means are expensive, a problem arises in that a high cost is required for the process of bonding or laminating semiconductor chips using the bonding means.

또한, 패키지 기판에 접착되거나 적층되는 반도체 칩의 수에 대응되도록 접착 수단 개재 단계가 반복되기 때문에, 반도체 칩을 접착 또는 적층하는 공정에 장시간이 소요되는 문제가 발생된다. In addition, since the step of interposing the adhesive means is repeated so as to correspond to the number of semiconductor chips bonded or stacked on the package substrate, a problem that takes a long time in the process of bonding or laminating the semiconductor chips occurs.

따라서, 본 발명의 목적은, 반도체 칩을 접착 또는 적층하는 공정에 소요되는 비용을 절감시키고, 공정 시간을 단축시킬 수 있는 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 접착 및 적층 방법을 제공하는 데 있다. Accordingly, an object of the present invention is to provide a method for adhering and laminating semiconductor chips using an adhesive polyimide layer that can reduce the cost of the process of adhering or laminating semiconductor chips and shorten the process time. have.

상기 목적을 달성하기 위하여, 본 발명은 다음과 같은 구성의 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 접착 방법을 제공한다. In order to achieve the above object, the present invention provides a method for bonding a semiconductor chip using an adhesive polyimide layer having the following configuration.

본 발명에 따른 반도체 칩의 접착 방법은, (a) 접착력이 있는 폴리이미드층이 형성된 복수개의 반도체 칩들이 배열된 웨이퍼를 제공하는 단계와, (b) 웨이퍼를 절단하여 반도체 칩들을 개별적으로 분리하는 단계와, (c) 반도체 칩이 실장될 패키지 기판을 준비하는 단계와, (d) 패키지 기판에 반도체 칩을 폴리이미드층을 매개로 접착시키는 단계와, (e) 폴리이미드층을 완전 경화시키는 단계를 포함한다. The method of adhering a semiconductor chip according to the present invention comprises the steps of: (a) providing a wafer in which a plurality of semiconductor chips having an adhesive polyimide layer are arranged; and (b) cutting the wafer to separate the semiconductor chips individually. (C) preparing a package substrate on which the semiconductor chip is to be mounted, (d) bonding the semiconductor chip to the package substrate through a polyimide layer, and (e) completely curing the polyimide layer. It includes.

본 발명에 따른 반도체 칩의 접착 방법에 있어서, (a) 단계는, (a1) 집적 회로가 내재된 복수개의 칩 몸체들과, 집적회로와 접속되어 칩 몸체들의 상부면에 형성된 복수개의 칩 패드들을 갖는 웨이퍼 몸체를 준비하는 단계와, (a2) 웨이퍼 몸체의 상부면에 폴리이미드를 도포하는 단계와, (a3) 폴리이미드를 1차 불완전 경화시켜 제 1차 폴리이미드층을 형성하는 단계와, (a4) 제 1차 폴리이미드층에 자외선을 조사하는 단계와, (a5) 제 1차 폴리이미드층을 2차 불완전 경화시켜 제 2차 폴리이미드층을 형성하는 단계와, (a6) 제 2차 폴리이미드층으로부터 칩 패드들을 노출시키는 단계를 포함한다. In the method of bonding a semiconductor chip according to the present invention, step (a) comprises: (a1) a plurality of chip bodies incorporating an integrated circuit and a plurality of chip pads connected to the integrated circuit and formed on the upper surfaces of the chip bodies; (A2) applying a polyimide to the upper surface of the wafer body, (a3) forming a first polyimide layer by primary incomplete curing of (a3) a4) irradiating ultraviolet rays to the primary polyimide layer, (a5) secondary incomplete curing of the primary polyimide layer to form a secondary polyimide layer, and (a6) secondary polyis Exposing the chip pads from the mid layer.

한편, 본 발명은 다음과 같은 구성의 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 적층 방법을 제공한다. On the other hand, the present invention provides a method for laminating a semiconductor chip using an adhesive polyimide layer having the following structure.

본 발명에 따른 반도체 칩의 적층 방법은, (a) 접착력이 있는 하부 폴리이미드층이 형성된 복수개의 하부 반도체 칩들이 배열된 하부 웨이퍼를 제공하는 단계와, (b) 하부 반도체 칩 상에 적층될 복수개의 상부 반도체 칩들이 배열된 상부 웨이퍼를 제공하는 단계와, (c) 상부 웨이퍼와 하부 웨이퍼를 절단하여 상부 반도체 칩들과 하부 반도체 칩들을 개별적으로 분리하는 단계와, (d) 하부 반도체 칩 상에 상부 반도체 칩을 하부 폴리이미드층을 매개로 접착시키는 단계와, (e) 하부 폴리이미드층을 완전 경화시키는 단계를 포함한다. The stacking method of a semiconductor chip according to the present invention comprises the steps of: (a) providing a lower wafer on which a plurality of lower semiconductor chips with an adhesive lower polyimide layer are formed; and (b) a plurality of lower semiconductor chips to be stacked on the lower semiconductor chip. Providing an upper wafer having two upper semiconductor chips arranged; (c) cutting the upper wafer and the lower wafer to separate the upper semiconductor chips and the lower semiconductor chips separately, and (d) the upper part on the lower semiconductor chip. Bonding the semiconductor chip through the lower polyimide layer, and (e) completely curing the lower polyimide layer.

본 발명에 따른 반도체 칩의 적층 방법에 있어서, (a) 단계는, (a1) 집적회로가 내재된 복수개의 칩 몸체들과, 집적회로와 접속되어 칩 몸체들의 상부면에 형성된 복수개의 칩 패드들을 갖는 하부 웨이퍼 몸체를 준비하는 단계와, (a2) 하부 웨이퍼 몸체의 하부면에 폴리이미드를 도포하는 단계와, (a3) 폴리이미드를 1차 불완전 경화시켜 제 1차 폴리이미드층을 형성하는 단계와, (a4) 제 1차 폴리이미드층에 자외선을 조사하는 단계와, (a5) 제 1차 폴리이미드층을 2차 불완전 경화시켜 제 2차 폴리이미드층을 형성하는 단계와, (a6) 제 2차 폴리이미드층으로부터 칩 패드들을 노출시키는 단계를 포함한다. In the stacking method of a semiconductor chip according to the present invention, the step (a) comprises: (a1) a plurality of chip bodies in which an integrated circuit is embedded, and a plurality of chip pads connected to the integrated circuit and formed on upper surfaces of the chip bodies. Preparing a lower wafer body, (a2) applying a polyimide to the lower surface of the lower wafer body, (a3) forming a first polyimide layer by primary incomplete curing of the polyimide; (a4) irradiating ultraviolet rays to the primary polyimide layer, (a5) secondary incomplete curing of the primary polyimide layer to form a secondary polyimide layer, and (a6) a second Exposing chip pads from the primary polyimide layer.

본 발명에 따른 반도체 칩의 적층 방법에 있어서, (b) 단계는, (b1) 집적회로가 내재된 복수개의 칩 몸체들과, 집적회로와 접속되어 칩 몸체들의 상부면에 형성된 복수개의 칩 패드들을 갖는 상부 웨이퍼 몸체를 준비하는 단계와, (b2) 웨이퍼 몸체의 상부면에 폴리이미드를 도포하는 단계와, (b3) 폴리이미드를 불완전 경화시켜 폴리이미드층을 형성하는 단계와, (b4) 상부 폴리이미드층으로부터 칩 패드들을 노출시키는 단계를 포함할 수 있다. In the stacking method of a semiconductor chip according to the present invention, the step (b) comprises: (b1) a plurality of chip bodies incorporating an integrated circuit and a plurality of chip pads connected to the integrated circuit and formed on the upper surfaces of the chip bodies; Preparing a top wafer body having (b2) applying polyimide to the top surface of the wafer body, (b3) incompletely curing the polyimide to form a polyimide layer, and (b4) Exposing the chip pads from the mid layer.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다. Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 반도체 칩의 접착 방법을 나타내는 순서도 이다. 3 is a flowchart illustrating a method of bonding a semiconductor chip according to an embodiment of the present invention.

도 3을 참조하면, 본 발명의 실시예에 따른 반도체 칩의 접착 방법은 반도체 칩의 집적회로를 보호하는 폴리이미드층에 접착력을 부여하고, 접착 수단을 대신하여 폴리이미드층을 매개로 패키지 기판에 반도체 칩을 접착시키는 특징을 갖는다. 이러한 본 실시예에 따른 반도체 칩의 접착 방법은, 웨이퍼 제공 단계(110), 반도체 칩 분리 단계(120), 패키지 기판 준비 단계(130), 접착 단계(140) 및 완전 경화 단계(150)를 포함하여 구성된다. Referring to FIG. 3, in the method of adhering a semiconductor chip according to an embodiment of the present invention, an adhesive force is applied to a polyimide layer protecting an integrated circuit of the semiconductor chip, and the adhesive is applied to the package substrate through the polyimide layer instead of the adhesion means. It has the characteristic of adhering a semiconductor chip. The bonding method of the semiconductor chip according to the present embodiment includes a wafer providing step 110, a semiconductor chip separating step 120, a package substrate preparing step 130, an bonding step 140, and a complete curing step 150. It is configured by.

이와 같은 본 발명의 실시예에 따른 반도체 칩의 접착 방법의 각 단계 및 그에 의해 제조된 반도체 패키지를 도 4 내지 도 7을 참조하여 설명하면 다음과 같다. 여기서, 도 4 내지 도 6은 본 발명의 실시예에 따른 반도체 칩의 접착 방법의 각 단계를 나타내는 도면들이며, 도 7은 본 발명의 실시예에 따른 반도체 칩의 접착 방법에 의해 제조된 반도체 패키지를 나타내는 단면도이다. Each step of the method of adhering a semiconductor chip according to the embodiment of the present invention and the semiconductor package manufactured by the same will be described with reference to FIGS. 4 to 7 as follows. 4 to 6 are diagrams illustrating each step of a method for bonding a semiconductor chip according to an embodiment of the present invention, and FIG. 7 is a view illustrating a semiconductor package manufactured by a method for bonding a semiconductor chip according to an embodiment of the present invention. It is sectional drawing to show.

본 실시예의 접착 단계는, 도 4에 도시된 바와 같이, 접착력이 있는 폴리이미드층(7)이 형성된 복수개의 반도체 칩(4)들이 배열된 웨이퍼(1)를 제공하는 단계로부터 출발한다. The bonding step of this embodiment starts from providing a wafer 1 in which a plurality of semiconductor chips 4 on which an adhesive polyimide layer 7 is formed, as shown in FIG. 4.

먼저, 웨이퍼 몸체(2)를 준비하는 단계가 진행된다. 웨이퍼 몸체(2)는, 통상적인 제조 공정을 통하여, 집적회로(도시되지 않음)가 내재된 실리콘 소재의 복수개의 칩 몸체(5)들과, 집적회로와 접속되어 칩 몸체(5)들의 상부면에 형성된 복수개의 칩 패드(6)들을 포함하며, 이웃하는 칩 몸체(5)들을 구분하는 칩 절단 영역(3)을 더 포함하도록 제조된다. First, the step of preparing the wafer body 2 is performed. The wafer body 2 is, through a conventional manufacturing process, a plurality of chip bodies 5 of silicon material in which an integrated circuit (not shown) is embedded, and an upper surface of the chip bodies 5 connected to the integrated circuit. It comprises a plurality of chip pads (6) formed in the fabrication, and further comprises a chip cutting area (3) for separating the adjacent chip body (5).

다음으로, 폴리이미드(polyimide)를 도포하는 단계가 진행된다. 즉, 칩 패드(6)가 형성되어 있는 웨이퍼 몸체(2)의 상부면에 폴리이미드를 도포한다. Next, the step of applying a polyimide is carried out. That is, polyimide is applied to the upper surface of the wafer body 2 on which the chip pads 6 are formed.

다음으로, 제 1차 폴리이미드층(7)을 형성하는 단계가 진행된다. 즉, 폴리이미드를 열을 이용하여 1차 불완전 경화시켜 제 1차 폴리이미드층(7)을 형성한다. 이 때, 제 1차 폴리이미드층(7)은 폴리이미드의 유동성이 제어된 상태이다. Next, the step of forming the primary polyimide layer 7 proceeds. That is, the polyimide is primary incompletely cured using heat to form the primary polyimide layer 7. At this time, the primary polyimide layer 7 is in a state where the fluidity of the polyimide is controlled.

다음으로, 자외선(ultraviolet rays)을 조사한 다음, 제 2차 폴리이미드층(7)을 형성하는 단계가 진행된다. 즉, 제 1차 폴리이미드층(7)에 자외선을 조사한 다음, 열을 이용하여 2차 불완전 경화시켜 제 2차 폴리이미드층(7)을 형성한다. 이러한 제 2차 폴리이미드층(7)은 일정 크기의 접착력을 갖는다. Next, after irradiating ultraviolet rays (ultraviolet rays), the step of forming the secondary polyimide layer 7 is performed. That is, the first polyimide layer 7 is irradiated with ultraviolet rays, and then secondly incompletely cured using heat to form the second polyimide layer 7. This secondary polyimide layer 7 has an adhesive strength of a certain size.

다음으로, 칩 패드(6)들을 노출시키는 단계가 진행된다. 즉, 제 2차 폴리이미드층(7)으로부터 칩 패드(6)들을 노출시킴으로써, 접착력이 있는 폴리이미드층(7)이 형성된 반도체 칩(4)들이 배열된 웨이퍼(1)를 얻을 수 있다. Next, the step of exposing the chip pads 6 proceeds. That is, by exposing the chip pads 6 from the secondary polyimide layer 7, the wafer 1 in which the semiconductor chips 4 on which the adhesive polyimide layer 7 is formed is arranged can be obtained.

이어서, 웨이퍼(1)의 제조가 완료되면, 도 5에 도시된 바와 같이, 반도체 칩(4)을 분리하는 단계가 진행된다. 즉, 칩 절단 영역(3)을 따라서 웨이퍼(1)를 절단하여, 반도체 칩(4)들을 개별적으로 분리한다. Subsequently, when manufacturing of the wafer 1 is completed, as shown in FIG. 5, the step of separating the semiconductor chip 4 is performed. That is, the wafer 1 is cut along the chip cutting region 3 to separate the semiconductor chips 4 individually.

계속해서, 도 6에 도시된 바와 같이, 인쇄회로기판(10)을 준비하여 반도체 칩(4)을 접착시키는 단계가 진행된다. 인쇄회로기판(10)은 윈도우(12)가 형성된 기판 몸체(11)에 금속 배선층(13)이 배선되고, 기판 패드(14)와 단자 패드(15)를 제외한 금속 배선층(13) 상에 포토 솔더 레지스트층(16)이 덮여 있는 구조를 갖는다. 이 때, 기판 패드(14)와 단자 패드(15)는 인쇄회로기판(10)의 일면에 배열되며, 인 쇄회로기판(10)의 타면은 칩 실장 영역으로 이용된다. 즉, 반도체 칩(4)을 폴리이미드층(7)을 매개로 인쇄회로기판(10)의 칩 실장 영역에 접착시킨다. 이러한 반도체 칩(4)과 인쇄회로기판(10)의 접착은 열압착(thermo-compression)에 의해 이루어질 수 있다. Subsequently, as shown in FIG. 6, the step of preparing the printed circuit board 10 and adhering the semiconductor chip 4 is performed. In the printed circuit board 10, a metal wiring layer 13 is wired to a substrate body 11 having a window 12 formed thereon, and photo solder is formed on the metal wiring layer 13 except for the substrate pad 14 and the terminal pad 15. It has a structure in which the resist layer 16 is covered. In this case, the substrate pad 14 and the terminal pad 15 are arranged on one surface of the printed circuit board 10, and the other surface of the printed circuit board 10 is used as a chip mounting area. That is, the semiconductor chip 4 is bonded to the chip mounting region of the printed circuit board 10 via the polyimide layer 7. The adhesion between the semiconductor chip 4 and the printed circuit board 10 may be performed by thermo-compression.

마지막으로, 폴리이미드층(7)을 완전 경화시킴으로써, 반도체 칩(4)과 인쇄회로기판(10)의 접착 상태를 유지시킨다. 이와 같이, 폴리이미드층(7)은 반도체 칩(4)의 집적회로를 외부로부터 보호할 뿐만 아니라, 반도체 칩(4)을 인쇄회로기판(10)에 접착시키는 접착 수단으로서의 역할을 한다. Finally, the polyimide layer 7 is completely cured to maintain the adhesion state between the semiconductor chip 4 and the printed circuit board 10. As described above, the polyimide layer 7 not only protects the integrated circuit of the semiconductor chip 4 from the outside but also serves as an adhesive means for adhering the semiconductor chip 4 to the printed circuit board 10.

한편, 이와 같은 구성의 반도체 칩(4)의 접착 방법에 의해 제조된 반도체 패키지(30)는, 도 7에 도시된 바와 같이, 반도체 칩(4)이 폴리이미드층(7)을 매개로 인쇄회로기판(10)에 접착되고, 반도체 칩(4)의 칩 패드(6)와 인쇄회로기판(10)의 기판 패드(14)가 본딩 와이어(21)에 의해 전기적으로 연결된 구조를 갖는다. 또한, 칩 패드(6), 기판 패드(14) 및 본딩 와이어(21)는 수지 봉합부(22)에 의해 봉합되며, 단자 패드(15)에는 외부 접속 단자(externally connecting terminal)로서 솔더 볼(23)이 형성되어 있다. On the other hand, in the semiconductor package 30 manufactured by the bonding method of the semiconductor chip 4 having such a configuration, as shown in FIG. 7, the semiconductor chip 4 is a printed circuit via the polyimide layer 7 as a medium. Bonded to the substrate 10, the chip pad 6 of the semiconductor chip 4 and the substrate pad 14 of the printed circuit board 10 are electrically connected by the bonding wire 21. In addition, the chip pad 6, the substrate pad 14, and the bonding wire 21 are sealed by the resin sealing portion 22, and the terminal pad 15 is solder ball 23 as an externally connecting terminal. ) Is formed.

한편, 전술한 실시예에서는 패키지 기판으로 인쇄회로기판을 이용한 반도체 칩의 접착 방법에 대해서만 개시하였으나, 다양한 종류의 패키지 기판을 이용하여 본 발명의 반도체 칩의 접착 방법을 구현할 수 있다. 도 8은 그러한 예로서, 도 8은 본 발명의 다른 실시예에 따른 반도체 칩의 접착 방법에 의해 제조된 반도체 패키지를 나타내는 단면도이다. Meanwhile, in the above-described embodiment, only the bonding method of the semiconductor chip using the printed circuit board as the package substrate is disclosed, but the bonding method of the semiconductor chip of the present invention may be implemented using various kinds of package substrates. 8 is an example, and FIG. 8 is a cross-sectional view illustrating a semiconductor package manufactured by a method of bonding a semiconductor chip according to another exemplary embodiment of the present disclosure.

도 8을 참조하면, 반도체 칩(4)의 접착 방법의 기본 구성은 전술한 실시예의 반도체 칩(4)의 접착 방법과 동일하다. 다만, 본 실시예의 반도체 칩(4)의 접착 방법은 반도체 칩(4)을 리드 프레임(40)에 접착시킨다. 8, the basic configuration of the bonding method of the semiconductor chip 4 is the same as the bonding method of the semiconductor chip 4 of the above-described embodiment. However, in the bonding method of the semiconductor chip 4 of the present embodiment, the semiconductor chip 4 is bonded to the lead frame 40.

즉, 본 발명의 다른 실시예에 따르면, 반도체 칩(4)을 접착력이 있는 폴리이미드층(7)을 매개로 리드 프레임(40)에 접착시키는 구성을 갖는다. 이 때, 리드 프레임(40)은 반도체 칩(4)이 실장되는 내부 리드(41)들과 내부 리드(41)들로부터 연장된 외부 리드(42)들을 포함한다. 이에 따라, 리드 프레임(40)을 이용하여 제조된 반도체 패키지(60)는, 반도체 칩(4)이 폴리이미드층(7)을 매개로 내부 리드(41)의 일면에 접착되고, 반도체 칩(4)의 칩 패드(6)와 내부 리드(41)의 타면이 본딩 와이어(51)에 의해 전기적으로 연결된 구조를 갖는다. 또한, 반도체 칩(4), 내부 리드(41) 및 본딩 와이어(51)는 수지 봉합부(52)에 의해 봉합되며, 수지 봉합부(52)의 외부로 외부 리드(42)가 돌출되어 있다. That is, according to another embodiment of the present invention, the semiconductor chip 4 is bonded to the lead frame 40 through the polyimide layer 7 having the adhesive force. At this time, the lead frame 40 includes internal leads 41 on which the semiconductor chip 4 is mounted and external leads 42 extending from the internal leads 41. Accordingly, in the semiconductor package 60 manufactured using the lead frame 40, the semiconductor chip 4 is adhered to one surface of the internal lead 41 via the polyimide layer 7, and the semiconductor chip 4 is formed. Chip pad 6 and the other surface of the inner lead 41 are electrically connected by the bonding wire 51. In addition, the semiconductor chip 4, the inner lead 41, and the bonding wire 51 are sealed by the resin sealing part 52, and the outer lead 42 protrudes outside the resin sealing part 52. As shown in FIG.

한편, 전술한 반도체 칩의 접착 방법에서는 반도체 칩을 패키지 기판에 접착시키는 방법에 대해서만 개시하였으나, 접착력이 있는 폴리이미드층을 이용하여 복수개의 반도체 칩을 적층할 수도 있다. 도 9 및 도 10은 그러한 예로서, 도 9는 본 발명의 실시예에 따른 반도체 칩의 적층 방법을 나타내는 순서도이고, 도 10은 본 발명의 실시예에 따른 반도체 칩의 적층 방법에 의해 제조된 적층 칩 패키지를 나타내는 단면도이다. On the other hand, in the above-described method of bonding the semiconductor chip, only the method of adhering the semiconductor chip to the package substrate is disclosed, but a plurality of semiconductor chips may be laminated using a polyimide layer having adhesive force. 9 and 10 are examples thereof, and FIG. 9 is a flowchart illustrating a method of stacking semiconductor chips according to an embodiment of the present invention, and FIG. 10 is a stack manufactured by a method of stacking semiconductor chips according to an embodiment of the present invention. It is sectional drawing which shows a chip package.

도 9를 참조하면, 본 발명의 실시예에 따른 반도체 칩의 적층 방법은 하부 반도체 칩의 하부 폴리이미드층에 접착력을 부여하고, 접착 수단을 대신하여 하부 폴리이미드층을 매개로 하부 반도체 칩에 상부 반도체 칩을 적층하는 특징을 갖는다. 이러한 본 실시예에 따른 반도체 칩의 적층 방법은, 하부 웨이퍼 제공 단계(160), 상부 웨이퍼 제공 단계(170), 상하부 반도체 칩 분리 단계(180), 접착 단계(190) 및 완전 경화 단계(200)를 포함하여 구성된다. 이 때, 하부 웨이퍼 제공 단계(160) 및 상부 웨이퍼 제공 단계(170)는 전술한 바 있는 웨이퍼 제공 단계(도 3의 110)와 동일한 구성을 가지며, 상부 웨이퍼 제공 단계(170)의 경우에는 공지기술인 웨이퍼 제조 공정과 동일한 구성을 가질 수도 있다. 9, in the stacking method of a semiconductor chip according to an exemplary embodiment of the present invention, an adhesive force is applied to a lower polyimide layer of a lower semiconductor chip, and an upper portion of the lower semiconductor chip is replaced by a lower polyimide layer instead of an adhesive means. The semiconductor chip is laminated. The stacking method of the semiconductor chip according to the present exemplary embodiment may include a lower wafer providing step 160, an upper wafer providing step 170, an upper and lower semiconductor chip separating step 180, an adhesive step 190, and a complete curing step 200. It is configured to include. At this time, the lower wafer providing step 160 and the upper wafer providing step 170 has the same configuration as the wafer providing step (110 of FIG. 3) described above, in the case of the upper wafer providing step 170, It may have the same configuration as the wafer fabrication process.

이와 같은 본 발명의 실시예에 따른 반도체 칩의 적층 방법에 의해 제조된 반도체 패키지를 도 10을 참조하여 설명하면 다음과 같다. The semiconductor package manufactured by the semiconductor chip stacking method according to the embodiment of the present invention will be described with reference to FIG. 10 as follows.

도 10을 참조하면, 반도체 패키지(100)는, 인쇄회로기판(80) 상에 접착층(94)을 매개로 실장되어 있는 하부 반도체 칩(4) 상에 하부 폴리이미드층(7)을 매개로 상부 반도체 칩(74)이 적층된 구조를 갖는다. 이 때, 상하부 반도체 칩들(4, 74)의 칩 패드들(6, 76)은 인쇄회로기판(80) 상부면의 기판 패드(84)와 본딩 와이어(91)에 의해 전기적으로 연결된다. 또한, 상하부 반도체 칩들(4, 74)과 본딩 와이어(91)는 인쇄회로기판(80)의 상부에 형성되는 수지 봉합부(92)에 의해 봉합되며, 인쇄회로기판(80) 하부면의 단자 패드(85)에는 외부 접속 단자로서 솔더 볼(93)이 형성되어 있다. Referring to FIG. 10, the semiconductor package 100 is formed on the printed circuit board 80 via the lower polyimide layer 7 on the lower semiconductor chip 4 mounted on the printed circuit board 80 via the adhesive layer 94. The semiconductor chip 74 has a stacked structure. In this case, the chip pads 6 and 76 of the upper and lower semiconductor chips 4 and 74 are electrically connected to each other by the bonding pad 91 and the substrate pad 84 of the upper surface of the printed circuit board 80. In addition, the upper and lower semiconductor chips 4 and 74 and the bonding wire 91 are sealed by a resin encapsulation unit 92 formed on an upper portion of the printed circuit board 80, and the terminal pad of the lower surface of the printed circuit board 80 is sealed. The solder ball 93 is formed in the 85 as an external connection terminal.

따라서, 본 발명의 구조를 따르면, 반도체 칩의 집적회로를 보호하는 폴리이미드층에 접착력을 부여함으로써, 반도체 칩을 접착력이 있는 폴리이미드층을 매개 로 패키지 기판에 접착시키거나, 다른 반도체 칩에 적층시킬 수 있다. Therefore, according to the structure of the present invention, by attaching the adhesive force to the polyimide layer that protects the integrated circuit of the semiconductor chip, the semiconductor chip is adhered to the package substrate via the adhesive polyimide layer or laminated to another semiconductor chip. You can.

이로 인하여, 반도체 칩을 패키지 기판에 접착시키거나, 다른 반도체 칩에 적층시키는 경우, 고가의 접착 수단을 이용할 필요가 없기 때문에, 반도체 칩의 접착 또는 적층 공정에 소요되는 비용을 절감할 수 있다. For this reason, when bonding a semiconductor chip to a package board | substrate or laminating | stacking on another semiconductor chip, it is not necessary to use expensive adhesion means, and the cost of the bonding or lamination process of a semiconductor chip can be reduced.

더욱이, 접착 수단 개재 단계가 제거됨에 따라서 반도체 칩의 접착 또는 적층 공정이 단순화됨으로써, 반도체 칩의 접착 또는 적층 공정에 소요되는 시간을 단축할 수 있다. Furthermore, as the bonding step is removed, the bonding or laminating process of the semiconductor chip is simplified, thereby reducing the time required for the bonding or laminating process of the semiconductor chip.

Claims (5)

(a) 접착력이 있는 폴리이미드층이 형성된 복수개의 반도체 칩들이 배열된 웨이퍼를 제공하는 단계;(a) providing a wafer in which a plurality of semiconductor chips with an adhesive polyimide layer are formed; (b) 상기 웨이퍼를 절단하여 반도체 칩들을 개별적으로 분리하는 단계;(b) cutting the wafer to separate semiconductor chips individually; (c) 상기 반도체 칩이 실장될 패키지 기판을 준비하는 단계;(c) preparing a package substrate on which the semiconductor chip is to be mounted; (d) 상기 패키지 기판에 상기 반도체 칩을 상기 폴리이미드층을 매개로 접착시키는 단계; 및(d) adhering the semiconductor chip to the package substrate via the polyimide layer; And (e) 상기 폴리이미드층을 완전 경화시키는 단계;를 포함하는 것을 특징으로 하는 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 접착 방법. (e) completely curing the polyimide layer; and a method of adhering a semiconductor chip using an adhesive polyimide layer, characterized in that it comprises a. 제 1항에 있어서, 상기 (a) 단계는, The method of claim 1, wherein step (a) comprises: (a1) 집적회로가 내재된 복수개의 칩 몸체들과, 상기 집적회로와 접속되어 상기 칩 몸체들의 상부면에 형성된 복수개의 칩 패드들을 갖는 웨이퍼 몸체를 준비하는 단계;(a1) preparing a wafer body having a plurality of chip bodies incorporating an integrated circuit and a plurality of chip pads connected to the integrated circuit and formed on upper surfaces of the chip bodies; (a2) 상기 웨이퍼 몸체의 상부면에 폴리이미드를 도포하는 단계;(a2) applying polyimide to the upper surface of the wafer body; (a3) 상기 폴리이미드를 1차 불완전 경화시켜 제 1차 폴리이미드층을 형성하는 단계;(a3) forming a primary polyimide layer by primary incomplete curing of the polyimide; (a4) 상기 제 1차 폴리이미드층에 자외선을 조사하는 단계;(a4) irradiating ultraviolet rays to the first polyimide layer; (a5) 상기 제 1차 폴리이미드층을 2차 불완전 경화시켜 제 2차 폴리이미드층 을 형성하는 단계; 및(a5) forming a second polyimide layer by secondary incompletely curing the first polyimide layer; And (a6) 상기 제 2차 폴리이미드층으로부터 상기 칩 패드들을 노출시키는 단계;를 포함하는 것을 특징으로 하는 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 접착 방법. (a6) exposing the chip pads from the second polyimide layer; a method of adhering a semiconductor chip using an adhesive polyimide layer, comprising: a. (a) 접착력이 있는 하부 폴리이미드층이 형성된 복수개의 하부 반도체 칩들이 배열된 하부 웨이퍼를 제공하는 단계;(a) providing a lower wafer comprising a plurality of lower semiconductor chips having an adhesive lower polyimide layer formed thereon; (b) 상기 하부 반도체 칩 상에 적층될 복수개의 상부 반도체 칩들이 배열된 상부 웨이퍼를 제공하는 단계;(b) providing an upper wafer on which a plurality of upper semiconductor chips to be stacked on the lower semiconductor chip are arranged; (d) 상기 상부 웨이퍼와 상기 하부 웨이퍼를 절단하여 상기 상부 반도체 칩들과 상기 하부 반도체 칩들을 개별적으로 분리하는 단계;(d) cutting the upper wafer and the lower wafer to separately separate the upper semiconductor chips and the lower semiconductor chips; (e) 상기 하부 반도체 칩 상에 상기 상부 반도체 칩을 상기 하부 폴리이미드층을 매개로 접착시키는 단계; 및(e) adhering the upper semiconductor chip to the lower semiconductor chip through the lower polyimide layer; And (f) 상기 하부 폴리이미드층을 완전 경화시키는 단계;를 포함하는 것을 특징으로 하는 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 적층 방법. (f) completely curing the lower polyimide layer; and a method of laminating a semiconductor chip using an adhesive polyimide layer, characterized in that it comprises a. 제 3항에 있어서, 상기 (a)단계는, The method of claim 3, wherein step (a) comprises: (a1) 집적회로가 내재된 복수개의 칩 몸체들과, 상기 집적회로가 접속되어 상기 칩 몸체들의 상부면에 형성된 복수개의 칩 패드들을 갖는 하부 웨이퍼 몸체를 준비하는 단계;(a1) preparing a lower wafer body having a plurality of chip bodies incorporating an integrated circuit and a plurality of chip pads connected to the integrated circuit and formed on upper surfaces of the chip bodies; (a2) 상기 하부 웨이퍼 몸체의 하부면에 폴리이미드를 도포하는 단계;(a2) applying polyimide to a lower surface of the lower wafer body; (a3) 상기 폴리이미드를 1차 불완전 경화시켜 제 1차 폴리이미드층을 형성하는 단계;(a3) forming a primary polyimide layer by primary incomplete curing of the polyimide; (a4) 상기 제 1차 폴리이미드층에 자외선을 조사하는 단계;(a4) irradiating ultraviolet rays to the first polyimide layer; (a5) 상기 제 1차 폴리이미드층을 2차 불완전 경화시켜 제 2차 폴리이미드층을 형성하는 단계; 및(a5) forming a second polyimide layer by secondary incompletely curing the first polyimide layer; And (a6) 상기 제 2차 폴리이미드층으로부터 상기 칩 패드들을 노출시키는 단계;를 포함하는 것을 특징으로 하는 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 적층 방법. (a6) exposing the chip pads from the second polyimide layer; a stacking method of a semiconductor chip using an adhesive polyimide layer, comprising: a. 제 3항에 있어서, 상기 (b) 단계는, The method of claim 3, wherein step (b) comprises: (b1) 집적회로가 내재된 복수개의 칩 몸체들과, 상기 집적회로와 접속되어 상기 칩 몸체의 상부면에 형성된 복수개의 칩 패드들을 갖는 상부 웨이퍼 몸체를 준비하는 단계;(b1) preparing an upper wafer body having a plurality of chip bodies incorporating an integrated circuit and a plurality of chip pads connected to the integrated circuit and formed on an upper surface of the chip body; (b2) 상기 웨이퍼 몸체의 상부면에 폴리이미드를 도포하는 단계;(b2) applying polyimide to the upper surface of the wafer body; (b3) 상기 폴리이미드를 불완전 경화시켜 상부 폴리이미드층을 형성하는 단계; 및(b3) incompletely curing the polyimide to form an upper polyimide layer; And (b4) 상기 상부 폴리이미드층으로부터 상기 칩 패드들을 노출시키는 단계;를 포함하는 것을 특징으로 하는 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 적층 방법. (b4) exposing the chip pads from the upper polyimide layer; and stacking the semiconductor chip using the adhesive polyimide layer.
KR1020060011539A 2006-02-07 2006-02-07 Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength KR20070080324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060011539A KR20070080324A (en) 2006-02-07 2006-02-07 Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060011539A KR20070080324A (en) 2006-02-07 2006-02-07 Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength

Publications (1)

Publication Number Publication Date
KR20070080324A true KR20070080324A (en) 2007-08-10

Family

ID=38600721

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060011539A KR20070080324A (en) 2006-02-07 2006-02-07 Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength

Country Status (1)

Country Link
KR (1) KR20070080324A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101518760B1 (en) * 2014-12-31 2015-05-08 주식회사 자이스 Attaching method for chip using conductive adhesive
CN117253779A (en) * 2023-11-17 2023-12-19 西安天光半导体有限公司 Back side glue brushing method of semiconductor wafer
CN117253780A (en) * 2023-11-17 2023-12-19 西安天光半导体有限公司 Glue brushing method for semiconductor wafer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101518760B1 (en) * 2014-12-31 2015-05-08 주식회사 자이스 Attaching method for chip using conductive adhesive
CN117253779A (en) * 2023-11-17 2023-12-19 西安天光半导体有限公司 Back side glue brushing method of semiconductor wafer
CN117253780A (en) * 2023-11-17 2023-12-19 西安天光半导体有限公司 Glue brushing method for semiconductor wafer
CN117253779B (en) * 2023-11-17 2024-01-23 西安天光半导体有限公司 Back side glue brushing method of semiconductor wafer
CN117253780B (en) * 2023-11-17 2024-01-23 西安天光半导体有限公司 Glue brushing method for semiconductor wafer

Similar Documents

Publication Publication Date Title
JP5161732B2 (en) Manufacturing method of semiconductor device
TWI421904B (en) Semiconductor memory device and manufacturing method thereof
US8358514B2 (en) Electronic control device
JP4188337B2 (en) Manufacturing method of multilayer electronic component
US20020109216A1 (en) Integrated electronic device and integration method
JPH07201918A (en) Semiconductor-device packaging method, lead-tape used therefor, and packaged semiconductor device
US9230948B2 (en) Method of manufacturing a semiconductor device
WO2006080351A9 (en) Semiconductor device and its manufacturing method
TWI575622B (en) :verfahren zur herstellung von halbleiter-bauelementen und entspreschendes halbleiter-bauelement:process to produce semiconductor components and corresponding semiconductor component
WO1998025302A1 (en) Semiconductor device sealed with resin, and its manufacture
KR20070080324A (en) Attaching and stacking method of semiconductor chip using polyimide layer with adhesive strength
TWI566343B (en) Chip package having protection piece compliantly attached on chip sensor surface
WO2000008685A1 (en) Wiring substrate, method of manufacture thereof, and semiconductor device
JP5396881B2 (en) Manufacturing method of electronic device
US20070114672A1 (en) Semiconductor device and method of manufacturing the same
JP4862986B2 (en) Manufacturing method of semiconductor device
JP5234703B2 (en) Manufacturing method of semiconductor device
JP4472481B2 (en) Semiconductor device, method of manufacturing the same, and stacked semiconductor device
JP2004335970A (en) Composite electronic component
US20230282536A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP4652428B2 (en) Semiconductor device and manufacturing method thereof
JP2005522028A (en) Semiconductor device packaging system
JP4473668B2 (en) Semiconductor device and manufacturing method thereof
KR20030045224A (en) A chip scale package manufactured by wire bonding method and a manufacturing method thereof
JP2008071847A (en) Manufacturing method for semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination