KR20070076791A - Displaying substrate - Google Patents

Abstract

A display substrate is provided to reduce an RC delay variation in a gate signal between upper and lower ends of a panel by inputting a clock signal to upper and lower ends of a clock line. A plurality of pixels are defined by gate lines and data lines. A gate circuit part(CS) outputs a gate signal to the gate lines. A line part(LS) is formed adjacently to the gate circuit part, and includes a first clock line(CLK1), a second clock line(CLK2), and a ground line(VSS). A first additional line(SL1) and a second additional line(SL2) are formed at one side of the line part. A first connection line(CL1) and a second connection line(CL2) electrically connect the first additional line with the first clock line, and a third connection line(CL3) and a fourth connection line(CL4) electrically connect the second additional line with the second clock line.

Description

Display board {DISPLAYING SUBSTRATE}

1 is a view schematically showing a display device according to the present invention.

2 is a schematic plan view of a portion of a display substrate according to a first exemplary embodiment of the present invention.

3 is a cross-sectional view taken along the line II-II ′ of FIG. 2.

4 is a schematic plan view of a portion of a display substrate according to a second exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along line III-III ′ of FIG. 4.

<Description of the symbols for the main parts of the drawings>

CLK1: first clock wiring CLK2: second clock wiring

VSS: Ground Wire SL1: First Additional Wiring

SL2: second additional wiring CL1: first connecting wiring

CL2: 2nd connection wiring CL3: 3rd connection wiring

CL4: 4th connection wiring IL1: 1st application wiring

IL2: second application wiring IL3: third application wiring

SRC1 to SRCn: Stage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device for improving delay variation of gate signals generated between upper and lower panels.

In general, the display device includes a display panel, a gate driver for outputting a gate signal to the gate wiring of the display panel, and a data driver for outputting a data signal to the data wiring of the display panel in synchronization with the gate signal. In general, the gate and data drivers are integrated to form a chip.

Recently, in order to reduce defects caused in the process of mounting the chip-type gate driver on the display panel, a structure in which a gate driver (for example, a gate driver circuit) is directly formed on the display panel is adopted.

The gate driving circuit includes a wiring portion consisting of a clock signal wiring, a clock bar signal wiring, and a ground wiring, and one shift register having a plurality of stages connected in a cascade, and outputs a gate signal in response to various signals provided from the wiring portion. It includes a circuit part. Each stage is electrically connected to the wirings through a plurality of connection wirings extending from the wirings.

A parasitic capacitance is generated between the plurality of connection wirings, the clock signal wiring, the clock bar signal wiring, and the ground wiring (for example, an overlap region), and an RC delay is generated between the clock signal and the clock bar signal by the parasitic capacitance. . Therefore, an RC delay is also generated in the gate signal output based on the clock signal and the clock bar signal. Since the RC delay has a cumulative characteristic, a deviation occurs in the RC delay of the gate signal between the upper and lower ends of the display panel.

Such RC delay variation has a problem of deteriorating a panel when applying a display device to larger size, higher resolution, and higher frequency driving.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display substrate for improving the RC delay deviation between the upper and lower ends of the gate signal.

According to an embodiment of the present invention, a display substrate includes a plurality of pixel parts, a gate circuit part, a wiring part, a first additional wire and a second additional wire, a first connection wire, a second connection wire, And a third connection wiring and a fourth connection wiring. The pixel units are defined by gate lines and data lines, and the gate circuit unit outputs a gate signal to the gate lines. The wiring portion is formed adjacent to the gate circuit portion and includes a first clock wiring, a second clock wiring, and a ground wiring. The first additional wiring and the second additional wiring are formed on one side of the wiring portion. The first connection wire and the second connection wire electrically connect the first additional wire and the first clock wire, and the third connection wire and the fourth connection wire electrically connect the second additional wire and the second clock wire. Connect.

According to such a display substrate, by applying the clock signal to the upper and lower ends of the clock wire, the RC delay variation of the clock signal between the upper and lower stages can be improved to improve the RC delay variation of the gate signal between the upper and lower stages.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a view schematically showing a display device according to the present invention.

As illustrated, the display device according to the present invention includes a display panel 300, a gate driver 200, and a data driver 100.

The data driver 100 includes a printed circuit board 110 on which a driving circuit is mounted, a flexible printed circuit board 120 electrically connecting the printed circuit board 110 and the display panel 300. The data driver chip 130 is mounted on the flexible printed circuit board 120 to output data signals to the data lines DL.

The display panel 300 includes first and second substrates 310 and 320 facing each other, and a liquid crystal layer (not shown) interposed between the first and second substrates 310 and 320, and the display area. And a non-display area PA surrounding the display area DA. A plurality of pixel parts are formed in the display area DA by gate lines and data lines GL and DL intersecting each other. Each pixel unit includes a thin film transistor TFT, a liquid crystal capacitor, and a storage capacitor CLC, CST, and the liquid crystal capacitor and the storage capacitor CLC, CST are electrically connected to the thin film transistor TFT.

The gate driver 200 is mounted in the non-display area PA of the first substrate 310 and is composed of one shift register in which a plurality of stages are cascaded to output a gate signal to the gate lines GL.

Hereinafter, display substrates (eg, first substrates) according to exemplary embodiments will be described in detail with reference to the accompanying drawings.

2 is a schematic plan view of a portion of a display substrate according to a first exemplary embodiment of the present invention.

1 and 2, a display substrate according to a first exemplary embodiment of the present invention may include a gate circuit part CS, a wiring part LS, first additional wirings and second additional wirings SL1 and SL2, and a first substrate. The connection wiring CL1, the second connection wiring CL2, the third connection wiring and the fourth connection wiring CL3 and CL4 are included.

The gate circuit CS includes a plurality of stages SRC1 to SRCn that are cascaded. Each stage SRC1 to SRCn is connected in one-to-one correspondence with the gate lines GL, and outputs a gate signal to the gate line GL based on the input clock signal. Specifically, odd-numbered stages receive a first clock signal, and even-numbered stages receive a second clock signal that is out of phase with the first clock signal (eg, 180 ° in phase difference). That is, odd-numbered stages output gate signals to odd-numbered gate lines GL based on the first clock signal, and even-numbered stages SRC are even-numbered gate lines GL based on the second clock signal. Outputs a gate signal. On the other hand, each stage (SRC1 ~ SRCn) receives the control signals including the ground voltage to drive sequentially.

The wiring part LS is formed adjacent to one side of the gate circuit part CS, and includes a first clock wire CLK1 to which a first clock signal is applied, a second clock wire CLK2 to which a second clock signal is applied, and a ground. And a ground line VSS to which a voltage is applied. The first clock line CLK1 provides a first clock signal to odd-numbered stages through the first application line IL1, and the second clock line CLK2 provides even-numbered stages through the second application line IL2. To provide a second clock signal. The ground line VSS provides a ground voltage to each of the stages SRC1 to SRCn through an extended third application line IL3.

The first additional wires and the second additional wires SL1 and SL2 are formed at one side of the wiring part LS, and the first additional wire SL1 is electrically connected to the first clock wire CLK1 and the second additional wires SL1 and SL2 are electrically connected to the first clock wire CLK1. The wiring SL2 is electrically connected to the second clock wire CLK2. In detail, the first additional wire SL1 is electrically connected to the first clock wire CLK1 through the first connection wire and the second connection wires CL1 and CL2, and the second additional wire SL2 is connected to the third wire. The second clock line CLK2 is electrically connected to each other through the connection line and the fourth connection line CL3 and CL4.

That is, the first to fourth connection wires CL1, CL2, CL3, and CL4 electrically connect the additional wires SL1 and SL2 and the clock wires CLK1 and CLK2, and the first and third connection wires ( CL1 and CL3 are connected to the upper ends of the first clock wire CLK1 and the second clock wire CLK2 (for example, before the foremost stage), and the second and fourth connection wires CL2 and CL4 are respectively connected. The first clock line CLK1 and the second clock line CLK2 are connected to lower ends (for example, after the last stage).

Therefore, the first clock signal is applied to the upper end of the first clock wire CLK and the first clock wire CLK1 through the first additional wire SL1, the first connection wire, and the second connection wires CL1 and CL2. It is also applied to the bottom of. Similarly, the second clock signal is applied to the upper end of the second clock wire CLK2 and the second clock wire CLK2 through the second additional wire SL2, the third connection wire, and the fourth connection wires CL3 and CL4. It is also applied to the bottom of. At this time, since the resistances of the additional wires SL1 and SL2 and the connection wires CL1, CL2, CL3, and CL4 have little influence on the clock signal, the first clock signal and the second clock signal may be respectively formed. The same applies to the upper and lower ends of the first clock wiring and the second clock wiring CLK1 and CLK2.

3 is a cross-sectional view taken along the line II-II ′ of FIG. 2.

2 and 3, a first clock wire CLK1, a second clock wire CLK2, a first additional wire SL1, a second additional wire SL2, a second connection wire, and a first connection wire are formed on a substrate. 4 The connection lines CL2 and CL4 are formed of the first metal material and formed in the first layer. The first application wiring IL1, the second application wiring IL2, the third application wiring IL3, and the ground wiring VSS are formed of a second metal material and formed on a second layer different from the first layer. The first connection line and the third connection line CL1 and CL3 are formed of a third metal material and formed on a third layer different from the first layer and the second layer.

Specifically, the first clock wiring CLK1, the second clock wiring CLK2, the first additional wiring SL1, the second additional wiring SL2, the second connection wiring, and the first connection wiring made of the first metal material on the substrate. Four connection lines CL2 and CL4 are formed. For example, the first metal material includes aluminum (AI) or an aluminum alloy. The second connection line CL2 extends from the first additional line SL1 to be directly connected to the first clock line CLK1, and the fourth connection line CL2 extends from the second additional line SL2. And directly connected to the second clock line CLK2. Thereafter, a gate insulating layer GI is formed over the entire surface of the substrate, such that the first clock wire CLK1, the second clock wire CLK2, the first additional wire SL1, the second additional wire SL2, and the second connection wire are formed. And the fourth connection lines CL2 and CL4 are covered by the gate insulating layer GI.

The ground wiring VSS, the first application wiring IL1, the second application wiring IL3, and the third application wiring IL2 and IL3 formed of the second metal material are formed on the gate insulating layer GI. The material includes chromium (Cr). In this case, although not illustrated, the first applied wiring IL1 is connected to the first clock wire CLK1 through an contact hole in which a part of the first clock wire CLK1 is exposed, and thus, the first clock wire CLK1 is odd-numbered with the first clock wire CLK1. Electrically connect the stage. In addition, the second application line IL2 is connected to the second clock line CLK2 through a contact hole exposing a part of the second clock line CLK2 to electrically connect the second clock line CLK2 and the even-numbered stage. Connect. The third application line IL3 extends from the ground line VSS to electrically connect the ground line VSS to each stage SRC1 to SRCn. The ground line VSS and the first to third application lines IL1, IL2, and IL3 are covered by the passivation layer PS formed over the entire surface of the substrate.

The first connection line and the third connection lines CL1 and CL3 made of a third metal material are formed on the passivation layer PS. For example, the third metal material includes indium tin oxide (ITO). The first connection wire CL1 is connected to the first clock wire CLK1 and the first through a contact hole through which a part of the first clock wire CLK1 is exposed and a contact hole through which a part of the first additional wire SL1 is exposed. The additional wiring SL1 is electrically connected. The third connection wire CL3 is connected to the second clock wire CLK2 and the second through a contact hole through which a part of the second clock wire CLK2 is exposed and a contact hole through which a part of the second additional wire SL2 is exposed. The additional wiring SL2 is electrically connected.

4 is a schematic plan view of a portion of a display substrate according to a second exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line III-III ′ of FIG. 4.

As illustrated, the display substrate according to the second exemplary embodiment of the present invention may include a gate circuit part CS, a wiring part LS, first additional wirings and second additional wirings SL1 and SL2, and a first connection wiring CL1. ), The second connection wiring CL2, the third connection wiring CL4, and the fourth connection wiring CL3 and CL4.

Hereinafter, for convenience of description, the second embodiment will be described based on differences from the first embodiment.

4 and 5, the first clock wires and the second clock wires CLK1 and CLK2 are formed of a first metal material on the substrate and formed in the first layer. Ground wiring VSS, first application wiring IL1, second application wiring IL2, third application wiring IL3, first additional wiring SL1, second additional wiring SL2, and second connection wiring And the fourth connection lines CL2 and CL4 are formed of a second metal material and formed on a second layer different from the first layer. The first connection line and the third connection line CL1 and CL3 are formed of a third metal material and formed on a third layer different from the first layer and the second layer.

In this case, the second connection wiring CL2 is formed to extend from the first additional wiring SL1 and the first additional wiring SL1 and the first clock wiring through a contact hole exposing a part of the first clock wire CLK1. Electrically connect (CLK1). The fourth connection line CL4 extends from the second additional line SL2 to expose the second additional line SL2 and the second clock line CLK2 through a contact hole exposing a part of the second clock line CLk2. ) Is electrically connected.

Specifically, the first clock wires and the second clock wires CLK1 and CLK2 made of the first metal material are formed on the substrate. For example, the first metal material includes aluminum (Al) or an aluminum alloy. The first and second clock wires CLK1 and CLK2 are then covered by a gate insulating film GI formed over the entire surface of the substrate.

A ground wiring VSS made of a second metal material on the gate insulating layer GI, first to third application wirings IL1, IL2, and IL3, a first additional wiring SL1, a second additional wiring SL2, The second connection line and the fourth connection line CL2 and CL4 are formed. For example, the second metal material includes chromium Cr. The first to third application wirings IL1, IL2, IL3 are configured in the same manner as in the first embodiment.

The second connection line CL2 extends from the first additional line SL1 and is connected to the first clock line CLK2 through a contact hole through which a portion of the first clock line CLK1 is exposed. 1 The additional wiring SL1 and the first clock wiring CLK1 are electrically connected to each other. The fourth connection wire CL4 extends from the second additional wire SL2 and is connected to the second clock wire CLK2 through a contact hole through which a portion of the second clock wire CLK2 is exposed, thereby providing a second additional connection. The wiring SL2 and the second clock wiring CLK2 are electrically connected to each other.

The protective film PS is formed over the entire surface of the substrate on which the first additional wirings and the second additional wirings SL1 and SL2 are formed, so that the ground wiring VSS, the first to third application wirings SL1 and SL2, and the first The additional wiring SL1, the second additional wiring SL2, the second connection wiring and the fourth connection wiring CL2 and CL4 are covered by the protective film PS.

The first connection line and the third connection lines CL1 and CL3 made of a third metal material are formed on the passivation layer PS. For example, the third metal material includes indium tin oxide (ITO). The first connection wire CL1 electrically connects the first additional wire SL1 and the first clock wire CLK1 through the contact holes, and the third connection wire CL3 connects the second additional wire (through the contact holes). SL2) and the second clock wire CL2 are electrically connected to each other.

As described above, according to the present invention, the RC delay of the gate signal between the upper and lower ends of the panel is input by inputting a clock signal input only to the upper end of the clock wire to the upper and lower ends of the clock wire using additional wiring and connection wiring. Improve the deviation.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (8)

A plurality of pixel portions defined by gate lines and data lines; A gate circuit unit outputting a gate signal to the gate lines; A wiring part formed adjacent to the gate circuit part and including a first clock wire, a second clock wire, and a ground wire; First and second additional wirings formed on one side of the wiring portion; And A first connection line and a second connection line electrically connecting the first additional line and the first clock line; a third connection line and a fourth connection line electrically connecting the second additional line and the second clock line. A display substrate comprising connection wiring. The display device of claim 1, wherein the first connection wire and the third connection wire are connected to upper ends of the first clock wire and the second clock wire, and the second connection wire and the fourth connection wire are respectively connected to the first clock wire and the first clock wire; A display substrate connected to the lower end of the second clock wire. The display substrate of claim 2, wherein the first additional wiring and the second additional wiring are formed on the same layer as the first clock wiring and the second clock wiring. The display substrate of claim 2, wherein the first additional wiring and the second additional wiring are formed on the same layer as the ground wiring. 3. The display device of claim 2, wherein the second connection wires and the fourth connection wires are formed on the same layer as the first additional wires and the second additional wires, and the first connection wires and the third connection wires are formed on the first clock wire, A display substrate formed on a layer different from the second clock wiring and the ground wiring. The display substrate of claim 1, wherein the circuit unit comprises a plurality of stages that are cascaded. 7. The apparatus of claim 6, wherein the first clock wire transfers a first clock signal to odd-numbered stages of the stages through a first application wire, and the second clock wire is connected to the stages through a second application wire. And a second clock signal to the even-numbered stages, and the ground line transfers a ground voltage to each stage through a third application line. The display substrate of claim 7, wherein the first to third application wirings are formed on the same layer as the ground wirings.

Images