KR20070071018A - Image sensor and method for manufacturing the same - Google Patents

Abstract

An image sensor is provided to completely prevent dark current introduced into an N^- diffusion region through a P^0 diffusion region overlapping a spacer from flowing to a channel region by forming a P^0 diffusion region surrounding a part of an N^- diffusion region such that the P^0 diffusion region has a predetermined slope in a region overlapping the gate electrode of a transfer transistor. A trench having a predetermined slope is formed in a substrate to have a depth step from the surface of the substrate(20). A first diffusion region of first conductivity type for a photodiode is formed in the substrate to overlap the slope of the trench. A second diffusion region of second conductivity type is extended from the upper surface of the first diffusion region to the slope to block the dark current introduced from the surface of the substrate. A gate electrode is formed on the trench to overlap a part of the slope. The gate electrode can be a gate electrode(41a) of a transfer transistor for transferring the charges accumulated in the photodiode.

Description

Image sensor and manufacturing method thereof {IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME}

1 is a circuit diagram showing a unit pixel of a general CMOS image sensor.

2 is a plan view showing unit pixels of a general CMOS image sensor;

3 is a cross-sectional view taken along the line II ′ of FIG. 2;

4 is a cross-sectional view illustrating a portion of a unit pixel of a CMOS image sensor according to an exemplary embodiment of the present invention.

5A to 5N are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention shown in FIG. 4.

<Description of the symbols for the main parts of the drawings>

13: photodiode 1: transfer transistor

2: reset transistor 3: drive transistor

4: select transistor A: active region

20 substrate 21 pad oxide film

22: pad nitride film 23: trench

24: Channel stop ion implantation process 25: Channel stop layer

27 device isolation layer 28 oxide film

29: nitride film 30, 36, 42, 46, 51: photoresist pattern

32: sacrificial oxide film 33, 44: P ^O ion implantation process

35: P ⁰ diffusion region 37: photodiode ion implantation process

39, 39a: N ^- diffusion region 40: gate oxide film

41: threshold voltage ion implantation process

41a: gate electrode of a transfer transistor

41b: gate electrode of reset transistor

47: LDD ion implantation process 48: LDD region

50: spacer 52: source / drain ion implantation process

53a: floating diffusion region 53b: source / drain region

The present invention relates to an image sensor and a method for manufacturing the same, and more particularly, to an image sensor and a method for manufacturing the same comprising a photodiode.

Recently, the demand for digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

As a camera module, an image sensor module using a Charge Coupled Device (CCD) or a Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, which are basic components, is widely used.

In general, a CMOS image sensor implements an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detecting a signal in a switching manner. Currently, a unit pixel of most CMOS image sensors is implemented. One photodiode and four NMOS transistors in which control signals Tx, Rx, Dx, and Sx are respectively input to the gate are configured.

1 is a circuit diagram illustrating a unit pixel of a general CMOS image sensor.

Referring to FIG. 1, a unit pixel of a CMOS image sensor may include a photo diode (PD) that receives light to generate photocharges, and a floating diffusion node configured to float photoelectric charges collected from the photo diodes (PD). A source follower buffer amplifier (Source Follower) to amplify the potential of the transfer transistor 1 for transporting to the FD, the reset transistor 2 for resetting the potential of the floating diffusion node FD, and the floating diffusion node FD. A drive transistor 3, which functions as a buffer amplifier, and a select transistor 4, which performs a switching role in order to output a signal amplified from the drive transistor 3, are constituted. Herein, reference numeral '5', which is not described, refers to a load transistor receiving an R _L control signal.

FIG. 2 is a plan view illustrating unit pixels of a general CMOS image sensor, and FIG. 3 is a cross-sectional view taken along the line II ′ of FIG. 2.

2 and 3, a general CMOS image sensor includes an N ⁻ diffusion region 13 for photodiodes and a portion of the N ⁻ diffusion region 13 locally formed in the substrate 10 of the active region A. Referring to FIGS. The gate electrode 12a of the transfer transistor overlapped and formed on the substrate 10 and a plurality of transistor gate electrodes formed on the substrate 10 exposed by the gate electrode 12a of the transfer transistor are included.

In particular, in order to prevent dark current flowing into the N ⁻ diffusion region 13 from the surface of the substrate 10, an upper surface of the N ⁻ diffusion region 13 is doped with a P ⁰ diffusion region that is doped with an opposite conductivity type. 18) is formed, wherein the P ⁰ diffusion region 18 is formed in the form of LDD as shown in the figure.

That is, the P ⁰ diffusion region 18 forms the LDD region 14 in the N ⁻ diffusion region 13 exposed to one side of the gate electrode 12a of the transfer transistor after forming the gate electrode 12a of the transfer transistor. After that, spacers 16 are formed on both sidewalls of the gate electrode 12a of the transfer transistor, and then a P-type dopant is injected into the N ^- diffusion region 13 exposed to one side of the spacer 16 at a high concentration to form a high concentration junction. The area 17 is formed.

Therefore, in the P ⁰ diffusion region 18, the depth in the region corresponding to the spacer 16 is significantly lower than the depth in the region exposed to one side of the spacer 16. Therefore, there is a problem that dark current is generated in a region having a relatively low depth, that is, a region overlapping with the spacer 16.

2 and 3, reference numerals '12b', '12c', and '12d', which are not described, respectively represent gate electrodes of reset transistors, gate electrodes of drive transistors, and gate electrodes of select transistors, respectively. Electrically separated from the substrate 10 through 11, '19a' and '19b' represent floating diffusion regions and source / drain regions, and '15' is an LDD constituting the floating diffusion region and source / drain regions. Area.

Accordingly, an object of the present invention is to provide an image sensor and a method of manufacturing the same, which are designed to solve the above-mentioned problems of the prior art and can block the flow of dark current flowing from the surface of a substrate.

According to an aspect of the present invention, there is provided a substrate having a trench having a predetermined inclined surface to have a depth step from a surface thereof, and a first conductive type for photodiode formed in the substrate so as to overlap the inclined surface of the trench. A first diffusion region, a second diffusion region of a second conductivity type formed to extend from the upper surface of the first diffusion region to the inclined surface to block the dark current flowing from the surface of the substrate, and to partially overlap the inclined surface; An image sensor including a gate electrode formed on an upper portion of a trench is provided.

In addition, the present invention according to another aspect for achieving the above object, providing a substrate defined by the active region and the field region, forming a sacrificial oxide film to have a predetermined inclined surface on both sides of the substrate surface, Forming a first diffusion region of a first conductivity type in the substrate of the active region exposed to both sides of the sacrificial oxide film and the substrate corresponding to the inclined surface of the sacrificial oxide film so as to block a dark current flowing from the surface of the substrate; And forming a second diffusion region of the second conductivity type for a photodiode locally in the substrate at the bottom of the first diffusion region, and removing the sacrificial oxide film to have a depth step from the surface of the substrate. Forming a trench, and forming a trench on the trench to be aligned with one side of the second diffusion region. It provides a process for preparing an image sensor forming a byte electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

4 is a plan view illustrating unit pixels of a CMOS image sensor according to an exemplary embodiment of the present invention. Here, for convenience of description, a transistor for controlling the charge of the photodiode is used as an NMOS transistor as an example, and a unit pixel composed of one photodiode and four NMOS transistors is illustrated.

Referring to FIG. 4, a CMOS image sensor according to an exemplary embodiment of the present invention may include a substrate 20 having a trench (not shown) having a predetermined inclined surface to have a depth step from a surface thereof, and a substrate 20 to overlap the inclined surface of the trench. A photodiode N ^- diffusion region 39a formed therein and a P ⁰ diffusion region 35 extending from an upper surface of the N ^- diffusion region 39a to an inclined surface to block dark current flowing from the surface of the substrate 20. And a gate electrode 41a of the transfer transistor formed on the trench so that the inclined surface and a portion thereof overlap each other.

As a result, according to the exemplary embodiment of the present invention, the P ⁰ diffusion region 35 is formed so as to surround one side of the N ⁻ diffusion region 39a with a predetermined inclined surface in a region overlapping with the gate electrode 41a of the transfer transistor. The dark current flowing into the N ⁻ diffusion region 39a through the P ⁰ diffusion region 35 in the region overlapping the spacer 50 can be reliably blocked from flowing to the channel region.

Here, the gate electrode (41a) of the transfer transistor also in accordance with the slope of the P ⁰ diffusion region 35 in the region overlapping the P ⁰ diffusion region 35 can be formed to have an inclination. The gate electrode 41b of the reset transistor may be further formed on the trench spaced apart from the gate electrode 41a of the transfer transistor to reset the photodiode through the gate electrode 41a of the transfer transistor.

Here, a spacer 50 made of an insulating film is provided on both sidewalls of the gate electrode 41a of the transfer transistor and the gate electrode 41b of the reset transistor. Preferably, the P ⁰ diffusion region 35 corresponds to the spacer 50. It has a higher doping concentration in the region exposed to one side of the spacer 50 than in the region.

At this time, the gate electrode 41a of the transfer transistor and the gate electrode 41b of the reset transistor are electrically separated from the substrate 20 through the gate oxide film 40, and the substrate 20 is active by the device isolation film 27. It is defined as an area and a field area. Preferably, device isolation film 27 is formed according to known STI techniques.

Here, a channel stop layer 25 doped with the same conductivity type as the P ⁰ diffusion region 35 may be further formed at an interface between the device isolation layer 27 and the substrate 20. The P ⁰ diffusion region 35 is electrically connected to the channel stop layer 25 so that when the voltage is applied to the P ⁰ diffusion region 35, the same voltage is also applied to the substrate 20. It is formed overlapping with the upper corner portion of 25).

To this end, the substrate 20 is also doped with the same P-type impurity ions as the P ⁰ diffusion region 35 and the channel stop layer 25.

In addition, a floating diffusion region 53a and a source / drain region 53b are formed in the substrate 20 exposed to both sides of the plurality of transistor gate electrodes including the gate electrodes 41a and 41b of the transfer transistor and the reset transistor. . Preferably, the floating diffusion region 53a and the source / drain region 53b are formed in LDD form. Accordingly, the floating diffusion region 53a and the source / drain region 53b include the LDD region 48.

Hereinafter, a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5A to 5N. Here, only a part of the unit pixels of the CMOS image sensor is shown for convenience of description.

First, as shown in FIG. 5A, a trench 23 is formed in the substrate 20 by applying a known shallow trench isolation (STI) technique. This defines an active region and a field region in the substrate 20. That is, the trench 23 is formed to form an isolation layer for defining a field region.

For example, the substrate 20 may be a P-type substrate doped with a P-type, and an epitaxial layer (not shown) may be epitaxially grown by doping the same P-type impurities on the substrate 20.

For example, after the pad oxide film 21 and the pad nitride film 22 are sequentially deposited on the substrate 20, a predetermined photoresist pattern (not shown) is formed on the pad nitride film 22.

Subsequently, a part of the pad nitride film 22 is etched by performing an STI etching process using a photoresist pattern, and then a strip process is performed to remove the photoresist pattern. Next, the trench 23 is formed by etching the exposed pad oxide film 21 and the substrate 20 by using the pad nitride film 22 as a mask.

Subsequently, as illustrated in FIG. 5B, the substrate is exposed by the trench 23 (see FIG. 5A) by performing a channel stop ion implantation process 24 using the pad nitride film 22 as a mask. A channel stop layer 25 is formed along the interface of 20. For example, the channel stop layer 25 is formed by implanting the same P-type impurity ions as the substrate 20, for example, boron (B) ions.

In this case, the channel stop ion implantation process 24 is performed to enhance isolation between neighboring unit pixels, and the channel stop layer 25 also serves to increase capacitance of the photodiode. The reason why the channel stop layer 25 can increase the capacitance of the photodiode is as follows.

This is because when the reverse stop voltage is applied to the P ⁰ diffusion region and the channel stop layer 25 is doped with the same conductivity type as the P ⁰ diffusion region and the substrate 20 to be formed through a subsequent process, the channel stop layer 25 The same voltage is applied to the substrate 20 through the same. Therefore, the depletion layer of the photodiode is increased to increase the capacitance of the photodiode.

In particular, the channel stop ion implantation process 24 is tilted to be thinly doped to the interface of the substrate 20 exposed due to the trenches 23 (see FIG. 5A), that is, less dopant ions are implanted in the active region direction. The injection method is applied. By doing so, it is possible to prevent the reduction of the area of the photodiode, thereby increasing the sensitivity of the image sensor.

Subsequently, as shown in FIG. 5C, the HDP (High Density Plasma) oxide film is subjected to a CMP (Chemical Mechanical Polishing) process so that the trench 23 (see FIG. 5A) is embedded to planarize the HDP oxide film.

Subsequently, a wet etching process is performed to remove the pad nitride film 22 (see FIG. 5B) and the pad oxide film 21 (see FIG. 5B). As a result, an isolation layer 27 is formed in the trench 23.

Subsequently, as illustrated in FIG. 5D, the oxide film 28 and the nitride film 29 are sequentially deposited by a hard mask on the substrate 20 including the device isolation film 27.

Subsequently, after the photoresist (not shown) is applied onto the nitride film 29, an exposure and development process using a photo mask (not shown) is performed to form the photoresist pattern 30.

Next, an etching process using the photoresist pattern 30 as a mask is performed to sequentially etch the nitride film 29 and the oxide film 28, which are hard masks, to form a hard mask pattern.

Subsequently, as shown in FIG. 5E, a strip process is performed to remove the photoresist pattern 30 (see FIG. 5D).

Then, by applying a well-known LOCOS (LOCal Oxidation of Silicon) technology, a sacrificial oxide film of the same type as the LOCOS type field oxide film is formed on the surface of the substrate 20 exposed by the hard mask pattern, that is, the nitride film 29 and the oxide film 28. To form 32. Here, the sacrificial oxide film 32 is formed to secure the inclined surface of the P ⁰ diffusion region to be formed through a subsequent process.

At this time, in order to control the bird's beak of the sacrificial oxide film 32, the thickness of the nitride film 29 is appropriately controlled.

Subsequently, as illustrated in FIG. 5F, a wet etching process is performed to remove the nitride layer 29 (see FIG. 5E). For example, the nitride layer 29 is removed by performing a wet etching process using phosphoric acid (H ₃ PO ₄ ).

Subsequently, in order to prevent dark current generated from the surface of the substrate 20, a low concentration of P ⁰ ion implantation process 33 using the remaining oxide film 28 and the sacrificial oxide film 32 as a mask is performed to lower the concentration in the substrate 20. P ⁰ diffusion region 35 is formed. In this case, the P ⁰ diffusion region 35 is formed by overlapping the channel stop layer 25 to be electrically connected to the substrate 20 through the channel stop layer 25.

In particular, during the P ⁰ ion implantation process 33, a low concentration P-type dopant is implanted into the substrate 20 corresponding to a portion where the sacrificial oxide film 32 has a slope. Accordingly, the P ⁰ diffusion region 35 is formed to extend to the portion where the sacrificial oxide film 32 has an inclined surface.

Subsequently, as shown in FIG. 5G, after the photoresist (not shown) is applied onto the oxide film 28 including the sacrificial oxide film 32, an exposure and development process using a photomask (not shown) is performed to carry out the photo. The resist pattern 36 is formed. The photoresist pattern 36 is used to define a region in which the photodiode is to be formed. The photoresist pattern 36 has a structure in which a region between the sacrificial oxide layer 32 and the device isolation layer 27 is opened.

Subsequently, an N ⁻ ion implantation process 37 using the photoresist pattern 36 as a mask is performed to form an N ⁻ diffusion region 39 for the photodiode. In this case, the N ⁻ ion implantation process 37 lowers the doping concentration of the implanted N-type impurities to increase the number of electron hole pairs generated by light. Through this, the depletion layer of the photodiode can be increased.

For example, the N ⁻ ion implantation process 37 implants phosphorus (P) or arsenic (As) ions, which are a Group 5 material.

Subsequently, as shown in FIG. 5H, a strip process is performed to remove the photoresist pattern 36 (see FIG. 5G). Then, a drive-in process is performed to diffuse the N ⁻ diffusion region 39a.

Subsequently, as illustrated in FIG. 5I, the oxide film 28 (see FIG. 5H) and the sacrificial oxide film 32 (see FIG. 5H) where defects are generated through a plurality of ion implantation processes are removed, and then the sacrificial oxide film 32 is removed. As a result, the gate oxide film 40 is formed along the step of the entire structure having the inclined surface.

Subsequently, the threshold voltage ion implantation process 41 for adjusting the threshold voltage of the transistor is performed using the gate oxide film 40.

5J, a polysilicon film (not shown) is deposited on the gate oxide film 40 as the gate conductive film. At this time, the polysilicon film deposits a doped or undoped silicon film. For example, in the case of an undoped silicon film, it is deposited by a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ . On the other hand, in the case of the doped silicon film is deposited by LPCVD method using a gas mixed with PH ₃ , PCl ₅ , BCl ₃ or B ₂ H ₆ in SiH ₄ .

Next, a predetermined photoresist pattern 42 is formed on the polysilicon film. Here, the photoresist pattern 42 is formed to define the gate electrode and overlaps the inclined portion of the P ⁰ diffusion region 35.

Next, an etching process using the photoresist pattern 42 as a mask is performed to etch the polysilicon film. As a result, a plurality of gate electrodes for the transistor are formed on the gate oxide film 40. For example, the gate electrode 41a of the transfer transistor formed to be aligned with one side of the N ⁻ diffusion region 39a and the gate electrode 41b of the reset transistor formed to be spaced apart from the predetermined distance are formed. In addition, gate electrodes (not shown) of the drive transistor and the select transistor are simultaneously formed.

Subsequently, as shown in FIG. 5K, a high concentration of P ⁰ ion implantation process 44 using the photoresist pattern 42 as a mask is performed to form a high concentration of P-type impurity ions in the P ⁰ diffusion region 35 (dotted line display). Inject). Therefore, the P ⁰ diffusion region 35 has a higher doping concentration in the region exposed to one side of the gate electrode 41a of the transfer transistor than in the region corresponding to the gate electrode 41a of the transfer transistor.

In this case, although not shown in the drawing, a high concentration of P-type impurity ions may be easily diffused in the inclined portion of the P ⁰ diffusion region 35 in a subsequent heat treatment process.

Here, the high concentration P ⁰ ion implantation process 44 may be performed by forming a separate photoresist pattern (not shown) without using the photoresist pattern 42 formed for forming the gate electrode.

Subsequently, as shown in FIG. 5L, a strip process is performed to remove the photoresist pattern 42 (see FIG. 5K), and then a separate photoresist pattern 46 is formed. The photoresist pattern 46 is formed to define an LDD region constituting the source / drain of the transistor, and has a structure covering the region where the photodiode is formed.

Next, an LDD ion implantation process 47 using the photoresist pattern 46 as a mask is performed to form the LDD region 48 in the substrate 20 exposed by the plurality of transistor gate electrodes. For example, the LDD region 48 is formed in the substrate 20 exposed to both sides of the gate electrode 41a of the transfer transistor and the gate electrode 41b of the reset transistor.

Subsequently, as shown in FIG. 5M, the strip process is performed to remove the photoresist pattern 46 (see FIG. 5L), and then spacers 50 are formed on both sidewalls of the plurality of transistor gate electrodes. For example, after the insulating film for the spacer is deposited along the step of the upper part of the entire structure including the gate electrode 41a of the transfer transistor and the gate electrode 41b of the reset transistor, the spacer 50 is formed by dry etching.

Subsequently, another photoresist pattern 51 is formed. The photoresist pattern 51 is formed to define a source / drain region of the transistor and covers the region in which the photodiode is formed.

Subsequently, a source / drain ion implantation process 52 using the photoresist pattern 51 and the spacer 50 as a mask is performed to penetrate the LDD region 48 exposed by the spacer 50 into the substrate 20. Source / drain regions 53a and 53b are formed. At this time, the source / drain region 53a formed in the region between the gate electrode 41a of the transfer transistor and the gate electrode 41b of the reset transistor is called a floating diffusion region.

Subsequently, as shown in FIG. 5N, a strip process is performed to remove the photoresist pattern 51 (see FIG. 5M).

Thereafter, the contact and the wiring process are carried out according to a known technique.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in the end, the P ⁰ diffusion region is formed so as to surround one side of the N ⁻ diffusion region with a predetermined inclined surface in the region overlapping with the gate electrode of the transfer transistor. Dark current flowing into the N ⁻ diffusion region through the P ⁰ diffusion region can be reliably blocked from flowing to the channel region. Through this, the noise of the image sensor may be removed to improve reliability.

Claims (21)

A substrate having a trench having a predetermined sloped surface to have a depth step from the surface; A first diffusion region of a first conductivity type for a photodiode formed in the substrate so as to overlap an inclined surface of the trench; A second diffusion region of a second conductivity type formed to extend from an upper surface of the first diffusion region to the inclined surface to block a dark current flowing from the surface of the substrate; And A gate electrode formed on the trench to overlap a portion of the inclined surface Image sensor comprising a. The method of claim 1, And the gate electrode has an inclination along an inclined surface of the second diffusion region in an area overlapping the second diffusion region. The method according to claim 1 or 2, And the gate electrode is a gate electrode of a transfer transistor for transferring charge accumulated in the photodiode. The method of claim 3, wherein And a gate electrode of the reset transistor formed on the trench spaced apart from the gate electrode of the transfer transistor to reset the photodiode through the transfer transistor. The method of claim 4, wherein And spacers on both sidewalls of the gate electrode of the transfer transistor and the gate electrode of the reset transistor. The method of claim 5, The second diffusion region has a higher doping concentration in a region exposed to one side of the spacer than in a region corresponding to the spacer. The method of claim 4, wherein And the gate electrode of the transfer transistor and the gate electrode of the reset transistor are electrically separated from the substrate through a gate oxide film. The method of claim 4, wherein And the substrate is defined by an isolation layer as an active region and a field region. The method of claim 8, And a channel stop layer of the second conductivity type formed at an interface between the device isolation layer and the substrate. The method of claim 9, And the second diffusion region overlapping an upper edge portion of the channel stop layer. Providing a substrate defined by an active region and a field region; Forming a sacrificial oxide film on the surface of the substrate to have a predetermined inclined surface at both sides; Forming a first diffusion region of a first conductivity type in the substrate of the active region exposed to both sides of the sacrificial oxide film and the substrate corresponding to the inclined surface of the sacrificial oxide film so as to block a dark current flowing from the surface of the substrate; ; Forming a second diffusion region of a second conductivity type for a photodiode locally in the substrate at the bottom of the first diffusion region; Removing the sacrificial oxide layer to form a trench having a predetermined slope to have a depth step from the surface of the substrate; And Forming a gate electrode on the trench to be aligned with one side of the second diffusion region Image sensor manufacturing method comprising a. The method of claim 9, And the gate electrode is a gate electrode of a transfer transistor for transferring charge accumulated in the photodiode. The method of claim 12, And forming a gate electrode of the reset transistor on the trench spaced apart from the gate electrode of the transfer transistor to reset the photodiode through the transfer transistor while simultaneously forming a gate electrode of the transfer transistor. The method according to any one of claims 11 to 13, The sacrificial oxide film is formed by performing a LOCOS process using a hard mask pattern covering an area where the photodiode is to be formed as an anti-oxidation film. The method of claim 14, The hard mask pattern is formed of a laminated film of an oxide film / nitride film. The method of claim 15, The nitride film is removed immediately after the sacrificial oxide film is formed, and the oxide film remains to be used as a screen oxide film when forming the first diffusion region. The method of claim 16, After forming the first diffusion region, Removing the oxide film and the sacrificial oxide film; Forming a gate oxide film along a step of an upper portion of the entire structure from which the sacrificial oxide film is removed; And Implementing ion implantation process to control the threshold voltage Image sensor manufacturing method further comprising. The method according to any one of claims 11 to 13, After forming the gate electrode, And implanting impurity ions of the first conductivity type into the first diffusion region existing on an upper surface of the second diffusion region exposed to one side of the gate electrode. The method of claim 18, Implanting impurity ions of the first conductivity type into the first diffusion region, Forming spacers on both sidewalls of the gate electrode; And And performing a source / drain ion implantation process using the spacer as a mask. The method according to any one of claims 11 to 13, Providing the substrate defined by the active region and the field region, Forming a trench of a predetermined depth in the substrate; Forming a channel stop layer of the first conductivity type along an interface of the substrate exposed by the trench; And Forming an isolation layer to fill the trench Image sensor manufacturing method comprising a. The method of claim 20, And the first diffusion region is formed to overlap an upper edge portion of the channel stop layer.

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