KR20070021796A - Circuit device and method for stabilizing memory - Google Patents

Abstract

The present invention relates to a circuit device. The circuit device may include: a power supply unit for converting input power to supply output power and supplying the output power after a predetermined delay time when the input power is cut off; A memory in which access is restricted until the supply of the output power is interrupted when access is interrupted while the output power is supplied to the power supply unit; An access unit for accessing the memory; And a controller configured to control the access unit to complete the access operation to the memory when the input power is cut off. As a result, it is possible to improve the stability of the circuit when the supply resumes after the power is cut off.

SDRAM, Access, Stable, Power

Description

Circuit device and memory stabilization method {CIRCUIT DEVICE AND METHOD FOR STABILIZING MEMORY}

1 is a block diagram showing the configuration of a conventional circuit device,

FIG. 2 is a block diagram illustrating characteristics of a power supply unit of the circuit device of FIG. 1.

3 is a waveform diagram illustrating an operation of accessing an SDRAM by a CPU of the circuit device of FIG. 1;

4 is a block diagram showing the configuration of a circuit device according to an embodiment of the present invention;

5 is a waveform diagram illustrating an operation of a CPU accessing an SDRAM according to an embodiment of the present invention.

6 is a flowchart illustrating the operation of a circuit device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100: circuit device 110: flash memory

120: SDRAM 130: CPU

140: power supply unit 150: control unit

152: reset IC 154: microcomputer

156: delay element

The present invention relates to a circuit device and a memory stabilization method. More specifically, the present invention relates to a circuit device and a memory stabilization method that can improve the stability of the circuit when the supply resumes after the power is cut off.

An image processing device such as a TV may be implemented as a circuit device. For example, the conventional image processing apparatus 1 as shown in FIG. 1 has a flash memory storing data of a CPU 13 controlling the overall operation of the apparatus and a computer program corresponding to the operation of the CPU 13. , 11) and a synchronous dynamic RAM (SDRAM) 12 for storing data necessary for the operation of the CPU 13. On the other hand, the image processing apparatus 1 resets the power supply unit 14 and the CPU 13 for supplying power to each component, and allows the power to be turned on and off. 16, a reset IC 15 for resetting the microcomputer 16 to operate smoothly when the power is turned on and off, and wiring (not shown) for connecting each component. can do.

In such a conventional image processing apparatus 1, the power supply unit 14 inputs an input power source such as, for example, a commercial AC power source of 220 V, converts it into a voltage of an appropriate level, and outputs the CPU 13 and the reset IC ( 15), flash memory 11, SDRAM 12 and so on. When input power such as commercial AC power input to the power supply unit 14 is cut off, the reset IC 15 detects that power is cut off based on the level of the output power supplied from the power supply unit 14, and the microcomputer Send a reset signal to (16). When the reset signal is transmitted from the reset IC 15, the microcomputer 16 sends a reset signal for resetting the CPU 13 to the CPU 13, and the CPU 13 stops all processes being processed to stop the operation of the entire apparatus. do. On the other hand, when power supply is resumed from the power supply unit 14, power is supplied to the CPU 13, the flash memory 11, the SDRAM 12, and the like, and the CPU 13 operates the device again.

When the power supply unit 14 of the conventional image processing apparatus 1 is interrupted and resupplied (17 in FIG. 2), the characteristics of the output power as shown in FIG. 2 (18 in FIG. 2) Can have That is, when the input power is cut off (a in FIG. 2), the output power of the power supply unit 14 drops from the potential A (eg, about 5 V) to the potential B (eg, about 3.5 V), and is charged internally. After the potential is maintained for a predetermined time by the power source, the potential gradually decreases as the charged power source is discharged. The CPU 13, the flash memory 11, the SDRAM 12, and the like determine that the power is supplied when the level of the power input from the power supply unit 14 is equal to or higher than the potential C (for example, about 3.3 V), and normal operation is performed. Perform.

On the other hand, as described above, when the input power is cut off (a in FIG. 2), the CPU 13 stops all the operations that were being performed by the input reset signal. If the CPU 13 is accessing data stored in the SDRAM 12 (5 in Fig. 3), when the reset signal is input, access to the SDRAM 12 is stopped (c in Fig. 3).

By the way, even if the input power is cut off (a in Fig. 2), since the power supplied to the SDRAM 12 is greater than the potential C as the potential B, the SDRAM 12 is not the CPU 13 unless the output power is smaller than the potential C. Abnormal access to the device is stopped unstable (3 in Figure 3). 3D shows the time point when the access of the SDRAM 12 ends. When the SDRAM 12 stops unstable, when the input power is supplied again to the power supply unit 14 while the output power is not smaller than the potential C (b in Fig. 2), the CPU 13 causes the SDRAM 12 Attempts to access the card 1), but since the SDRAM 12 is unstablely stopped, normal access is not possible, and the entire device operation cannot be resumed.

An object of the present invention is to provide a circuit device and a memory stabilization method which can improve the stability of a circuit upon resuming supply after power supply is cut off.

In order to achieve the above object, the present invention, in the circuit device, converts the input power to supply the output power, when the input power is cut off the power supply unit that the supply of the output power is cut off after a predetermined delay time elapsed ; A memory in which access is restricted until the supply of the output power is interrupted when access is interrupted while the output power is supplied to the power supply unit; An access unit for accessing the memory; And a controller configured to control the access unit to complete the access operation to the memory when the input power is cut off.

The power supply unit may include a switched-mode power supply (SMPS) for inputting an AC power and converting the same to output a DC power. The power supply unit may gradually reduce the output power when the input power is cut off, and the memory may determine that the output power is supplied when the size of the output power is greater than or equal to a predetermined value.

The memory may be a synchronous dynamic random access memory (SDRAM). The access unit is a central processing unit (CPU), and the control unit includes a reset IC which transmits an interrupt signal to the CPU when the input power is cut off, and the CPU provides the interrupt signal port for receiving the interrupt signal. When the interrupt signal is input while the memory is being accessed, the memory access can be completed. The reset IC receives the output power of the power supply unit, and when the output power is less than or equal to a predetermined value, the reset IC may determine that the input power is cut off.

The control unit may further include a microcomputer for transmitting a reset signal to the CPU after the CPU completes access to the memory when the input power is cut off, and the CPU has a reset signal port for receiving the reset signal. When the reset signal is input, access to the memory may be stopped. The control unit receives a microcomputer to receive the interrupt signal from the reset IC and outputs a reset signal; And a delay element for receiving the reset signal from the microcomputer and delaying the CPU until the CPU completes access to the memory and transmitting the reset signal to the CPU, wherein the CPU provides a reset signal port for receiving the reset signal. The operation may be stopped when the reset signal is input.

The object of the present invention, the power supply for converting the input power to supply the output power, the supply of the output power is cut off after a predetermined delay time when the input power is cut off; A memory in which access is restricted until the supply of the output power is interrupted when access is interrupted while the output power is supplied to the power supply unit; And a memory stabilization method of a circuit device including an access unit for accessing the memory, the method comprising: determining whether the input power is cut off; And if the input power is cut off, completing the access to the memory of the access unit.

In the determining of whether the input power is cut off, if the output power is less than or equal to a predetermined value, it may be determined that the input power is cut off. The access unit is a CPU, and the step of completing access to the memory of the access unit may include transmitting an interrupt signal to the CPU to complete access to the memory of the CPU. The memory stabilizing method may include transmitting, to the CPU, a reset signal for stopping the operation of the CPU after the access unit completes access to the memory.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 4 is a block diagram showing a main configuration of a circuit device 100 according to an embodiment of the present invention. The circuit device 100 of the present embodiment may be an image processing device such as a TV. As shown in FIG. 4, the circuit device 100 may include a flash memory 110, an SDRAM 120, a CPU 130, a power supply 140, and a controller 150.

The CPU 130 of this embodiment is an example of an access unit of the present invention, and performs overall control of the circuit device 100 of this embodiment. The flash memory 110 may store data of instructions programmed according to a predetermined computer language to enable a control operation of the CPU 130. The SDRAM 120 of the present embodiment is an example of the memory of the present invention, and data necessary for the CPU 130 to perform a control operation may be stored. The CPU 130 may access data stored in the SDRAM 120 to perform a control operation.

The power supply unit 140 of the present embodiment supplies power to the CPU 130, the flash memory 110, the SDRAM 120, and the like. The power supply unit 140 inputs input power which is a commercial AC power of 220V, for example, converts it appropriately, and supplies output power. The power supply unit 140 of the present embodiment takes a predetermined time to be completely discharged by the internally charged power when the input power is cut off. The power supply unit 140 may include a switched-mode power supply (SMPS) for inputting AC power as an input power, converting the same, and outputting DC power. The power supply unit 140 of this embodiment has a configuration similar to the power supply unit 14 of FIG. That is, the power supply unit 140 may gradually reduce the output power when the input power is cut off. In this case, the SDRAM 120 may determine that the power is normally supplied when the size of the output power of the power supply 140 is a predetermined value, for example, about 3.3V or more.

The controller 150 controls the CPU 130 to complete the access operation to the SDRAM 120 when the input power of the power supply 140 is cut off. As illustrated in FIG. 4, the controller 150 of the present exemplary embodiment may include a reset IC 152, a microcomputer 154, and a delay unit 156. The reset IC 152 receives power from the power supply 140. The reset IC 152 transmits an interrupt signal to the CPU 130 when the input power to the power supply unit 140 is cut off. In this case, the CPU 130 may have the interrupt signal port for receiving the interrupt signal of the reset IC 152, and may complete the access of the SDRAM 120 when the interrupt signal is input while the SDRAM 120 is being accessed. .

When the reset IC 152 senses the output power of the power supply 140 and evaluates that the output power is less than or equal to a predetermined value, the reset IC 152 may determine that the input power of the power supply 140 is cut off. For example, the reset IC 152 may be a comparator such as an OP-AMP, and inputs a potential corresponding to the output power of the power supply unit 140 and a reference potential of about 4.2 V, and corresponds to a potential corresponding to the output power. Is less than the reference potential of about 4.2V, depending on the setting, a signal with a logic state low or high can be output as an interrupt signal.

When the input power of the power supply unit 140 is cut off, the microcomputer 154 may transmit a reset signal to the CPU 130 after the CPU 130 completes access to the SDRAM 120. In this case, the CPU 130 may have a reset signal port for receiving a reset signal from the microcomputer 154, and may stop all operations that are being performed when the reset signal is input. The microcomputer 154 of the present exemplary embodiment may output a reset signal to the CPU 130 when the interrupt signal is input from the reset IC 152.

 The controller 150 may further include a delay element 156 that receives a reset signal from the microcomputer 154 and delays the CPU 130 until the CPU 130 completes access to the SDRAM 120 and transmits the delay signal to the CPU 130. Can be. In this case, the CPU 130 may have a reset signal port for receiving a reset signal, and may stop the operation when the reset signal is received. The delay element 156 may be implemented as a capacitor having a predetermined capacity C [Farad] having one end connected in parallel with the CPU 130 with respect to the microcomputer 154 and the other end grounded. The capacitance C of the delay element 156 may be determined based on the time to be delayed.

5 is a waveform diagram schematically illustrating a waveform of a CPU 130 accessing the SDRAM 120 according to an embodiment of the present invention. In FIG. 5, 54 denotes an input power source, 52 denotes an access operation of the CPU 130 to the SDRAM 120, and 56 denotes an overall operation of the CPU 130. When the input power of the power supply 140 is cut off (e) of FIG. 5, the CPU 130 receives an interrupt signal by the reset IC 152. In this case, the CPU 130 waits for the reset signal after the access operation is arranged by the interrupt signal even when the SDRAM 120 is being accessed. The access to the SDRAM 120 is terminated by the cleanup operation of the CPU 130 (f in FIG. 5). After a predetermined time has elapsed by the delay element 156, the CPU 130 receives a reset signal from the microcomputer 154 and stops all the operations (g in Fig. 5). Therefore, even if the input power is cut off, the SDRAM 120 does not stop unstable because the access operation of the SDRAM 120 by interruption is completed before the operation termination by the reset of the CPU 130 is completed.

6 is a flow chart schematically showing the operation of the circuit device 100 according to an embodiment of the present invention. First, the reset IC 152 detects the output power of the power supply unit 140 and evaluates whether or not the output power is a predetermined value or less (S102). If it is determined that the evaluation result is less than the predetermined value (YES in S102), the reset IC 152 transmits an interrupt signal to the CPU 130, and transmits the same signal as the interrupt signal as a reset signal to the microcomputer 154 (S104). .

When the CPU 130 receives the interrupt signal, the CPU 130 cleans up the access of the SDRAM 120 in operation (S106). On the other hand, when the microcomputer 154 receives an interrupt signal, the microcomputer 154 transmits a reset signal to the CPU 130 after a predetermined time delay through the delay element 156 (S108). The CPU 130 stops all operations when receiving the reset signal (S110).

As mentioned above, the present invention has been described in detail through preferred embodiments, but the present invention is not limited thereto and may be variously implemented within the scope of the claims.

As described above, according to the present invention, it is possible to provide a circuit device and a memory stabilization method which can improve the stability of the circuit when the supply resumes after the power is cut off.

Claims (12)

In a circuit device, A power supply unit converting input power to supply output power, and supplying the output power after a predetermined delay time when the input power is cut off; A memory in which access is restricted until the supply of the output power is interrupted when access is interrupted while the output power is supplied to the power supply unit; An access unit for accessing the memory; And And a controller configured to control the access unit to complete the access operation to the memory when the input power is cut off. The method of claim 1, The power supply unit comprises a switch-mode power supply (SMPS) for inputting an AC power and converting it to output a DC power. The method of claim 1, The power supply unit gradually reduces the output power when the input power is cut off, And the memory determines that the output power is supplied when the magnitude of the output power is greater than or equal to a predetermined value. The method of claim 1, And the memory is a synchronous dynamic random access memory (SDRAM). The method of claim 1, The access unit is a central processing unit (CPU), The control unit includes a reset IC for transmitting an interrupt signal to the CPU when the input power is cut off, And said CPU has said interrupt signal port for receiving said interrupt signal and completes access to said memory upon receiving said interrupt signal while accessing said memory. The method of claim 5, And the reset IC receives the output power of the power supply unit and determines that the input power is cut off when the output power is less than or equal to a predetermined value. The method of claim 5, The control unit may further include a microcomputer that transmits a reset signal to the CPU after the CPU completes access to the memory when the input power is cut off. And the CPU has a reset signal port for receiving the reset signal, and stops access to the memory upon receiving the reset signal. The method of claim 6, The control unit receives a microcomputer to receive the interrupt signal from the reset IC and outputs a reset signal; And A delay element for receiving the reset signal from the microcomputer and delaying the CPU until the CPU completes access to the memory and transmits the delay signal to the CPU; And the CPU has a reset signal port for receiving the reset signal, and stops an operation when the reset signal is received. A power supply unit converting input power to supply output power, and supplying the output power after a predetermined delay time when the input power is cut off; A memory in which access is restricted until the supply of the output power is interrupted when access is interrupted while the output power is supplied to the power supply unit; And a memory access method comprising a access unit for accessing the memory, Determining whether the input power is cut off; And And if the input power is cut off, completing the access to the memory of the access unit. The method of claim 9, In the determining of whether the input power is cut off, And determining that the input power is cut off if the output power is less than or equal to a predetermined value. The method of claim 9, The access unit is a CPU, Completing the access to the memory of the access unit, And transmitting an interrupt signal to the CPU to complete the access of the CPU to the memory. The method of claim 11, And transmitting a reset signal to the CPU to stop the operation of the CPU after the access unit completes access to the memory.

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