KR20040006380A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE: A sense amplifier circuit is provided to remove a leakage current and improve sensing margin by applying a back bias voltage to a gate during a turn-off of an isolation transistor as maintaining the characteristics of the isolation transistor of a sense amplifier. CONSTITUTION: A cross coupled sense amplifier senses data loaded on a bit line by a sense amplifier control signal. The first isolation transistor part(10) blocks the connection with the bit line by the first bit line isolation signal. An equalizing transistor part(20) precharges the bit line by a bit line precharge signal. And the second isolation transistor part(40) blocks the connection with the bit line by the second bit line isolation signal. A negative bias level is applied to a gate when the first and the second isolation transistor part and the equalizing transistor part are turned off.

Description

Sense amplifier circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit, and more particularly, to a sense amplifier circuit for controlling a gate voltage of an isolation transistor of a sense amplifier when sensing data of a memory device to improve a sensing margin.

In general, the sense amplifier of a semiconductor memory device uses a nearly shared sense amplifier structure. In addition, the isolation transistor used for sensing the sense amplifier uses the pumping voltage Vpp or the external voltage Vext generated by the pumping voltage generator, and the isolation transistor is turned off by using the ground voltage Vss. .

In addition, the isolation transistor associated with data-in to precharge time (tDPL) is often a transistor having a low threshold voltage.

However, in the above case, when the threshold voltage of the transistor is lowered in the inline process, the amount of leakage current increases even when the isolation transistor is turned off. Therefore, when ΔV (sensing margin) decreases during charge sharing according to the leakage current, there is a problem that a long test of tRAS occurs during the operation of the sense amplifier, so that the sensing margin is reduced and causes a failure.

That is, when the bit line becomes the power supply voltage level during the sensing operation and the bit bar line becomes the ground voltage level, the unselected isolation transistor must maintain a certain turn-off characteristic. However, in this case a leakage current occurs and a current path is formed to the unselected block. Therefore, the bit line precharge level of the electrically blocked bit line and the bit bar line is applied to the sense amplifier so that the line connected to the power supply voltage applying terminal is increased in voltage, and the line connected to the ground voltage applying terminal is lowered in voltage.

In this case, there is a problem in that the precharge command requires more tRP (precharge time), resulting in deterioration of device performance and data failure.

The present invention was created to solve the above problems, while maintaining the characteristics of the isolation transistor of the sense amplifier as it is, at the same time applying a back bias voltage to the gate during the turn-off of the isolation transistor to remove the leakage current and to reduce the sensing margin Its purpose is to improve it.

1 is a circuit diagram of a sense amplifier circuit in accordance with the present invention.

2 is an operation timing diagram of a sense amplifier circuit according to the present invention;

The sense amplifier circuit of the present invention for achieving the above object is a cross-coupled sense amplifier for sensing data carried on the bit line by the sense amplifier control signal and the connection of the bit line by the first bit line separation signal. A first isolation transistor section for blocking, an equalizing transistor section for precharging the bit line by the bit line precharge signal, and a second isolation transistor section for disconnecting the connection with the bit line by the second bit line separation signal, The negative bias level is applied to the gate when the first and second isolation transistors and the equalizing transistors are turned off.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a circuit diagram of a sense amplifier circuit according to the present invention.

According to the present invention, the bit control unit 10 comprises NMOS transistors N1 and N2 which block or connect the bit lines BL and / BL and the sense amplifier 30 by the bit line separation signal bish, and bit by the bit line precharge signal blp. An equalizing unit 20 composed of NMOS transistors N3 to N5 precharges the lines BL and / BL.

In addition, the present invention provides a bit line sense amplifier 30 composed of cross-coupled connected PMOS transistors P1, P2 and NMOS transistors N6, N7 which sense data loaded on the bit lines BL, / BL by the sense amplifier control signals RTO, / S. ) And a line control unit 40 composed of NMOS transistors N8 and N9 which block or connect the bit lines BL and / BL and the sense amplifier 30 by the bit line separation signal bisl.

Here, a back bias voltage is applied to the bulks of the NMOS transistors N1, N2, N8, and N9 of the line controllers 10 and 40 described above. The NMOS transistors N1, N2, N8, and N9, which are isolation transistors, have a back bias voltage level at which the bit line separation signals bish and bisl applied to the gate at turn-off are negative biased.

In addition, NMOS transistors N3 to N5, which are equalizing transistors, have a back bias voltage level at which the bit line precharge signal blp applied to the gate at turn-off is negative bias.

An operation process of the sense amplifier circuit of the present invention having such a configuration will be described below with reference to the waveform diagram of FIG. 2.

First, when an active command is input in the normal operation period 1, the voltage of the cell transistor associated with the corresponding address (x-address) is pumped to the pumping voltage Vpp level. At the same time, one of the bit line separation signals bish or bisl associated with the corresponding address is enabled, so that the selected cell transistor is turned on and the unselected cell transistor is turned off.

At this time, when the bit line isolation signal bish (or bisl) is enabled, the NMOS transistors N1 and N2 (or N8 and N9) are turned on, and the NMOS transistors N8 and N9 (or N1 and N2) are turned off. Here, the level of the bit line separation signal bish (or bisl) applied to the gates of the NMOS transistors N8 and N9 (or N1 and N2) when the NMOS transistors N8 and N9 (or N1 and N2) are turned off is the back bias voltage Vbb level. Becomes Therefore, the leakage current is prevented from occurring by improving the turn-off characteristic of the isolation transistor.

In addition, when the equalizing unit 20 is enabled, the voltage applied to the gates of the NMOS transistors N3 to N5 becomes the back bias voltage level, thereby improving the turn-off characteristic, thereby preventing the occurrence of leakage current.

Thereafter, the data stored in the capacitor by the turned-on cell transistor is recharged using the sense amplifier 30 after performing charge distribution in the section (2), and then performs a read and write operation. In the precharge period 4, the precharge command is input and the bit line separation signals bish and bisl are enabled to turn on the NMOS transistors N1, N2, N8, and N9. Therefore, the bit line BL and the bit bar line / BL are precharged to the bit line precharge voltage Vblp (half Vcc) level.

As described above, the present invention uses the gate voltage at the turn-off of the isolation transistors N1, N2, N8, and N9 as the back bias voltage Vbb having a negative bias, thereby controlling the channel resistance value of the transistor to turn the isolation transistor. The leakage current does not occur when off and the current consumption can be reduced.

3 is another embodiment of a sense amplifier circuit according to the present invention.

3 shows an NMOS transistor N10 and an NMOS transistor N19 which connect or block the bit line BL and the bit bar line / BL by the bit line equalizing signal bleq, and the bit line BL, / BL by bit line separation signal bish. And a line control unit 50 including NMOS transistors N11 and N12 for blocking or connecting the sense amplifier 60 and a cross-coupled connection for sensing data carried on the bit lines BL and / BL by sense amplifier control signals CSP and CSN. And a bit line sense amplifier 60 composed of PMOS transistors P3, P4 and NMOS transistors N13, N14.

The equalizing unit 70 includes NMOS transistors N15 and N16 which precharge the bit lines BL and / BL by the bit line equalizing signal bleq, and the bit lines BL and BL and the sense amplifier 60 by the bit line separation signal bisl. ) Is provided with a line control unit 80 composed of NMOS transistors N17 and N18.

Here, the switching elements NMOS transistors N10 and N19 are provided outside the isolation transistor to perform equalization by the bit line equalizing signal bleq after sensing and reading / writing data. Therefore, by shorting the bit line BL and the bit bar line / BL directly, the bit line is precharged with the precharge voltage to improve the tRP characteristic.

At this time, the bit line equalizing signal bleq applied to the gate when the NMOS transistors N10 and N19 are turned off has a back bias voltage level of negative bias.

Accordingly, the turn-off characteristics of the NMOS transistors N10 and N19 are improved during charge distribution and sensing of the sense amplifier to block the connection between the bit line BL and the bit bar line / BL to improve the sensing margin during charge distribution.

As described above, the present invention provides the following effects.

First, the leakage current generated when the isolation transistor of the sense amplifier is turned off is improved to improve the tRP time.

Second, tRAS eliminates leakage current due to isolation transistors under long test conditions, thus reducing device failure.

Third, by using the back bias voltage as the gate voltage of the transistor to improve the turn-off characteristics it is possible to reduce the current consumption (Icc current).

Fourth, it is possible to improve the precharge characteristic by improving the sensing margin during charge distribution of the sense amplifier.

Claims (5)

A cross coupled sense amplifier configured to sense data carried on the bit line by a sense amplifier control signal; A first isolation transistor unit for disconnecting the connection with the bit line by a first bit line isolation signal; An equalizing transistor unit for precharging the bit line by a bit line precharge signal; And A second isolation transistor unit for disconnecting the connection with the bit line by a second bit line separation signal; And a negative bias level is applied to a gate when the first and second isolation transistor units and the equalizing transistor unit are turned off. The method of claim 1, wherein the negative bias level is A sense amplifier circuit characterized by a back bias voltage level. The method of claim 1, wherein the first and second isolation transistor unit And the back bias voltage is applied through a bulk. A cross coupled sense amplifier configured to sense data carried on the bit line by a sense amplifier control signal; A first isolation transistor unit for disconnecting the connection with the bit line by a first bit line isolation signal; An equalizing transistor unit for precharging the bit line and the bit bar line by a bit line equalizing signal; A second isolation transistor unit for disconnecting the connection with the bit line by a second bit line isolation signal; And And a switching transistor unit configured to connect or block the bit line and the bit bar line by the bit line equalizing signal. And the switching transistor unit is connected between the bit line and the bit bar line, and a negative bias level is applied to a gate during turn-off. The method of claim 4, wherein the negative bias level is A sense amplifier circuit characterized by a back bias voltage level.