KR20030078307A - Synchronous Memory Device with block for controlling data strobe signal - Google Patents

Abstract

PURPOSE: A synchronous memory device including a data strobe signal control part for low latency read is provided, which operates without a delay time at a low latency read operation. CONSTITUTION: A phase comparison part(300) for preamble signal compares a timing of an active signal(ACTIVE) with that of a phase synchronized clock signal(FCLK). A data strobe signal control part(100) controls an enable timing of a preamble signal(PREAMBLE) according to an output of the phase comparison part for preamble signal and then outputs it. And an output buffer(200) receives the preamble signal being output from the data strobe signal control part and then converts a data strobe signal into a preamble state, and outputs it.

Description

Synchronous Memory Device with block for controlling data strobe signal

The present invention relates to a double data rate (DDR) synchronous memory device, which is a next generation memory device, and more particularly, to a dial-synchronous memory device capable of low latency access.

As is well known, a synchronous memory device (hereinafter, referred to as a synchronous memory device) that operates in synchronization with an external system clock is widely used for semiconductor memory devices. A conventional synchronous memory device is a device that inputs and outputs one data over a period of a clock in synchronization with a rising edge of a clock, whereas a digital synchronous memory device is continuously synchronized with a clock rising and falling edge. Two data can be input and output. Therefore, even if the clock frequency is not increased, at least twice the operating speed can be realized compared to the conventional synchronous memory device, and thus, it has gained much attention as a next generation memory device. On the other hand, in order to inform the CPU or the controller of the correct timing of the output data, and to minimize the time skew generated between the chips in the memory chipset (Chip Set) The memory chip outputs a data strobe signal (DQS signal hereinafter) as well as data to the outside of the chip during read driving.

FIG. 1 is a block diagram for generating a DQS signal in a conventional digital synchronous memory device.

Referring to FIG. 1, a block configuration for generating a DQS signal includes a clock buffer 10 that receives clock signals CLK and CLKB from an external source and outputs the delay locked loop, and receives data and a DQS output from the clock buffer. Delay locked loop (DLL) 20, which functions to make the output have no delay compared to external clock, and external commands (/ CS, / RAS, / CAS, / WE) Controls the DQS signal output buffer by receiving the command buffer 30 for converting the signal to be used internally, the output signal READ of the command buffer 30, and the output signal RCLK / FCLK of the delay lock loop 20. And a DQS signal output buffer 50 for outputting a DQS signal under the control of the DQS signal controller 40.

FIG. 2 is a block diagram of the DQS signal controller of FIG. 1.

Referring to FIG. 2, the DQS signal controller 40 includes a read command, a CAS latency (CL), a burst length control (BL), and an output signal of the delay lock loop 20. RCLK / FCLK) as input and a preamble control unit 41 for outputting a preamble signal (PREAMBLE) for maintaining the preamble state of the DQS output, and a DQS data generator (DQS data generator) for controlling the DQS data signal (DQS_DATA) in accordance with CL and BL. 42) and a DQS Hi-Z control section 43 for controlling the DQS signal in a high impedance (Hi-Z) state.

FIG. 3 is a waveform diagram showing DQS signal timing when a read command is input when CL = 1.5.

First, in the digital synchronous memory device, the output data DQ is synchronized with the falling edge and the rising edge of the clock CLK, and two data are successively output within one clock period. The DQS maintains a high impedance state (section A) before the read command is input, and then becomes " low " 0.5 cycles after the read command is input.

In this way, the data strobe signal DQS goes "low" before data output is called "preamble state" (Section B). Subsequently, when data is output, the DQS signal is shifted from the preamble state to "High" in synchronization with the data initially output, and then toggled as the next data is output (Section C) to "low". Transition to. If more data is output (i.e., the burst length is greater than 2), the DQS signal is toggled again and the process of transitioning to "high" is repeated. When the output of the data is completed, the DQS signal returns to the high impedance state to inform the external device that the data is not output.

That is, the DQS operation after the read command is largely performed in a high impedance state, a preamble state, a toggling state, a postamble state, and a high impedance.

FIG. 4 is a waveform diagram illustrating an operation of the digital synchronous memory device of FIG. 1 in normal operation. FIG.

First, when the read command RD is input, the read signal READ is output accordingly, and the DQS output enable signal DQS_OE and the preamble signal PREAMBLE are enabled high according to the read signal READ. Subsequently, the DQS signal becomes the preamble state (tPRE) according to the preamble signal (PREAMBLE). After the preamble state continues for one clock, the DQS signal is toggled according to the output signals RCLK and FCLK of the delay lock loop. Corresponding data is output.

FIG. 5 is a waveform diagram illustrating an operation of the digital synchronous memory device of FIG. 1 during abnormal operation.

As shown in Fig. 4, when the low latency such as CL = 1.5, the read signal READ and the DQS output enable signal DQS_OE are output signals FCLK and RCLK of the delay locked loop after the read command RD is input. If it lags behind, the preamble signal will output with a time delay.

Therefore, in the related art, when the digital synchronous memory device is operated at low cascade latency CL, it is inevitably operated to have a delay time at the beginning of the operation.

An object of the present invention is to provide a synchronous memory device in which low latency operates without a delay time even in a read operation.

FIG. 1 is a block diagram for generating a DQS signal in a conventional digital synchronous memory device.

FIG. 2 is a block diagram of a DQS signal controller in the digital synchronous memory device of FIG.

3 is a waveform diagram showing DQS signal timing.

FIG. 4 is a waveform diagram showing the operation of the digital synchronous memory device of FIG. 1 in normal operation; FIG.

Fig. 5 is a waveform diagram showing the operation of the digital synchronous memory device of Fig. 1 in the abnormal operation.

6 is a block diagram illustrating a DQS signal in a synchronous memory device according to a preferred embodiment of the present invention.

FIG. 7 is a block diagram showing a phase comparator for a preamble signal in FIG. 6; FIG.

FIG. 8 is a block diagram illustrating a preamble signal controller in FIG. 6; FIG.

FIG. 9 is a waveform diagram showing an operation of the memory device of FIG.

According to an aspect of the present invention, there is provided a phase comparator for comparing a timing of an active signal and a phase locked clock signal. A data strobe signal controller for controlling and outputting an enable timing of the preamble signal according to an output of the preamble signal phase comparator; A synchronous memory device having an output buffer for receiving a preamble signal output from the data strobe signal controller and converting the data strobe signal into a preamble state is provided.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

6 is a block diagram illustrating a DQS signal in a synchronous memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the block related to the DQS signal of the synchronous memory device according to the present embodiment is a phase comparator 300 for preamble signal for comparing the timing of the active signal ACTIVE and the phase-locked clock signal FCLK. And a data strobe signal controller 100 for adjusting an enable timing of the preamble signal PREMBLE according to the output signal FAST_PRE <0: i> of the phase comparator 300 for the preamble signal, and a data strobe signal controller ( It is composed of a DQS output buffer 200 for receiving the preamble signal (PREAMBLE) output from the 100 to convert the DQS signal (DQS) to a preamble state.

In addition, the data strobe signal controller 100 inputs a read command READ, a cascade latency CL, a buster length BL, and an output signal RCLK / FCLK of a delay locked loop to input a preamble state of the DQS output. The preamble control unit 110 outputs a preamble signal (PREAMBLE) for maintaining, the DQS data generator 120 for controlling the DQS data signal DQS_DATA according to the cascade latency and the buster length, and the high impedance of the DQS signal. , Hi-Z) DQS Hi-Z control unit 130 for controlling.

FIG. 7 is a block diagram illustrating a phase comparator for a preamble signal in FIG. 6.

Referring to FIG. 7, the phase comparator 300 for the preamble signal receives the active signal ACTIVE to generate a dummy read command generator 310 for generating a dummy read command DUM_READ and a phase-locked clock FCLK. When the delay 320 generating the delayed clock D_FCLK for a predetermined time and the delayed clock D_FCLK are generated earlier than the dummy read command DUM_READ, information on the timing is output (FAST_PRE <0: i>). It consists of a phase comparator 330.

FIG. 8 is a block diagram illustrating a preamble signal controller of FIG. 6.

The preamble signal controller 110 adjusts the propagation delay time of the read command READ according to the output signal FAST_PRE <0: i> of the phase comparator 330 to generate a first preamble signal A. The first preamble signal generator 112, the second preamble signal generator 113 for generating the read command READ as the second preamble signal B according to the phase-locked clock FCLK, and the phase comparator ( A signal synthesizer 111 for outputting the enable signal FAST_PRE according to the output signal FAST_PRE <0: i> of the 330 and the first and second preamble signals A and B according to the enable signal FAST_PRE. ) Is selected and output as a preamble signal (PREAMBLE).

FIG. 9 is a waveform diagram illustrating an operation of the memory device of FIG. 6. Hereinafter, an operation of the semiconductor device for generating the data strobe signal described above will be described with reference to FIGS. 6 to 9.

First, when the active signal ACTIVE is input from the phase comparator 300 for the preamble signal, the dummy read command generator 310 generates a dummy read command DUM_READ and outputs the phase comparator 330 to the phase comparator. The clock FCLK is output to the phase comparator 330 as the delayed clock D_CLK after passing through the delay 320. The phase comparator 330 checks how soon the delayed clock D_CLK is generated than the dummy read command DUM_READ, and outputs information on the timing that is generated quickly if it is generated quickly.

For example, if the delayed clock D_CLK is generated earlier than the dummy read command DUM_READ, one of the output signals FAST_PRE <0: i> of the phase comparator is output high, and the delayed clock D_CLK is the dummy read command DUM_READ. If it is generated later, the output signals FAST_PRE <0: i> of the phase comparator are all kept low.

When the output signals FAST_PRE <0: i> of the phase comparator remain low, the multiplex 114 performs a second operation according to the output signal FAST_PRE of the signal synthesizer 111 of the preamble signal controller 110. The output signal B of the preamble signal generator 113 is output as a preamble signal PREAMBLE.

On the other hand, when one of the output signals FAST_PRE <0: i> of the phase comparator remains high, the multiplex 114 generates the first preamble signal generator 112 according to the output signal FAST_PRE of the signal synthesizer 111. Output signal A is output as a preamble signal PREAMBLE.

The output signal FAST_PRE <0: i> of the phase comparator has a plurality of bits to store information about how quickly the delayed clock D_CLK is generated than the dummy read command DUM_READ and generate the first preamble signal according to the information. The delay value of the unit 112 is determined, and the signal synthesizer 111 enables the output signal FAST_PRE to be high even if only one of the plurality of bits of the phase comparator output signal FAST_PRE <0: i> becomes high. Let's do it.

Therefore, even when the delayed clock D_CLK is generated earlier than the dummy read command DUM_READ when the low latency (eg, CL = 1.5), the preamble signal PREAMBLE may be generated without a delay time by the first preamble signal generator. As a result, when the low latency (e.g., CL = 1.5), the preamplifier signal (PREAMBLE) is generated without a delay time, so that the data output can be made faster, and the synchronous memory performance can be improved.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, data can be output at an accurate timing even in a low latency state, and the performance of the synchronous memory device can be expected to be improved.

Claims (3)

A phase comparator for preamble signal for comparing the timing of the active signal and the phase-locked clock signal; A data strobe signal controller for controlling and outputting an enable timing of the preamble signal according to an output of the preamble signal phase comparator; And an output buffer configured to receive a preamble signal output from the data strobe signal controller, convert the data strobe signal into a preamble state, and output the converted signal. The method of claim 1, The phase comparison unit for the preamble signal, A dummy read command generator configured to receive the active signal and generate a dummy read command; A delay for receiving the phase locked clock and generating a clock delayed for a predetermined time; And And a phase comparator for outputting information on timing when the delayed clock is generated earlier than the dummy read command. The method of claim 2, The data strobe signal controller A first preamble signal generator for generating a first preamble signal by adjusting a propagation delay time of a read command according to the output signal of the phase comparator; A second preamble signal generator for generating the read command as a second preamble signal according to the phase-locked clock; A signal synthesizer for outputting an enable signal according to the output signal of the phase comparator; And And a multiplex for selecting the first preamble signal and the second preamble signal according to the enable signal and outputting the preamble signal.