KR20030050096A - Method of trench type device isolation - Google Patents

Abstract

PURPOSE: A trench isolation method is provided to prevent a dent phenomenon chronically occurring in a conventional trench-type isolation process by performing a relatively simple additional process for recessing a pad layer. CONSTITUTION: The pad layer is formed on a substrate(100). An etch stop layer is formed on the pad layer. The etch stop layer, the pad layer and the substrate in a trench region are sequentially eliminated through a patterning process to form an etch stop layer pattern, a pad layer pattern and a substrate trench(140). An isotropic etch process is performed on the pad layer pattern to laterally recess the pad layer pattern. A silicon nitride layer liner(160) is formed on the substrate including the inner wall of the trench. A silicon oxide layer is stacked on the substrate to fill the trench. A chemical mechanical polishing(CMP) process is performed on the front surface of the substrate until the etch stop layer pattern is exposed. The etch stop layer pattern is removed to expose an active region through an etch process.

Description

Method of trench type device isolation

The present invention relates to a method of forming a semiconductor device, and more particularly, to a trench type device isolation method for a substrate.

A semiconductor device is formed by forming many electronic elements on a substrate having a limited area and forming wirings to associate them. In order for each electronic device on the substrate to operate normally, separation between the devices is required so that they are not affected by the operation of nearby devices.

In order to separate devices, a method of forming a field oxide film in an area between devices of a substrate is mainly used. Conventionally, LOCOS (Local Oxidation of Silicon) method of wet oxidation of a part of a substrate is mainly used to form a field oxide film. However, the LOCOS method has a disadvantage in that a bird 'beak phenomenon in which the oxide film penetrates into the active region around the field oxide film occurs. Therefore, as device integration of semiconductor devices progresses, the necessity of narrowing the field oxide film region and expanding the active region relatively increases, so that a trench type device isolation method is widely used.

1 to 5 are process cross-sectional views illustrating respective steps of a conventional trench isolation method.

Referring to the drawings, a conventional trench type isolation method is described. First, a silicon nitride film is formed on the substrate 10 as a pad oxide film 20 and an etch stop layer. The etching stop layer pattern 30 is formed by removing the etch stop layer in the trench region through a conventional patterning process, and then the substrate 10 is etched using the etch stop layer pattern 30 as an etch mask to form an etch stop layer 30. Form the trench 40.

Annealing is performed to etch damage to the trench 40 sidewalls. In this case, the thermal oxide film 50 is formed on the substrate surface including the trench inner wall. Subsequently, the silicon nitride film liner 60 is formed on the entire surface of the substrate to achieve the state of FIG. 2. Here, the liner 60 prevents oxygen from being diffused by the oxide isolation film (70 in FIG. 3) filling the trench 40 in subsequent processes to oxidize the adjacent substrate 10. Accordingly, the liner 60 serves to prevent the surrounding substrate 10 crystals from being damaged due to the stress caused by the oxidation of the substrate 10 and prevent current leakage from occurring due to the crystal damage.

The silicon oxide film 70 is deposited on the entire surface of the substrate 10 through CVD to fill the trench as shown in FIG. 3. Subsequently, CMP is performed until the etch stop layer pattern 30 is exposed on the entire substrate. As a result, as shown in FIG. 4, the silicon oxide film remains only in the trench to form the device isolation layer 71.

In the step of exposing the active region to form the device, the etch stop layer pattern 30 is removed by a method such as phosphate wet etching. However, at this time, since the top of the liner 60 made of the same material as the etch stop layer pattern 30 is exposed, the top of the liner 60 between the thermal oxide film 50 and the CVD oxide film 70 filling the trench is also removed. Make a narrow gap In addition, the cleaning liquid having an etching force with respect to the silicon oxide film may be removed in the subsequent cleaning process through the narrow gap. As a result, as shown in FIG. 5, a dent phenomenon occurs in which the recess 80 is formed around the liner removed at the boundary between the device isolation layer 71 ′ and the active region.

If a dent occurs, there is a problem that a thin gate insulating film is formed around the concave gap 80. For example, when a transistor is formed in the active region, if the gap is filled with the gate film, the gate film of the gap is easily formed during the gate patterning process. It may remain without being removed. The residual film may have a long connection between the source region and the drain region to cause current leakage. On the other hand, when the residual film connected to the gate electrode acts on both edge portions of the channel together with the influence of the thinly formed gate insulating film, a high voltage is applied to the portion. In other words, some current flows through the channel before the threshold voltage is applied, which may also cause a hump phenomenon that makes the transistor characteristics unclear.

The present invention is to prevent the occurrence of a dent phenomenon and the occurrence of device defects such as the hump in the conventional trench type device isolation method described above, and to provide a trench type device separation method that can prevent the dent. do.

1 to 5 are process sectional views showing respective steps of the conventional trench isolation method;

6 to 12 are process cross-sectional views illustrating respective steps of a conventional trench isolation method.

In order to achieve the above object, the present invention provides a step of recessing a portion of the pad oxide layer under the etch stop layer pattern laterally through the substrate wet etching prior to the trench etching and the silicon nitride film liner in the conventional trench type isolation method. It is characterized in that the further provided.

That is, the present invention may include forming a pad film on a substrate, forming an etch stop film, and sequentially removing the etch stop film, the pad film, and the substrate from the trench region by using a patterning process to remove the etch stop film pattern, the pad film pattern, and the substrate. Forming a trench, isotropically etching the pad film pattern to recess the end of the pad film pattern laterally, forming a liner on the front surface of the substrate including the trench inner wall, and depositing a silicon oxide film on the front surface of the substrate Filling the trench; performing CMP until the etch stop layer pattern is exposed on the entire surface of the substrate; and removing the etch stop layer pattern by etching to expose the active region.

In the present invention, before the liner is formed, annealing is performed to cure the crystal damage caused by the trench sidewalls during the trench etching process, that is, a thermal oxide film is formed on the inner wall of the trench.

In the present invention, the pad film is usually formed of a silicon oxide film through thermal oxidation of a silicon substrate, but may be made of a silicon nitride film and another material having an etching selectivity with the substrate. In this case, as the isotropic etching material in the step of recessing the pad film laterally, one having a selectivity to the pad film should be used.

In the present invention, the liner or the anti-etching film uses a silicon nitride film, but it may also be assumed that the liner or the etching prevention film is made of a pad film and another material having an etching selectivity with the substrate. However, for the function of the liner, it should be formed of a material that can act as a barrier film that prevents oxygen diffusion.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

Referring to FIG. 6, the pad film 120 is formed on the surface of the substrate 100 for the purpose of stress relaxation before the etching prevention film is formed. The pad film 120 or the buffer layer is usually formed to a thickness of about 100 angstroms with a silicon oxide film through substrate thermal oxidation. An etch stop layer 130 is formed on the pad layer 120. The etch stop layer 130 is a material that can serve as an etch mask during etching for forming a trench in the substrate 100, and can act as an etch stopper for CMP in the process of forming an isolation layer. In general, the etch stop layer 130 may be formed with a silicon nitride layer having a thickness of about 1000 angstroms. Although not shown, a silicon oxide film for a hard mask may be further stacked on the etch stop layer 130.

Referring to FIG. 7, a trench 140 is formed in the substrate 100 by sequentially removing the etch stop layer, the pad layer, and the substrate from the trench region through a patterning process. For patterning, first, a photoresist pattern (not shown) that exposes the trench region is formed by photoresist film application, mask exposure, and development. The etch stop layer is etched using the photoresist pattern as an etch mask to form the etch stop layer pattern 130. At this time, the pad film is also removed to form the pad film pattern 120. The photoresist pattern is removed by a process such as ashing, and the trench 140 having a depth of thousands of angstroms is formed on the substrate using the etch stop layer pattern 130 as an etch mask.

7 and 8, a portion of the pad layer pattern 120 is removed by wet etching the substrate 100 on which the trench 140 is formed to form a recessed pad layer pattern 131. The pad layer pattern 120 is thin between the substrate 100 and the etch stop layer pattern 130. Therefore, the pad layer pattern 131 recessed through the wet etching has a form in which the peripheral portion is removed laterally from the periphery of the trench toward the active region. In this case, since only the pad layer pattern 120 should be recessed, the pad layer should have a selectivity with respect to the substrate and the etch stop layer with respect to a specific etching material.

Referring to FIG. 9, a thermal oxide film 150 is formed on the entire surface of the substrate or on the inner wall of the trench where the substrate silicon is exposed through heat treatment. Through heat treatment, the substrate surface damaged by the crystal structure during the trench etching process may be healed. Subsequently, silicon nitride film liner 160 is deposited on the entire surface of the substrate by CVD by about 50 to 100 angstroms. A method of forming a nitride film through substrate surface nitriding may also be considered, but adjustment is not easy. The silicon nitride film liner 160 may also be stacked in a concave shape on the recessed portion of the recessed pad film pattern 131. The length of the liner 160 in this portion is increased considerably compared with the case where the pad film pattern is not recessed.

Referring to FIG. 10, a silicon oxide film 170 is stacked. In this case, the lamination thickness may be sufficiently filled to fill all the trenches formed in the substrate, and the portion 165 recessed to the side of the recessed pad layer pattern 131 may be completely filled. In this case, the silicon oxide layer 170 is stacked to form a device isolation layer through the CMP, it is usually formed by CVD, a method such as SOG coating is also possible.

Referring to FIG. 11, a front surface CMP is performed on a substrate in which a trench is filled with a silicon oxide film 170. The CMP is performed to expose the etch stop layer pattern 130. Therefore, the silicon oxide layer 170 stacked on the entire surface of the substrate is removed from the upper surface of the etch stop layer pattern 130, and remains only in the trench to become the device isolation layer 171. In this case, since the liner 160 is concave, that is, the recessed pad layer pattern 131 end portion is under the etch stop layer pattern 130, the silicon oxide layer 170 is filled with the liner 160. The device isolation layer 171 is protected.

11 and 12, etching removal of the etch stop layer pattern 130 is performed. In general, wet etching having high etching efficiency is used, and phosphate wet etching is performed on the silicon nitride film. At this time, the exposed upper end of the liner 160 is also etched together. However, since the path is longer in cross-section than in the conventional case using the pad film recess, the upper end of the liner 160 is hardly etched down to the substrate surface 180. Therefore, when the recessed pad layer pattern 131 is removed and the substrate surface 180 of the active region is exposed, the top of the liner 160 included in the final device isolation layer 172 may be disposed on the silicon substrate surface 180. It is present and no dent occurs.

According to the present invention, it is possible to prevent the dent phenomenon, which is a chronic problem in the trench type device isolation method, through a relatively simple addition process of recessing the pad film.

Claims (4)

Forming a pad layer on the substrate and forming an etch stop layer on the pad layer; Forming an etch stop layer pattern, a pad layer pattern, and a substrate trench by sequentially removing the etch stop layer, the pad layer, and the substrate from the trench region using a patterning process; Isotropically etching the pad film pattern to recess the pad film pattern laterally; Forming a silicon nitride film liner on the entire surface of the substrate including an inner wall of the trench; Stacking a silicon oxide film on the entire surface of the substrate to fill the trench; Performing chemical mechanical polishing (CMP) until the etch stop layer pattern is exposed on the entire surface of the substrate; And removing the etch stop layer pattern by etching to expose an active region. The method of claim 1, And annealing the semiconductor sidewalls of the trench to heal crystal damages during the trench etching process before the forming of the silicon nitride film liner. The method of claim 1, The pad layer is a trench type device isolation method, characterized in that made of a silicon oxide film through thermal oxidation of the silicon substrate. The method of claim 1, And the liner and the etch stop layer are formed of a silicon nitride layer.