KR20030049571A - Method for forming metal line of semiconductor device using dual-damascene process - Google Patents
Method for forming metal line of semiconductor device using dual-damascene process Download PDFInfo
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- KR20030049571A KR20030049571A KR1020010079813A KR20010079813A KR20030049571A KR 20030049571 A KR20030049571 A KR 20030049571A KR 1020010079813 A KR1020010079813 A KR 1020010079813A KR 20010079813 A KR20010079813 A KR 20010079813A KR 20030049571 A KR20030049571 A KR 20030049571A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 61
- 239000002184 metal Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 56
- 239000011229 interlayer Substances 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000009977 dual effect Effects 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001227 electron beam curing Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 듀얼-다마신 공정을 이용한 금속배선 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring using a dual-damascene process.
반도체 메모리 소자의 집적도가 증가함에 따라, 메모리 셀들은 스택(Stack)구조화되고 있으며, 이에 따라, 각 셀들간의 전기적 연결을 위한 금속배선도 배선 설계를 용이하게 할 수 있는 다층 구조로 형성되고 있다. 이러한 다층금속배선 구조는 배선 설계가 자유롭고, 배선저항 및 전류용량 등의 설정을 여유있게 할 수 있다는 잇점이 있다.As the degree of integration of semiconductor memory devices increases, memory cells are stacked and thus, metal wiring diagrams for electrical connection between the cells are formed in a multilayer structure that can facilitate wiring design. Such a multilayer metal wiring structure has advantages in that the wiring design can be freely set and the setting of the wiring resistance and the current capacity can be made free.
한편, 금속배선 물질로서는 전기 전도도가 비교적 우수한 알루미늄(Al) 또는 그의 합금막이 주로 사용되어 왔으며, 최근에는 텅스텐은 물론, 알루미늄에 비해 전기 전도도가 더 우수한 구리(Cu)를 이용하려는 연구가 진행되고 있다.Meanwhile, aluminum (Al) or an alloy film thereof having relatively high electrical conductivity has been mainly used as a metal wiring material, and recently, studies have been conducted to use tungsten as well as copper (Cu) having better electrical conductivity than aluminum. .
이하에서는 종래의 금속배선 공정을 개략적으로 설명하도록 한다.Hereinafter, a conventional metallization process will be described schematically.
우선, 트랜지스터와 같은 소정의 하지층이 형성된 반도체 기판 상에 제1금속막을 증착한 상태에서, 상기 제1금속막 상에 공지의 포토리소그라피 공정을 통해 감광막 패턴을 형성하고, 이 감광막 패턴에 의해 가려지지 않은 제1금속막 부분을 식각하여 하부 금속배선을 형성한다.First, in a state in which a first metal film is deposited on a semiconductor substrate on which a predetermined base layer such as a transistor is formed, a photoresist pattern is formed on the first metal film through a known photolithography process, and covered by the photoresist pattern. A portion of the first metal film that is not supported is etched to form a lower metal wiring.
그런다음, 식각마스크로 이용된 감광막 패턴을 제거한 상태에서, 상기 하부 금속배선을 덮도록 기판의 전 영역 상에 HDP(High Density Plasma) 증착 방식에 의해 산화막을 증착한 후, CMP(Chemical Mechanical Polishing) 공정으로 그 표면을 연마하여 평탄한 표면을 갖는 층간절연막을 형성한다.Then, after removing the photoresist pattern used as an etch mask, an oxide film is deposited by HDP (High Density Plasma) deposition on the entire area of the substrate to cover the lower metal wiring, and then chemical mechanical polishing (CMP). The surface is ground by a step to form an interlayer insulating film having a flat surface.
다음으로, 상기 층간절연막의 일부분을 선택적으로 식각하여 하부 금속배선을 노출시키는 콘택홀을 형성하고, 이어서, 상기 콘택홀이 완전 매립되도록 층간절연막 상에 텅스텐막을 증착한 후, 상기 텅스텐막을 연마하여 상기 콘택홀 내에 상기 하부 금속배선과 전기적으로 콘택된 콘택플러그를 형성한다.Next, a portion of the interlayer insulating film is selectively etched to form a contact hole exposing the lower metal wiring, and then a tungsten film is deposited on the interlayer insulating film to completely fill the contact hole, and then the tungsten film is polished to A contact plug in electrical contact with the lower metal wire is formed in the contact hole.
그 다음, 콘택플러그 및 층간절연막 상에 제2금속막을 증착한 후, 포토리소그라피 공정을 통한 감광막 패턴의 형성, 상기 감광막 패턴을 이용한 제2금속막의 식각 및 상기 감광막 패턴의 제거를 차례로 수행하여 상기 콘택플러그와 콘택되는 상부 금속배선을 형성함으로써, 다층금속배선 구조를 완성한다.Then, after depositing the second metal film on the contact plug and the interlayer insulating film, the formation of the photoresist pattern through the photolithography process, the etching of the second metal film using the photoresist pattern and the removal of the photoresist pattern in order to perform the contact By forming the upper metal wiring in contact with the plug, the multilayer metal wiring structure is completed.
그러나, 종래 기술에 따라 금속배선을 형성할 경우에는, 도 1에 도시된 바와 같이, 금속막의 식각 특성과 관련하여 금속막의 건식 식각 후에 인접하는 금속배선들(4)간에 브릿지(Bridge : 10)가 발생할 수 있으며, 또한, 금속막이 화합물 형태로 잔류됨으로써 소자의 전기적 특성에 악영향을 미치는 문제점이 있다. 특히, 이러한 문제는 반도체 소자의 고집적화가 진행됨에 따라, 더욱 심각할 것으로 예상된다.However, in the case of forming the metal wiring according to the related art, as shown in FIG. 1, a bridge 10 between adjacent metal wirings 4 is formed after dry etching of the metal film with respect to the etching characteristics of the metal film. In addition, there is a problem that the metal film remains in the form of a compound, which adversely affects the electrical characteristics of the device. In particular, this problem is expected to be more serious as the integration of semiconductor devices proceeds.
도 1에서, 미설명된 도면부호 1은 반도체 기판, 2는 층간절연막, 그리고, 3은 콘택플러그를 각각 나타낸다.In FIG. 1, reference numeral 1 denotes a semiconductor substrate, 2 an interlayer insulating film, and 3 a contact plug, respectively.
한편, 상기한 문제를 해결하기 위해, 종래에는 다마신(damascene), 특히, 듀얼-다마신(dual-damascene) 공정을 이용한 금속배선 공정이 제안되었다. 여기서, 상기 듀얼-다마신 공정이란 콘택플러그 및 금속배선을 개별적 공정을 통해 각각 형성하는 방식이 아니라, 층간절연막 내에 콘택플러그 형성 영역을 포함한 금속배선이 형성될 영역을 미리 한정한 후에 금속막의 증착 및 금속막의 CMP를 통해 상기 콘택플러그 및 금속배선이 동시에 형성되도록 하는 공정이다.Meanwhile, in order to solve the above problem, a metal wiring process using a damascene, in particular, a dual-damascene process has been proposed. Here, the dual damascene process is not a method of forming contact plugs and metal wirings through separate processes, but rather defining a region in which an metal wiring including a contact plug forming region is to be formed in an interlayer insulating film, and then depositing a metal film. The contact plug and the metal wiring are simultaneously formed through the CMP of the metal film.
그런데, 자세하게 도시하고 설명하지는 않았지만, 종래의 듀얼-다마신 공정을 이용한 금속배선 공정은 콘택홀 및 금속배선 영역을 한정하기 위해 감광막 도포, 노광 및 현상을 포함하는 마스크 공정을 2회 실시하고 있으며, 아울러, 2회의 식각 공정을 수행하고 있기 때문에 공정이 다소 복잡한 문제점이 있다.By the way, although not shown and described in detail, the conventional metallization process using the dual-damascene process is performed two times the mask process including the photosensitive film coating, exposure and development to limit the contact hole and the metallization region, In addition, since the etching process is performed twice, the process is somewhat complicated.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 이웃하는 금속배선들간의 브릿지 발생을 방지할 수 있는 듀얼-다마신 공정을 이용한 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming metal wirings using a dual damascene process that can prevent the generation of bridges between neighboring metal wirings.
또한, 본 발명은 전체 공정 수를 줄일 수 있는 듀얼-다마신 공정을 이용한 금속배선 형성방법을 제공함에 그 다른 목적이 있다.In addition, another object of the present invention is to provide a method for forming metal wiring using a dual damascene process that can reduce the total number of processes.
도 1은 종래 문제점을 설명하기 위한 도면.1 is a view for explaining a conventional problem.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정 단면도.2A to 2G are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21 : 반도체 기판 22 : 층간절연막21 semiconductor substrate 22 interlayer insulating film
23 : 제1감광막 24 : 제2감광막23: first photosensitive film 24: second photosensitive film
25 : 감광막 패턴 26 : E-빔25 photosensitive film pattern 26 E-beam
27 ; 콘택플러그 28 : 금속배선27; Contact Plug 28: Metal Wiring
C : 콘택홀 T : 트렌치C: contact hole T: trench
상기와 같은 목적을 달성하기 위한 본 발명의 금속배선 형성방법은, 하지층이 구비된 반도체 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막 상에 포지티브형의 제1감광막을 도포하는 단계; 콘택 영역에 대응하는 상기 제1감광막 부분을 노광하는 단계; 상기 제1감광막 상에 네가티브형의 제2감광막을 도포하는 단계; 금속배선 영역에 대응하는 상기 제2감광막 부분을 노광하는 단계; 상기 노광된 제2 및 제2감광막 부분을 동시에 현상하여 T자형의 패턴을 갖는 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 E-빔으로 경화시키는 단계; 상기 경화된 감광막 패턴을 이용해서 노출된 층간절연막 부분을 식각하여 상기 층간절연막 내에 기판의 일부분을 노출시키는 콘택홀 및 금속배선 영역을 한정하는 트렌치를 형성하는 단계; 잔류된 감광막 패턴을 제거하는 단계; 상기 콘택홀 및 트렌치가 매립되도록 상기 층간절연막 상에 금속막을 증착하는 단계; 및 상기 층간절연막이 노출될 때까지 상기 금속막을 연마하는 단계를 포함한다.Metal wiring forming method of the present invention for achieving the above object, the step of forming an interlayer insulating film on a semiconductor substrate provided with a base layer; Applying a positive photosensitive film on the interlayer insulating film; Exposing the first photoresist portion corresponding to the contact region; Applying a negative photoresist film on the first photoresist film; Exposing the second photoresist portion corresponding to the metallization region; Simultaneously developing the exposed second and second photoresist portions to form a photoresist pattern having a T-shaped pattern; Curing the photoresist pattern with an E-beam; Etching the exposed portion of the insulating interlayer using the cured photoresist pattern to form a trench defining a contact hole and a metal wiring region exposing a portion of the substrate in the insulating interlayer; Removing the remaining photoresist pattern; Depositing a metal film on the interlayer insulating film to fill the contact hole and the trench; And polishing the metal film until the interlayer insulating film is exposed.
본 발명에 따르면, 듀얼-다마신 공정을 이용하는 것으로 인해 인접하는 금속배선들간의 브릿지 발생을 방지할 수 있으며, 아울러, 1회의 현상 및 식각 공정만으로 콘택홀 및 금속배선 영역이 한정되도록 하는 것으로 인해 전체 공정 수를 줄일 수 있다.According to the present invention, due to the dual damascene process, it is possible to prevent the generation of bridges between adjacent metal wires, and to limit the contact hole and the metal wire area by only one development and etching process. The number of processes can be reduced.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 자세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 소자의 다층금속배선 형성방법을 설명하기 위한 공정별 단면도이다.2A to 2G are cross-sectional views of processes for describing a method of forming a multilayer metal wiring of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 트랜지스터 및 하부 금속배선 등을 포함한 소정의 하지층(도시안됨)이 구비된 반도체 기판(21)을 마련하고, 상기 반도체 기판(21) 상에 HDP 방식으로 증착된 산화막으로 이루어지면서 후속하는 CMP 공정을 통해 표면 평탄화가 이루어진 층간절연막(22)을 형성한다. 그런다음, 상기 층간절연막(22) 상에 포지티브형의 제1감광막(23)을 도포하고, 콘택 형성용 레티클(reticle : 30)을 이용하여 콘택 형성 영역에 해당하는 상기 제1감광막 부분을 선택적으로 노광한다. 도면부호 23a는 노광된 제1감광막 영역을 나타낸다.Referring to FIG. 2A, a semiconductor substrate 21 having a predetermined base layer (not shown) including a transistor, a lower metal wiring, and the like is provided, and the oxide film is deposited on the semiconductor substrate 21 in an HDP manner. The interlayer insulating film 22 having the surface planarization is formed through a subsequent CMP process. Then, a positive first photosensitive film 23 is coated on the interlayer insulating film 22, and the portion of the first photosensitive film corresponding to the contact forming region is selectively selected using a contact forming reticle 30. It exposes. Reference numeral 23a denotes the exposed first photoresist film region.
도 2b를 참조하면, 선택적 노광이 이루어진 제1감광막(23) 상에 네가티브형의 제2감광막(24)을 도포하고, 배선 형성용 레티클(40)을 이용하여 금속배선 형성 영역을 제외한 나머지 영역에 대응하는 제2감광막 부분을 노광한다. 도면부호 24a는 노광된 제2감광막 영역을 나타낸다. 여기서, 상기 제2감광막(24)은 노광된 제1감광막 영역이 재차 노광되는 것을 방지하기 위해 네가티브형의 감광 물질로 이루어지도록 한 것이며, 아울러, 낮은 점성을 갖도록 해야 한다. 또한, 상기 제2감광막(24)은, 후속에서 설명되기는 하겠지만, 단순히 마스크의 역할만을 하므로, 도포 균일도(coating uniformity)는 크게 중요하지 않으며, 그래서, 과도 노광이 이루어져도 큰 문제는 발생되지 않는다.Referring to FIG. 2B, a negative second photoresist film 24 is applied onto the first photoresist film 23 subjected to selective exposure, and is applied to the remaining areas except the metal wiring formation area by using the wiring forming reticle 40. The corresponding second photosensitive film portion is exposed. Reference numeral 24a denotes the exposed second photosensitive film region. In this case, the second photoresist film 24 is made of a negative photosensitive material in order to prevent the exposed first photoresist film area from being exposed again, and should also have a low viscosity. In addition, although the second photosensitive film 24 will be described later, since it merely serves as a mask, the coating uniformity is not very important, so even if overexposure is made, no big problem occurs.
도 2c를 참조하면, 상기 결과물에 대해 1회의 현상 공정을 수행하여 노광된 제2감광막 영역 및 제1감광막 영역을 제거하고, 이 결과로서, 전체적으로 T자형의 감광막 패턴(25)을 형성한다. 그런다음, 이렇게 형성된 감광막 패턴(25)과 그 하부에 배치된 HDP 산화막 재질의 층간절연막(22)간의 식각 선택비(etch selectivity)를 조절하기 위해 E-빔(26)을 조사시켜 상기 감광막 패턴(25)을 경화(curing)시킨다.Referring to FIG. 2C, one development process is performed on the resultant to remove the exposed second photoresist region and the first photoresist region, and as a result, a T-shaped photoresist layer 25 is formed as a whole. Next, the E-beam 26 is irradiated to adjust the etch selectivity between the photoresist pattern 25 thus formed and the interlayer insulating layer 22 made of HDP oxide material disposed thereunder. 25) is cured.
여기서, 감광막과 HDP 산화막간의 식각선택비는 E-빔의 조사량과 조사시간에 따라 조절 가능하다. 또한, 상기 E-빔을 이용한 경화 공정 대신에 1차로 도포되는 포지티브형 제1감광막의 도포 두께를 조절함으로써, 감광막과 HDP 산화막간의 식각선택비, 즉, 콘택 형성시의 식각 깊이를 조절할 수도 있다.Here, the etching selectivity between the photosensitive film and the HDP oxide film can be adjusted according to the irradiation amount and the irradiation time of the E-beam. In addition, instead of the curing process using the E-beam, by controlling the coating thickness of the first positive photosensitive film to be applied first, the etching selectivity between the photosensitive film and the HDP oxide film, that is, the etching depth at the time of contact formation may be adjusted.
도 2d를 참조하면, 감광막 패턴(25)을 이용해서 노출된 층간절연막 부분을 1차로 건식식각한다. 이때, 감광막과 HDP 산화막간의 식각선택비에 의해, 상기 HDP 산화막으로된 층간절연막의 일부 두께가 식각되며, 동시에, 노출된 제1감광막 부분의 일부 두께가 함께 식각된다.Referring to FIG. 2D, the exposed portion of the interlayer insulating layer is primarily dry-etched using the photosensitive film pattern 25. At this time, by the etching selectivity between the photoresist film and the HDP oxide film, a part thickness of the interlayer insulating film made of the HDP oxide film is etched, and at the same time, a part thickness of the exposed first photoresist film part is etched together.
도 2e를 참조하면, 상기 결과물에 대해 2차로 건식식각을 수행하되, O2 가스를 첨가한 플라즈마 식각을 행하여 노출된 제1감광막 부분을 완전히 제거하고, 동시에, 층간절연막(22)의 일부 두께를 추가로 더 식각한다.Referring to FIG. 2E, dry etching is performed on the resultant in a secondary manner, and plasma etching with addition of O 2 gas is performed to completely remove the exposed first photoresist portion, and at the same time, to add a part thickness of the interlayer insulating layer 22. Etch more.
도 2f를 참조하면, 잔류된 감광막 패턴(25)을 이용해서 층간절연막(22)을 3차로 건식식각한다. 이 과정에서, 2회에 걸쳐 식각된 층간절연막 부분이 재차 식각되어 기판(21)을 노출시키는 콘택홀(C)이 형성되고, 동시에, 노출된 층간절연막의 상면 일부 두께가 함께 식각되어 금속배선 형성 영역을 한정하는 트렌치(T)가 혀엉된다.Referring to FIG. 2F, the interlayer insulating layer 22 is thirdly dry-etched using the remaining photoresist pattern 25. In this process, the portion of the interlayer insulating film etched twice is etched again to form a contact hole C exposing the substrate 21, and at the same time, the thickness of a part of the upper surface of the exposed interlayer insulating film is etched together to form a metal wiring. Trench T defining the area is tangled.
도 2g를 참조하면, 잔류된 감광막 패턴을 제거한 상태에서, 상기 콘택홀(C) 및 트렌치(T)가 완전 매립되도록 층간절연막(22) 상에 알루미늄, 구리, 텅스텐 등의 금속막을 증착하고, 이어, 상기 층간절연막(22)이 노출될 때까지 상기 금속막을 CMP 공정으로 연마하여 상기 콘택홀(C) 및 트렌치(T) 내에 기판, 또는, 하지층과 전기적으로 콘택되는 콘택플러그(27)를 포함한 금속배선(28)을 형성한다.Referring to FIG. 2G, a metal film of aluminum, copper, tungsten, or the like is deposited on the interlayer insulating film 22 so that the contact hole C and the trench T are completely filled in a state in which the remaining photoresist pattern is removed. And a contact plug 27 electrically contacting the substrate or the underlying layer in the contact hole C and the trench T by polishing the metal layer by the CMP process until the interlayer insulating layer 22 is exposed. The metal wiring 28 is formed.
상기와 같은 본 발명의 금속배선 형성방법은 다음과 같은 잇점을 갖는다.The metal wiring forming method of the present invention as described above has the following advantages.
첫째, 다마신 공정을 이용해서 금속배선을 형성기 때문에 인접하는 금속배선들간의 브릿지 발생이 근본적으로 일어나지 않는다.First, since the metal wiring is formed by using the damascene process, bridge generation between adjacent metal wirings does not occur fundamentally.
둘째, 종래의 듀얼-다마신 공정에서는 콘택홀 및 트렌치 형성을 위해 감광막 도포, 노광 및 현상을 포함하는 2회의 마스킹 공정을 수행해야 하고, 아울러, 2회의 식각 공정을 수행해야 하는 것으로 인해 전체 공정이 복잡한 문제점이 있지만, 본 발명의 듀얼-다마신 공정에서는 감광막의 도포 및 노광은 2회 수행하는 반면에현상 및 식각은 1회만 수행하므로, 공정 단순화를 얻을 수 있다.Second, in the conventional dual-damacin process, two masking processes including photoresist coating, exposure, and development must be performed to form contact holes and trenches, and in addition, two etching processes must be performed. Although there is a complicated problem, in the dual-damacin process of the present invention, the application and exposure of the photoresist film are performed twice while the development and etching are performed only once, so that the process can be simplified.
셋째, HDP 산화막과 감광막간의 식각선택비 조절을 위해, 종래의 듀얼-다마신 공정은 하드 베이킹(Hard baking)을 이용하지만, 본 발명의 공정은 E-빔 경화를 이용하므로, 그 조절도를 높일 수 있다.Third, in order to control the etching selectivity between the HDP oxide film and the photoresist film, the conventional dual-damacin process uses hard baking, but the process of the present invention uses E-beam curing, so that the control degree is increased. Can be.
이상에서와 같이, 본 발명은 듀얼-다마신 공정을 이용하여 금속배선을 형성하는 것으로 인해, 인접하는 금속배선들간의 브릿지 발생을 방지할 수 있으며, 이를 통해 금속배선의 신뢰성을 향상시킬 수 있다. 또한, 본 발명은 듀얼-다마신을 이용하되, 현상 및 식각 공정 수를 줄임으로써 공정 단순화를 얻을 수 있고, 이를 통해 생산성을 향상시킬 수 있다.As described above, the present invention can prevent the generation of bridges between adjacent metal wires by forming the metal wires by using the dual damascene process, thereby improving the reliability of the metal wires. In addition, the present invention uses dual-damacin, but by reducing the number of development and etching processes can obtain a process simplification, thereby improving productivity.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100676609B1 (en) * | 2005-09-13 | 2007-01-30 | 동부일렉트로닉스 주식회사 | Method for forming copper metal line and semiconductor device including the same |
| KR100744236B1 (en) * | 2005-12-23 | 2007-07-30 | 동부일렉트로닉스 주식회사 | Method for manufacturing dual damascene pattern |
| KR100947458B1 (en) * | 2003-07-18 | 2010-03-11 | 매그나칩 반도체 유한회사 | Method of manufacturing inductor in a semiconductor device |
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2001
- 2001-12-15 KR KR1020010079813A patent/KR20030049571A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100947458B1 (en) * | 2003-07-18 | 2010-03-11 | 매그나칩 반도체 유한회사 | Method of manufacturing inductor in a semiconductor device |
| KR100676609B1 (en) * | 2005-09-13 | 2007-01-30 | 동부일렉트로닉스 주식회사 | Method for forming copper metal line and semiconductor device including the same |
| KR100744236B1 (en) * | 2005-12-23 | 2007-07-30 | 동부일렉트로닉스 주식회사 | Method for manufacturing dual damascene pattern |
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