KR20010092074A - Semiconductor memory device having a high voltage word line driver circuit - Google Patents

Abstract

PURPOSE: A semiconductor memory device with a high voltage word line driver circuit is provided, which has an improved switching speed. CONSTITUTION: A source of a PMOS transistor(52) is connected to a power supply node(Vpp,64) and its drain is connected to a control node(60) or to the first control node, and its gate is connected to a control node(62) or to the second control node. A PMOS transistor(54) whose gate is connected to the control node(60) has a source-drain channel connected between the control nodes. An NMOS transistor(56) whose drain-source channel is connected between the control node(60) and ground voltage has a gate connected to receive a select signal(WDen) through an inverter(50). A drain-source channel of an NMOS transistor(58) is connected between the control node(62) and the ground voltage and its gate is connected to be supplied with the select signal directly. A PMOS transistor(66) whose gate is connected to the control node(62) has a source-drain channel connected between a node(66) and a word line(WL) connected to a memory cell, and an NMOS transistor(68) has a drain-source channel connected between the word line and the ground voltage and a gate connected to the control node(62). An NMOS transistor(70) and a depletion mode NMOS transistor(72) are connected serially between an output terminal of the inverter and the control node(62). Gates of transistors(70,72) are connected to receive the select signal in common.

Description

A semiconductor memory device having a high voltage word line driver circuit {SEMICONDUCTOR MEMORY DEVICE HAVING A HIGH VOLTAGE WORD LINE DRIVER CIRCUIT}

The present invention relates to a semiconductor memory device, and more particularly, to a high voltage word line driver circuit of a nonvolatile semiconductor memory device.

As is well known, integrated circuit electronic devices, although interlocked with each other, include circuitry that operates at different voltage levels and is powered separately. In addition, some of such circuits require different supply voltages depending on the mode of operation. For example, in nonvolatile semiconductor memory devices such as electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash, and the like, drivers, decoding, redundancy, programming circuits and the like. The same various circuits operate at different voltages depending on the mode of operation, and therefore must be connected to well known circuits such as "level shifters" (called high voltage switching circuits, level converters, etc.).

Examples for such level shifters are described in US Pat. No. 5,214,602, entitled “ DYNAMIC MEMORY WORD LINE DRIVER SCHEME, ” US Pat. No. 5,315,188, entitled " HIGH VOLAGE SWITCHING CIRCUIT ", US Pat. No. 5,602,796 entitled " WORD LINE DRIVER IN A SEMICONDUCTOR MEMORY DEVICE ", and US Pat. No. 5,959,902, entitled " VOLATGE LEVEL SHIFTER DEVICE, PARTICULARY FOR A NONVOLATILE MEMORY ", each incorporated by reference.

Referring to FIG. 1, a word line driver circuit well known in the art is shown. The word line driver circuit 10 includes a level shifter 12 and a driver 14, and drives the word line WL connected to the memory cell MC in response to the selection signal WDen. In particular, the word line driver circuit 10 is used in a nonvolatile semiconductor memory device having electrically erasable and programmable memory cells and delivers a high voltage to the word line WL. The high voltage is a voltage required for program / erase operation and is higher than a junction breakdown voltage (for example, a high voltage of + 7V or more) of the low-voltage NMOS transistor.

The level shifter 12 of FIG. 1 performing the same function as shown in the aforementioned reference (see FIG. 3 of US Pat. No. 5,959,902) includes an inverter 20, two PMOS transistors 22, 24, And two NMOS transistors 26 and 28. Cross-connected PMOS transistors 22, 24 have source-drain channels connected between power supply node 30, denoted Vpp, and corresponding control nodes 32, 34, respectively. The gate of the PMOS transistor 22 is connected to the control node 34, and the gate of the PMOS transistor 24 is connected to the control node 32. The drain-source channel of the NMOS transistor 26 is connected between the control node 32 and the ground voltage, and the gate is connected through the inverter 20 to receive the selection signal WDen. The drain-source channel of the NMOS transistor 28 is connected between the control node 34 and the ground voltage, and the gate is connected to directly receive the select signal WDen. The control node 34 used as the output of the level shifter 12 is connected with a driver 14 composed of a pull-up PMOS transistor 36 and a pull-down NMOS transistor 38.

In FIG. 1, transistors 22, 24, 26, 28, 36, 38 are implemented using transistors for high voltage (Vpp), and inverter 20 is a power supply voltage (Vdd) lower than high voltage (Vpp) as a power source. Use

In circuit operation, when the select signal WDen is at a logic low level (when the word line is not selected), the NMOS transistor 26 is turned on while the NMOS transistor 28 is turned off. This causes the control node 34 to charge to the high voltage Vpp via the PMOS transistor 24. As a result, the word line WL is grounded through the NMOS transistor 38 of the driver 14. In contrast, when the select signal WDen is at a logic high level (when a word line is selected), the NMOS transistor 26 is turned off while the NMOS transistor 28 is turned on. This causes the charged voltage of the control node 34 via the NMOS transistor 28 to discharge to ground voltage. As a result, the word line WL is supplied with a high voltage Vpp through the PMOS transistor 36 of the driver 14.

Substantially, the word line driver circuit 10 of FIG. 1 operates normally, but has a slow driving speed (or a long time from the activation time of the selection signal to the activation time of the word line). The speed of the word line driver circuit 10 is determined by the switching speed of the level shifter 12 (or the high-low transition time of the output node of the control node 34, i.e., the level shifter 12). As is well known to those skilled in the art, in general, the discharge capability of the high voltage NMOS transistor 28 is characterized by the structural characteristics of the high voltage NMOS transistor (e.g., a double diffusion structure of source and drain) double diffusion struture), which is lower than the discharge capability of low-voltage NMOS transistors (meaning the ability to sufficiently discharge any charged voltage to ground voltage). Therefore, the word line driver circuit 10 of FIG. 1 is unsuitable for a high speed memory device.

It is an object of the present invention to provide a word line driver circuit of a semiconductor memory device having an improved switching speed.

1 is a circuit diagram showing a word line driver circuit of a semiconductor memory device according to the prior art;

2 is a circuit diagram showing a word line driver circuit of a semiconductor memory device according to the present invention;

3 is a diagram for comparing the speed of the word line driver circuit of the prior art and the present invention;

4 is a circuit diagram illustrating a word line driver circuit of a semiconductor memory device according to another embodiment of the present invention; And

5 is a circuit diagram illustrating a word line driver circuit of a semiconductor memory device according to still another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10, 100, 100 ', 100 ": word line driver circuit

(Configuration)

According to a feature of the present invention for achieving the above object, a driver circuit used in a semiconductor memory device accepts an input signal having one of a power supply voltage and a ground voltage, and sets the voltage level of the input signal to the ground voltage and the high voltage. A level shifter for converting to any one of; The high voltage is greater than the junction breakdown voltage of the low voltage NMOS transistor; A driver for driving the output terminal of the driver circuit to one of the high voltage and ground voltage in accordance with the voltage level of the output signal output from the level shifter; And a discharge circuit connected to an output terminal of the level shifter and discharging a voltage at an output terminal of the level shifter in association with the level shifter according to the input signal.

In this embodiment, the level shifter includes a pair of cross-connected PMOS transistors, a pair of control nodes, a power supply node receiving the high voltage, and one of the control nodes is connected to the level shifter. An inverter having an input connected to the input signal, the inverter forming an output stage, and a pair of NMOS transistors each connected between a corresponding control node of the control nodes and the ground voltage, and one of the NMOS transistors. A gate is connected to the output of the inverter, a gate of another NMOS transistor is connected to the input signal, and each transistor is a high voltage transistor.

In this embodiment, the discharging means includes a low voltage NMOS transistor and a depletion-type NMOS transistor, wherein the low voltage NMOS transistor comprises a channel connected between an output terminal of the level shifter and an output terminal of the inverter; The depletion type NMOS transistor has a channel connected between an output terminal of the level shifter and the low voltage NMOS transistor, and a gate connected to receive the input signal.

(Action)

According to this circuit, the switching speed of the level shifter is improved by adding a low voltage NMOS transistor to the level shifter used in the high voltage word line driver circuit.

(Example)

Embodiments according to the present invention are described in detail below on the basis of reference drawings.

A word line driver circuit according to a preferred embodiment of the present invention is shown in FIG. The word line driver circuit 100 of the present invention is used in a semiconductor memory device, in particular, a nonvolatile semiconductor memory device (e.g., EPROM, EEPROM, flash, etc.), and according to a selection signal, the memory cell (or floating gate memory cell). Delivers a high voltage (Vpp) to the word line connected to the transistor). The high voltage Vpp is a voltage required for program / erase operation and is higher than the junction breakdown voltage of the low-voltage NMOS transistor (for example, a high voltage of + 7V or more).

Referring to FIG. 2, the source of the PMOS transistor 52 is connected to a power supply node 64 labeled "Vpp", the drain is connected to the control node 60 or the first control node, and the gate is connected to the control node ( 62) or a second control node. PMOS transistor 54 whose gate is connected to control node 60 has a source-drain channel connected between nodes 64 and 62. The NMOS transistor 56 having a drain-source channel connected between the control node 60 and the ground voltage has a gate connected to receive the selection signal WDen through the inverter 50. The drain-source channel of the NMOS transistor 58 is connected between the control node 62 and the ground voltage, and the gate is connected to receive the selection signal WDen directly.

The PMOS transistor 66 with its gate connected to the control node 62 has a source-drain channel connected between the node 66 and the word line WL connected to the memory cell, and the NMOS transistor 68 has a word line WL. And a drain-source channel connected between and a ground voltage, and a gate connected to the control node 62. Between the output terminal (or gate of the NMOS transistor 56) of the inverter 50 and the control node 62, the NMOS transistor 70 and the depletion type NMOS transistor 72 are connected in series. Gates of the transistors 70, 72 are connected to accept the select signal WDen in common.

In FIG. 2, PMOS and NMOS transistors 52-68 are each implemented using a transistor for high voltage (Vpp), and NMOS transistor 70 is implemented using a transistor for low voltage. The inverter 50 uses the power supply voltage Vdd as a power supply. The cross-connected PMOS transistors 52, 54 and NMOS transistor 56 constitute a pull-up circuit that charges the control node 62 to a high voltage (Vpp) in response to the output signal of the inverter 50, and the NMOS Transistors 58, 70, 72 constitute a pull-down circuit that discharges the charged voltage Vpp of control node 62 to ground voltage in response to select signal WDen. Then, the PMOS and NMOS transistors 66 and 68 constitute a driver, and the pull-down circuit, the pull-up circuit and the inverter 50 constitute a level shifter.

In FIG. 2, the drain of the NMOS transistor 70 is connected to the output terminal of the inverter 50, but may be directly connected to the ground voltage.

In circuit operation, when the select signal WDen is at a logic low level (when no word line is selected), the NMOS transistor 56 is turned on while the NMOS transistor 58 is turned off. At the same time, the NMOS transistor 70 is also turned off. This causes the control node 62, which forms the output stage of the level shifter, through the PMOS transistor 54 to be charged to high voltage Vpp. As a result, the word line WL is grounded through the NMOS transistor 68. Here, when the high voltage (Vpp) is charged to the control node 62, the gate oxide film breakdown of the low-voltage NMOS transistor 70 due to the junction breakdown voltage caused by the high voltage (Vpp) or the breakdown voltage induced in the gate. Is prevented by the depletion type NMOS transistor 72.

In contrast, when the select signal WDen is at a logic high level (when a word line is selected), the NMOS transistor 56 is turned off while the NMOS transistor 58 is turned on. The low voltage NMOS transistor 70 whose gate is connected to the select signal WDen is also turned on. This is through the high voltage NMOS transistor 58 where the charged voltage of the control node 62 forms the first discharge path and the depletion type PMOS transistor 72 and the low voltage NMOS transistor 70 which form the second discharge path. And a discharge to ground voltage through a pull-down transistor (not shown) of inverter 50. As a result, the word line WL is supplied with the high voltage Vpp through the PMOS transistor 66.

As described above, when the select signal WDen has a low-high transition, the charged voltage of the control node 62 is the first discharge path composed of the high voltage NMOS transistor 58 and the low voltage NMOS transistor 70. Is quickly discharged to the ground voltage level through a second discharge path consisting of This speeds up the switching speed of the level shifter, that is, the discharge speed, and as a result, the speed of the word line driver circuit (or the time from the time of activation of the selection signal to the time of driving of the word line) is increased. As can be seen in Figure 4, the speed of the word line driver circuit 100 according to the present invention is about 3.2 kW as compared to the driver circuit 10 of the prior art. Therefore, the word line driver circuit according to the preferred embodiment of the present invention is suitable for a high speed memory device.

Word line driver circuits according to other embodiments of the present invention are shown in FIGS. 4 and 5, respectively. Referring to FIG. 4, the word line driver circuit 100 ′ is the same as the word line driver circuit 100 of FIG. 2 except that the depletion type NMOS transistor 72 of FIG. 2 is replaced by the PMOS transistor 82. Do. The gate of the PMOS transistor 82 is connected to the output of the inverter 50, the source-drain channel is connected between the control node 62 and the low voltage NMOS transistor 70, and the bulk is connected to the control node 62. do. In order to avoid duplication of explanation, the description of the operation of the word line driver circuit 100 'of FIG. 4 is omitted here. However, the word line driver circuit 100 'of FIG. 4 also has the same effect as that of FIG.

The word line driver circuit 100 ″ in FIG. 5 is identical to FIG. 4 except that an NMOS transistor 92 is added to the word line driver circuit 100 ′ in FIG. 4, and the NMOS transistor 92 is controlled. And a drain-source channel connected between the node 62 and the low voltage NMOS transistor 70, and a gate supplied with a bias voltage Bis at a level lower than the power supply voltage Vdd. The description of the operation of the word line driver circuit 100 " However, the word line driver circuit 100 "of FIG. 5 also has the same effect as that of FIG.

As described above, the switching speed of the level shifter is improved by adding a low voltage NMOS transistor to the level shifter used in the high voltage word line driver circuit. As a result, the speed of the high voltage word line driver circuit is improved.

Claims (20)

In driver circuits used in semiconductor memory devices: A level shifter which receives an input signal having one of a power supply voltage and a ground voltage, and converts a voltage level of the input signal into one of the ground voltage and the high voltage; The high voltage is greater than the junction breakdown voltage of the low voltage NMOS transistor; A driver for driving the output terminal of the driver circuit to one of the high voltage and ground voltage in accordance with the voltage level of the output signal output from the level shifter; And means for discharging a voltage at an output terminal of the level shifter in association with the level shifter in response to the input signal. The method of claim 1, The level shifter includes a pair of cross-connected PMOS transistors, a pair of control nodes, a power supply node receiving the high voltage, and one of the control nodes forms an output terminal of the level shifter, An inverter having an input connected to an input signal, a pair of NMOS transistors each connected between a corresponding control node of the control nodes and the ground voltage, and a gate of one of the NMOS transistors at an output of the inverter. And a gate of another NMOS transistor connected to the input signal, wherein each transistor is a high voltage transistor. The method of claim 2, The means includes a low voltage NMOS transistor, the low voltage NMOS transistor having a channel connected between an output terminal of the level shifter and an output terminal of the inverter, and a gate connected to receive the input signal. The method of claim 3, wherein The means additionally includes a depletion-type NMOS transistor, wherein the depletion-type NMOS transistor is a channel connected between an output terminal of the level shifter and the low voltage NMOS transistor and a gate connected to receive the input signal. A driver circuit of a semiconductor memory device having a. The method of claim 3, wherein The means additionally includes a PMOS transistor, the PMOS transistor having a channel connected between an output terminal of the level shifter and the low voltage NMOS transistor, and a gate connected to an output terminal of the inverter, wherein the bulk of the PMOS transistor is Driver circuit of the semiconductor memory device connected to the output terminal of the level shifter. The method of claim 5, And the means further comprises a low voltage NMOS transistor having a channel connected between the output terminal of the level shifter and the low voltage NMOS transistor and a gate connected to receive a bias voltage lower than a power supply voltage. At least one word line coupled to the memory cell; A semiconductor memory device having a word line driver circuit coupled to the at least one word line, the semiconductor memory device comprising: The word line driver circuit is An inverter receiving a selection signal for selecting the at least one word line; A pull-up circuit for charging a control node to a high voltage in response to an output signal of the inverter; A pull-down circuit having first and second discharge paths commonly connected to the control node and discharging a voltage charged to the control node through the first and second discharge paths in response to the selection circuit; And a driver connected to the control node and driving the word line to one of the high voltage and the ground voltage according to the voltage of the control node. The method of claim 7, wherein The semiconductor memory device includes a nonvolatile semiconductor memory device. The method of claim 7, wherein And the high voltage is higher than a junction breakdown voltage of a low voltage NMOS transistor. The method of claim 7, wherein And the first discharge path includes a high voltage NMOS transistor, the NMOS transistor having a channel connected between the control node and the ground voltage and a gate connected to receive an output signal of the inverter. The method of claim 7, wherein And the second discharge path includes a low voltage NMOS transistor, the NMOS transistor having a channel connected between the control node and an output terminal of the inverter and a gate connected to receive the selection signal. The method of claim 11, And the second discharge path further includes a depletion MOS transistor, the MOS transistor having a channel connected between the control node and the NMOS transistor and a gate connected to receive the selection signal. The method of claim 11, The second discharge path additionally includes a PMOS transistor, the PMOS transistor having a channel connected between the control node and the NMOS transistor and a gate connected to an output terminal of the inverter, the bulk of the PMOS transistor being the control node. The semiconductor memory device connected to. The method of claim 13, The second discharge path additionally includes a second NMOS transistor, the NMOS transistor having a channel coupled between the control node and the first NMOS transistor and a semiconductor memory having a gate connected to receive a bias voltage lower than a power supply voltage. Device. The method of claim 7, wherein The pull-up circuit includes cross-connected PMOS transistors and NMOS transistors, each transistor including a high voltage transistor. In a word line driver circuit used in a semiconductor memory device: A first PMOS transistor having a source-drain channel connected between a high voltage supplying power supply node and a first control node; A second PMOS transistor having a source-drain channel connected between the power supply node and a second control node and a gate connected to the first control node; A gate of the first PMOS transistor is connected to the second control node; A first NMOS transistor having a drain-source channel connected between the first control node and a ground voltage and a gate connected to receive a selection signal through an inverter; A second NMOS transistor having a drain-source channel connected between the second control node and the ground voltage and a gate connected to directly receive the selection signal; A driver coupled to the second control node and driving a row line coupled to a memory cell according to the voltage level of the second control node; And a third NMOS transistor having a drain-source channel connected between the second control node and an output terminal of the inverter and a gate connected to receive the selection signal. The method of claim 16, And the first and second PMOS transistors and the first and second NMOS transistors are high voltage transistors, and the third NMOS transistors are low voltage transistors. The method of claim 17, And said high voltage has a voltage level greater than a junction breakdown voltage of a low voltage NMOS transistor. The method of claim 18, And a depletion type NMOS transistor, wherein the depletion type NMOS transistor has a drain-source channel connected between the second control node and the third NMOS transistor and a gate connected to directly receive the selection signal. Word line driver circuit in the device. The method of claim 18, And a low voltage PMOS transistor, said PMOS transistor having a source-drain channel connected between said second control node and said third NMOS transistor and a gate directly connected to an output terminal of said inverter. Line driver circuit.