KR20010045256A - A method of improving an etch profile - Google Patents
A method of improving an etch profile Download PDFInfo
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- KR20010045256A KR20010045256A KR1019990048483A KR19990048483A KR20010045256A KR 20010045256 A KR20010045256 A KR 20010045256A KR 1019990048483 A KR1019990048483 A KR 1019990048483A KR 19990048483 A KR19990048483 A KR 19990048483A KR 20010045256 A KR20010045256 A KR 20010045256A
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 229920000642 polymer Polymers 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 식각 프로파일 개선방법에 관한 것으로서, 특히, α-실리콘과 TiW로 이루어진 앤티-퓨즈부를 건식식각으로 개방할 때 종래 기술의 식각제인 BCl3와 SF6의 혼합기체에 N2를 첨가하여 식각부위 측면에 폴리머를 증착시키므로서 TiW측면의 식각량을 보상하여 전체적인 식각면의 프로파일을 개선하도록 한 반도체장치의 앤티-퓨즈부 식각방법에 관한 것이다.The present invention relates to a method for improving an etching profile, and in particular, when the anti-fuse part consisting of α-silicon and TiW is opened by dry etching, etching is performed by adding N 2 to a mixed gas of BCl 3 and SF 6 , which are conventional etching agents. The present invention relates to an anti-fuse part etching method of a semiconductor device to compensate for the etching amount on the TiW side by depositing a polymer on the side of the portion to improve the profile of the entire etching surface.
앤티-퓨즈부는 반도체기판상에 각종 소자들로 구성된 회로의 소정 부분을 개방시켜 필요한 회로를 구성한다. 따라서, 필요에 따라 소정부위의 앤티-퓨즈부를 건식식각으로 식각하여 제거한다.The anti-fuse part opens a predetermined portion of a circuit composed of various elements on a semiconductor substrate to constitute a necessary circuit. Therefore, if necessary, the anti-fuse part of the predetermined portion is removed by dry etching.
종래 기술에서는 TiW와 α-실리콘의 적층구조를 갖는 소정 부위의 앤티-퓨즈부를 제거하기 위하여 식각제로 SF6를 사용하고 식각부위의 프로파일(profile)을 개선하기 위하여 BCl3를 사용한다.In the prior art, SF 6 is used as an etchant to remove an anti-fuse portion of a predetermined region having a stacked structure of TiW and α-silicon and BCl 3 is used to improve the profile of the etching region.
도 1은 반도체장치의 앤티-퓨즈부(anti-fuse) 단면도이다.1 is a cross-sectional view of an anti-fuse portion of a semiconductor device.
도 1을 참조하면, 각종 소자들과 절연층이 형성된 반도체 기판인 실리콘기판(10)상에 소자들을 전기적으로 연결하는 알루미늄으로 이루어진 배선층(11)이 형성 되어 있다.Referring to FIG. 1, a wiring layer 11 made of aluminum is formed on a silicon substrate 10, which is a semiconductor substrate on which various elements and an insulating layer are formed.
배선층(11)을 포함하는 기판(10)상에 배선절연층(intermetal dielectric,32)이 소정 두께로 형성되어 있다.A wiring insulating layer 32 is formed on the substrate 10 including the wiring layer 11 to have a predetermined thickness.
배선절연층(12)의 소정 부분이 제거되어 배선층(11)의 일부 표면을 노출시키는 비어 홀(via hole)이 형성되어 있다.A predetermined portion of the wiring insulation layer 12 is removed to form a via hole exposing a part of the surface of the wiring layer 11.
비어홀에 의하여 노출된 배선층(11) 표면과 비어홀 내부 측면 및 배선절연층(12)의 일부 표면 까지 연장된 부위에 α-실리콘층(13)이 패터닝되어 있으며, 그 위에는 TiW층(14)이 형성되어 있다.The α-silicon layer 13 is patterned on the surface of the wiring layer 11 exposed by the via hole, the inner side surface of the via hole and a part of the wiring insulating layer 12, and the TiW layer 14 is formed thereon. It is.
α-실리콘층(13)과 TiW층(14)은 적층구조를 이루며 앤티-퓨즈부를 형성한다.The α-silicon layer 13 and the TiW layer 14 form a laminated structure and form an anti-fuse part.
도 2a와 도 2b는 각각 종래 기술에 따라 식각된 앤티퓨즈부의 단면도와 레이아웃이다.2A and 2B are cross-sectional views and layouts of anti-fuse portions etched according to the prior art, respectively.
도 2a와 도 2b를 참조하면, 도 1에 따라 형성된 앤티-퓨즈부와 유사한 구조에 대하여 건식식각을 실시하여 배선층(21)의 소정부위를 노출시킨다.2A and 2B, dry etching is performed on a structure similar to the anti-fuse part formed in FIG. 1 to expose a predetermined portion of the wiring layer 21.
이때, 앤티-퓨즈부는 상층에 TiW층(24_이 위치하고 그 하부에 α-실리콘층(23)이 위치한 구조로 패터닝되어 있다.At this time, the anti-fuse part is patterned in a structure in which the TiW layer 24_ is positioned above and the α-silicon layer 23 is located below.
이러한 앤티퓨즈부의 비어홀 저면에 위치한 배선층(21) 상부를 노출시키는 포토레지스트패턴(도시안함)을 배선절연층(22) 상에 형성한 다음, 포토레지스트패턴을 식각마스크로 이용하는 건식식각을 앤티-퓨즈부에 실시하여 비어홀에 의하여 노출되는 배선층(21)의 전부를 노출시킨다.A photoresist pattern (not shown) is formed on the wiring insulation layer 22 to expose the upper portion of the wiring layer 21 located on the bottom of the via hole. The dry etching using the photoresist pattern as an etching mask is then performed. The entirety of the wiring layer 21 exposed by the via hole is performed at the portion.
이때, 식각제로는 Bl3와 SF6를 같이 사용하며, 유량은 각각 40, 25 sccm으로 하고 공정압력은 저압으로 약 10-13mT로 유지하며 약 40W의 파워로 소정 시간(약 70초) 실시한다. SF6는 식각제이고 Bl3는 식각 프로파일 개선제로 사용된다.At this time, Bl 3 and SF 6 are used together, and the flow rate is 40 and 25 sccm, respectively, and the process pressure is maintained at about 10-13mT at low pressure and is performed for a predetermined time (about 70 seconds) with a power of about 40W. . SF 6 is an etchant and Bl 3 is used as an etching profile improver.
식각 후 포토레지스트패턴을 제거한 기판의 단면도가 도시되어 있다.A cross-sectional view of the substrate with the photoresist pattern removed after etching is shown.
식각된 앤티-퓨즈부의 단면은 앤티-퓨즈부의 상부구조인 TiW층(24)의 단면 프로파일(R)이 불규칙한 형태를 갖게 된다.The cross-section of the etched anti-fuse part has an irregular cross-sectional profile R of the TiW layer 24, which is the upper structure of the anti-fuse part.
따라서, 상술한 종래 기술에 따른 식각방법은 TiW층 식각시 측벽 부위에 폴리머의 증착이 용이하게 일어나지 않으므로 사이드 에치되어 평면 전자주사현미경으로 관찰할 때 TiW층의 측면 프로파일이 매우 불량하게 되어 소자의 신뢰성을 저하시키는 문제점이 있다.Therefore, the etching method according to the related art described above does not easily occur in the deposition of polymer on the sidewalls during the TiW layer etching, so that the side profile of the TiW layer becomes very poor when observed with a planar electron scanning microscope because of side etch. There is a problem of lowering.
따라서, 본 발명의 목적은 α-실리콘과 TiW로 이루어진 앤티-퓨즈부를 건식식각으로 개방할 때 종래 기술의 식각제인 BCl3와 SF6의 혼합기체에 N2를 첨가하여 식각부위 측면에 폴리머를 증착시키므로서 TiW측면의 식각량을 보상하여 전체적인 식각면의 프로파일을 개선하도록 한 반도체장치의 앤티-퓨즈부 식각방법을 제공하는데 있다.Accordingly, an object of the present invention is to deposit a polymer on the side of the etching site by adding N 2 to the mixed gas of BCl 3 and SF 6 , which is a conventional etching agent, when the anti-fuse part consisting of α-silicon and TiW is opened by dry etching. The anti-fuse part etching method of the semiconductor device to compensate the etching amount of the TiW side to improve the overall etching surface profile.
상기 목적을 달성하기 위한 본 발명에 따른 식각 프로파일 개선방법은 기판의 소정 부위에 형성된 배선을 노출시키는 홀이 형성된 절연층상에 홀을 소정 두께로 덮으며 절연층상의 일부까지 연장된 적층구조의 앤티-퓨즈부를 형성하는 단계와, 홀에 대응하는 앤티퓨즈부의 소정 부위를 노출시키는 식각마스크를 앤티퓨즈부와 절연층상에 형성하는 단계와, 식각마스크로 보호되지 않는 부위의 앤티퓨즈부를 질소를 첨가한 식각제로 제거하여 홀을 통한 배선의 표면을 노출시키는 단계와, 식각마스크를 제거하는 단계를 포함하여 이루어진다.The etching profile improvement method according to the present invention for achieving the above object is to cover the hole with a predetermined thickness on the insulating layer is formed on the hole is formed to expose the wiring formed in a predetermined portion of the substrate and having an anti-lamination structure extending to a portion on the insulating layer Forming a fuse portion, forming an etching mask exposing a predetermined portion of the antifuse portion corresponding to the hole on the antifuse portion and the insulating layer, and etching the antifuse portion of the portion not protected by the etching mask by adding nitrogen Removing zero to expose the surface of the wiring through the hole, and removing the etching mask.
도 1은 반도체장치의 앤티-퓨즈부(anti-fuse) 단면도1 is a cross-sectional view of an anti-fuse of a semiconductor device
도 2a와 도 2b는 각각 종래 기술에 따라 식각된 앤티퓨즈부의 단면도와 레이아웃2A and 2B are cross-sectional views and layouts of anti-fuse portions etched according to the prior art, respectively.
도 3a와 도 3b는 각각 본 발명에 따라 식각된 앤티퓨즈부의 단면도와 레이아웃3A and 3B are cross-sectional views and layouts of antifuse portions etched according to the present invention, respectively.
본 발명은 금속과 비정질실리콘으로 이루어진 앤티-퓨즈부 개방시 식각제에 질소를 첨가하여 식각공정을 진행하므로서 식각부위 측벽에 폴리머가 증착되는 성질을 이용하여 식가부위의 프로필을 개선한다.The present invention improves the profile of the etched portion by using a property of depositing a polymer on the sidewall of the etched portion by adding nitrogen to the etchant during opening of the anti-fuse portion made of metal and amorphous silicon.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3a와 도 3b는 각각 본 발명에 따라 식각된 앤티퓨즈부의 단면도와 레이아웃이고, 특히, 도 3b는 이러한 구조를 전자주사현미경(SEM)으로 촬영한 레이아웃의 모식도이다.3A and 3B are cross-sectional views and layouts of anti-fuse portions etched according to the present invention, respectively, and in particular, FIG. 3B is a schematic diagram of a layout photographing such a structure with an electron scanning microscope (SEM).
도 3a와 도 3b를 참조하면, 각종 소자들과 절연층이 형성된 반도체 기판인 실리콘기판(30)상에 소자들을 전기적으로 연결하는 알루미늄으로 이루어진 배선층(31)이 형성 되어 있고, 배선층(31)을 포함하는 기판(30)상에 배선절연층(intermetal dielectric,32)이 소정 두께로 형성되어 있다.3A and 3B, a wiring layer 31 made of aluminum is formed on the silicon substrate 30, which is a semiconductor substrate on which various elements and an insulating layer are formed, and the wiring layer 31 is formed. A wiring insulating layer 32 is formed on the substrate 30 including a predetermined thickness.
배선절연층(32)의 소정 부분이 제거되어 배선층(331)의 일부 표면을 노출시키는 비어 홀(via hole)이 형성되어 있다.A predetermined portion of the wiring insulating layer 32 is removed to form a via hole exposing a part of the surface of the wiring layer 331.
비어홀에 의하여 노출된 배선층(31) 표면과 비어홀 내부 측면 및 배선절연층(32)의 일부 표면 까지 연장된 부위에 α-실리콘층(33)/TiW층(34)이 패터닝되어 앤티-퓨즈부가 형성되고, 이러한 앤티-퓨즈부 개방을 위한 건식식각을 실시한 모습이 도시되어 있다.The α-silicon layer 33 / TiW layer 34 is patterned on the surface of the wiring layer 31 exposed by the via hole, the inner side surface of the via hole, and a portion of the wiring insulating layer 32 to form an anti-fuse part. The dry etching for opening the anti-fuse part is shown.
도 1에 도시된 구조와 같은 앤티-퓨즈부에 대하여 건식식각을 실시하여 배선층(31)의 소정부위를 노출시킨다.Dry etching is performed on the anti-fuse portion as shown in FIG. 1 to expose a predetermined portion of the wiring layer 31.
이때, 앤티-퓨즈부는 상층에 TiW층(34)이 위치하고 그 하부에 α-실리콘층(33)이 위치한 구조로 패터닝되어 있다.At this time, the anti-fuse part is patterned in a structure in which the TiW layer 34 is positioned on the upper layer and the α-silicon layer 33 is disposed on the lower layer.
이러한 앤티퓨즈부의 비어홀 저면에 위치한 배선층(31) 상부에 대응하는 TiW층을 노출시키는 포토레지스트패턴(도시안함)을 앤티-퓨즈부를 포함하는 배선절연층(32) 상에 형성한 다음, 포토레지스트패턴을 식각마스크로 이용하는 건식식각을 앤티-퓨즈부에 실시하여 비어홀에 의하여 노출되는 배선층(31)의 전부를 노출시킨다. 따라서, 배선층(31)과 앤티-퓨즈부는 서로 전기적으로 절단된다.A photoresist pattern (not shown) is formed on the wiring insulation layer 32 including the anti-fuse part to expose the TiW layer corresponding to the upper portion of the wiring layer 31 located on the bottom surface of the via hole. The dry etching using the etching mask is performed in the anti-fuse part to expose all of the wiring layer 31 exposed by the via hole. Thus, the wiring layer 31 and the anti-fuse part are electrically cut from each other.
이때, 식각제로는 Bl3와 SF6그리고 N2를 같이 사용하며, 유량은 각각 40, 25, 10 sccm으로 하고 공정압력은 저압으로 약 10-13mT로 유지하며 약 40W의 파워로 소정 시간(약 70초) 실시한다. SF6는 식각제이고 Bl3는 식각 프로파일 개선제이며, N2역시 식각 프로파일 개선제로 사용된다.At this time, Bl 3 , SF 6, and N 2 are used as the etchant, and the flow rates are 40, 25, and 10 sccm, respectively, and the process pressure is maintained at about 10-13 mT at low pressure and a predetermined time (about 70 seconds). SF 6 is an etchant, Bl 3 is an etch profile improver, and N 2 is also used as an etch profile improver.
식각 후 포토레지스트패턴을 제거한 기판의 단면도가 도시되어 있다.A cross-sectional view of the substrate with the photoresist pattern removed after etching is shown.
식각된 결과 앤티-퓨즈부의 상부구조인 TiW층(34)의 단면 프로파일(S)이 매끈한 형태를 갖게 된다. 이는, TiW층이 식각될 때 첨가된 질소에 의하여 식각측면에 폴리머가 증착되기 때문이다. 앤티-퓨즈부 식각시 질소의 양은 5-20 sccm으로 하지만, 만약 질소량이 너무 과도하면 식각장비에도 폴리머가 증착되어 이물질(particles) 등의 배기가 곤란해진다.As a result of etching, the cross-sectional profile S of the TiW layer 34, which is the upper structure of the anti-fuse part, has a smooth shape. This is because the polymer is deposited on the etching side by the added nitrogen when the TiW layer is etched. In the anti-fuse part, the amount of nitrogen is 5-20 sccm. However, if the amount of nitrogen is excessive, polymer is deposited on the etching equipment, which makes it difficult to exhaust particles and the like.
따라서, 본 발명은 식각가스를 SF6와 Bl3 및 N2를 사용하므로 식각 부위의 단면 프로필을 개선하여 소자의 신뢰성을 높이는 장점이 있다.Therefore, the present invention has the advantage of improving the reliability of the device by improving the cross-sectional profile of the etching portion because the etching gas using SF 6 and Bl3 and N 2 .
Claims (5)
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| KR1019990048483A KR20010045256A (en) | 1999-11-04 | 1999-11-04 | A method of improving an etch profile |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5527745A (en) * | 1991-03-20 | 1996-06-18 | Crosspoint Solutions, Inc. | Method of fabricating antifuses in an integrated circuit device and resulting structure |
| KR970052610A (en) * | 1995-12-29 | 1997-07-29 | 문정환 | Etching Method of Semiconductor Thin Film |
| KR20000069380A (en) * | 1997-10-13 | 2000-11-25 | 아끼구사 나오유끼 | Semiconductor device with fuse and fabricating method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5527745A (en) * | 1991-03-20 | 1996-06-18 | Crosspoint Solutions, Inc. | Method of fabricating antifuses in an integrated circuit device and resulting structure |
| KR970052610A (en) * | 1995-12-29 | 1997-07-29 | 문정환 | Etching Method of Semiconductor Thin Film |
| KR20000069380A (en) * | 1997-10-13 | 2000-11-25 | 아끼구사 나오유끼 | Semiconductor device with fuse and fabricating method thereof |
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