KR20010004202A - Device and method to control output data in semiconductor memory device - Google Patents

Abstract

PURPOSE: An apparatus for controlling data output of a semiconductor memory device is a pipe latch in put/output control apparatus which has a simple and a small area using a latch. CONSTITUTION: The pipe latch input/output control apparatus includes: the first control signal generation part generating the first control signal to activate a pipe latch input control signal in response to the first, the second and the third output enable signal activated in a read operation; a pipe latch input control part(630) generating the second control signal to control an input path of data transferred from a cell to a pipe latch in response to the first control signal and the first output enable signal; and a pipe latch output control part(650) generating the third control signal to control an output path from the pipe latch to an output driver in response to an output enable signal generated in response to the first control signal and the first output enable signal.

Description

Device and method to control output data in semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a next generation memory device (Double Data Rate) SDRAM (Synchronous DRAM), and more particularly, to a method and apparatus for controlling the output of data during a read operation of a DDR SDRAM.

As is well known, a synchronous DRAM (hereinafter referred to as SDRAM), which operates in synchronization with an external system clock, is widely used as a DRAM in semiconductor memory devices to improve operation speed. On the other hand, the conventional SDRAM is a device that inputs and outputs one data over a period of the clock in synchronization with the rising edge of the clock, while the DDR SDRAM is synchronized with the rising and falling edge of the clock. Two data can be input and output in succession. Therefore, even if the clock frequency is not increased, the operating speed can be at least twice as high as that of the conventional SDRAM. Meanwhile, in order to continuously output data, DDR SDRAM uses a method of temporarily storing data read from a cell in a plurality of pipe latches and then outputting the data.

Fig. 1 is a data output control block diagram of a DDR SDRAM, in which the command decoder 110 outputs the output control signals oe0, oe1, oe2 and outen by inputting a read command signal RD informing the start of a read operation, and the control. The pipe latch input / output controller 130 for outputting the pipe latch control enable signal pcd_en and the pipe count enable signal pcnt_en with the signals oe0, oe1, oe2, and outen as inputs, and the pipe latch control enable signal pcd_en as inputs. A pipe latch control signal generation unit 140 for generating a pipe latch control signal pcd, a pipe count control signal generation unit 150 for generating a pipe count signal pcnt by inputting the pipe count enable signal pcnt_en, and the pipe Pipe latch 160 for storing cell data in response to the latch control signal pcd and outputting the stored data in response to the pipe count signal pcnt. And an output driver 170 for outputting data output from the pipe latch 160 to the outside in response to the pipe count signal pcnt.

2 is a circuit diagram of a pipe latch input / output controller 130 according to the related art, and includes a pipe count enable signal generation unit 210 for outputting the pipe count enable signal pcnt_en in response to the output enable signal outen, and Pipe latch control enable signal generation unit for outputting pipe latch control enable signal pcd_en in response to the first, second and third output enable signals oe0, oe1 and oe2 and / pcnt_en inverting the pipe count enable signal. It consists of 250.

Specifically, the pipe count enable signal generation unit 210 receives an inverted signal of the output enable signal outen through an inverter INV21 to a first input terminal and the output enable signal outen to a second input terminal as a first delay element. 215) and the three-input NAND gate ND21 for inputting a signal having passed through the inverted latch 220 to the third input terminal and outputting the output signal of the inverted latch 220 to the second delay element 230 for a predetermined time. And inverters INV24 and INV25 that buffer them.

In addition, the pipe latch control enable signal generation unit 250 inputs the NOR gate NOR21 which inputs the signal delayed by the third delay element 255 from the first output enable signal oe0 and the second output enable signal oe1. And a NAND gate ND23 for inputting the output node signal N21 of the NOR gate NOR21 and the subpipe counter enable signal / pcnt_en, a signal delayed from the first output enable signal oe0, and a third output enable signal oe2. A two-clock detector 270 for outputting an output node N23, an output node N22 of the two-clock detector 270, an output node N23 of the NAND gate ND23, and a NAND gate ND25 for inputting the output node N23; Inverter INV26 outputs the pipe control enable signal pcd_en by inverting the output signal of the NAND gate ND25.

FIG. 2A is a schematic circuit diagram of the second clock detection unit 270. The output signal of the inverter INV27 inverting the delayed first output enable signal oe0 and the inverter INV28 inverting the third output enable signal oe2. And a three-input NAND gate ND27 for inputting an output signal and an output signal obtained by inverting (INV29) and delaying 275 the output signal of the inverter INV28.

Referring to the timing diagram of the read operation according to the prior art of FIG. 3, an operation having the above configuration, having a Cas Latency of 2 and a Burst Length of 2 will be described.

When the read command signal RD is applied, the command decoder 110 sequentially responds to the read command signal RD to sequentially output the first output enable signal oe0 and the second output enable signal oe1 and the third output enable as shown in FIG. 3. A signal oe2 is generated, and an output enable signal outen is generated in response to the second output enable signal oe1.

The signals oe0, oe1, oe2, and outen generated by the command decoder 110 are applied to the fibrous I / O control unit 130, and when the first output enable signal oe0 is activated as a logic “high”, a third delay element ( 255), the output node N21 of the NOR gate NOR21 is applied to the logic " low " and the logic " low " of the node N21 is applied to the NAND gate ND23 to make the output node N23 to the logic " high ".

Since the first output enable signal oe0 falls to a logic " low " by the inverter INV27, the output node N22 of the NAND gate ND27 becomes a logic " high " regardless of the second output enable signal oe2.

Therefore, the output signal of the NAND gate ND25 which takes in the node N22 and N23 becomes a logic "low" and is inverted by the inverter INV26 to enable the pipe latch control enable signal pcd_en to a logic "high".

Next, when the output enable signal outen activated by the second output enable signal oe1 is applied to the pipe count enable signal generation unit 210, the output enable signal outen is inverted by the inverter INV21 and is logic "low" to the NAND gate ND21. The output signal is logic " high " and the pipe count enable signal pcnt_en buffering it is enabled as logic " high ".

A read command RD is applied because Cas Latency is 2, and data starts to be output two clocks later. Since Burst Length is 2, the data is output within one clock. Therefore, the output of the pipe latch 160 is disabled three clocks after the read operation is started.

When the output enable signal outen applied to the pipe count enable signal generator 210 falls to a logic " low ", the signal inverted by the inverter INV21 and a predetermined delay in the first delay element 215 are applied. The output signal of the NAND gate ND21 that receives the signal inverted through the inverted and latched signals and the signal delayed by the second delay element 230 is delayed by the second delay element 230. At the moment it is applied to logic "high", it falls to logic "low", and in response, the pipe count enable signal pcnt_en is disabled to logic "low" to disconnect the pipelatch from the output driver.

As the pipe count enable signal pcnt_en falls to a logic " low, " the subpipe count enable signal / pcnt_en is applied to the NAND gate ND23 with a logic " high. &Quot; At this time, since the first output enable signal oe0 and the second output enable signal oe1 are both "low", the node N21 signal is a logic "high".

Thus, the node N23 signal drops to a logic " low ", and in response, the pipe latch control enable signal pcd_en is also disabled to a logic " low ".

A case in which the first read operation is started and the second read operation is started three clocks later will be described with reference to the timing diagram of the read operation when the cascade latency is 2.5 and the bus length is 2 in FIG.

Since the second clock detection unit 270 starts the second read operation before the pipe control enable signal pcd_en is activated in the first read operation and before the second clock detection unit 270 is disabled, the second clock detector 270 receives the data transmitted from the cell. While the pipe count signal pcnt_en is reset in the second reading operation, the pipe count signal pcnt_en exists to solve the case where the data is output in the order of the first, second, and first pipe latches.

A case in which the first read operation is started and the second read operation is started two clocks later will be described with reference to the timing diagram of the read operation when the cascade latency is 1.5 and the bus length is 2 in FIG. 5.

The second delay element 230 is disabled in response to the pipe count enable signal pcnt_en generated in response to the output enable signal outen after the first read operation is completed, and the second read operation is started and activated. The falling edge of the output enable signal outen is delayed through a delay so as not to fall to a logic " low "

However, the conventional pipe latch input and output unit is a complex and occupied area by adding circuits such as a two clock detector or a delay element to solve an error that may occur in performing a specific operation as described above. There is this.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a pipe latch input / output control device which occupies a simple and small area by using a latch.

1 is a data output control block diagram of a DDR SDRAM.

Figure 2 is a circuit diagram of a pipe latch input and output control unit according to the prior art.

FIG. 2A is a schematic circuit diagram of the two clock detector of FIG. 2; FIG.

3 is a timing diagram of a read operation according to the prior art;

4 is a timing diagram of a read operation when the cascade latency is 2.5 and the bus length is 2. FIG.

Fig. 5 is a timing diagram of a read operation when the cascade latency is 1.5 and the bus length is 2.

6 is a detailed circuit diagram of a pipe latch input / output control unit according to an embodiment of the present invention.

7 is a timing diagram of a read operation according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

130: pipe latch input and output control unit

630: pipe latch input control unit 650: pipe latch output control unit

The present invention for achieving the above object is a pipe latch input and output control apparatus, the first control signal for activating the pipe latch input control signal in response to the first, second and third output enable signal activated in the read operation; A first control signal generation unit generating a; A pipe latch input controller configured to generate a second control signal for controlling an input path of data transmitted from a cell to a pipe latch in response to the first control signal and the first output enable signal; And a pipe latch output controller configured to generate a third control signal for controlling an output path from the pipe latch to the output driver in response to the output enable signal generated in response to the first control signal and the first output enable signal. Characterized in that comprises a.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

6 is a detailed circuit diagram of a pipe latch input / output control unit of a DDR SDRAM according to an embodiment of the present invention.

As shown, a pipe latch input / output control signal for controlling data input / output to the pipe latch 160 via the NOR gate NOR61 and the inverter INV61 as inputs of the first, second, and third output enable signals oe0, oe1, and oe2. A pipe latch input / output control signal generation unit 610 for generating a pio_en, and a pipe latch input control unit for outputting a pipe latch control enable signal pcd_en in response to the pipe latch input / output control signal pio_en and the first output enable signal oe0 ( 630 and a pipe latch output control unit 650 for outputting the pipe count enable signal pcnt_en in response to the pipe latch input / output control signal pio_en and the output enable signal outen.

Specifically, the pipe latch input control unit 630 is the pipe latch input and output control signal pio_en is applied to the gate terminal of the inverter 631 consisting of a PMOS transistor PM61 and NMOS transistor NM61 and the ground power supply of the inverter 631 is a first The output enable signal oe0 is supplied through the source-drain path of the NMOS transistor NM62 which is applied to the gate. In addition, the output signal of the inverter outputs the pipe latch control enable signal pcd_en through inversion and storage by the first latch means 633.

The pipe latch output control unit 650 applies the pipe latch input / output control signal pio_en to the gate terminal of the inverter 651 consisting of a PMOS transistor PM62 and an NMOS transistor NM63, and the ground power of the inverter 651 is an output enable signal outen. Is supplied through the source-drain path of the NMOS transistor NM64. In addition, the output signal of the inverter outputs the pipe enable enable signal pcnt_en through inversion and storage by the second latch means 653.

An operation according to an embodiment of the present invention having the above configuration will be described with reference to the timing diagram of the output control unit of FIG.

When the read command signal RD is applied in the read operation of the DDR SDRAM, the first, second, and third output enable signals oe0, oe1, and oe2 generated by delaying the read command signal RD are 3 of the pipe latch input / output control signal generation unit 610. Input to NOR gate NOR61 and invert again to output pipe latch I / O control signal pio_en. That is, as the logical sum of oe0, oe1, and oe2, the pipe latch input / output control signal pio_en is activated as a logic " high " when only one of the oe0, oe1, and oe2 becomes a logic " high ".

When the pipe latch input / output control signal pio_en is activated with logic "high", it is applied to the pipe latch input control unit 630 and the pipe latch output control unit 650 to turn on the NMOS transistors NM61 and NM63. The output signal pipe latch control enable signal pcd_en of the pipe latch input controller 630 supplied with ground power by the NMOS transistor NM62 turned on by the first output enable signal oe0 is activated as a logic " high " The data passed from is stored as a pipelatch.

In addition, when the output enable signal outen is activated as logic "high" in response to the second output enable signal oe1 after a predetermined time, the NMOS transistor NM64 is turned on and turned on by the pipe latch input / output control signal pio_en. Through the NMOS transistor NM63, the pipe count enable signal pcnt_en is activated as logic "high" to output the data stored in the pipe latch to the outside through the output driver through the above process.

Even though the first output enable signal oe0 or the output enable signal outen is disabled as a logic " low " and the supply of ground power is cut off, the pipe latch control enable signal pcd_en and the The pipe count enable signal pcnt_en remains logic "high."

When the first, second, and third output enable signals oe0, oe1, and oe2 are all logic "low", the pipe latch input / output control signal pio_en is disabled as a logic "low" to turn on the PMOS transistors PM61 and PM62. By turning on, the pipe latch control enable signal pcd_en and the pipe count enable signal pcnt_en that are output by the latch are all disabled by logic "low", so that data input to the pipe latch and data transfer to the output driver are read. Complete the action.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above can reduce the chip size by simply configuring the pipe latch input / output control unit using a latch.

Claims (6)

In the pipe latch I / O control device, A first control signal generator configured to generate a first control signal for activating the pipe latch input control signal in response to the first, second and third output enable signals activated in the read operation; A pipe latch input controller configured to generate a second control signal for controlling an input path of data transmitted from a cell to a pipe latch in response to the first control signal and the first output enable signal; And Pipe latch output control unit for generating a third control signal for controlling the output path from the pipe latch to the output driver in response to the output enable signal generated in response to the first control signal and the first output enable signal. Pipe latch input and output control device comprising a. The method of claim 1, The first control signal generation unit A NOR gate configured to receive the first, second and third output enable signals; And And an inverter outputting the first control signal by inverting the output signal of the NOR gate. The method of claim 2, The pipe latch input control unit, A first inverter for inverting the first control signal; An NMOS transistor receiving the first output enable signal through a gate terminal and supplying a ground voltage of the first inverter through a source-drain path; And Latch means for inverting and latching an output signal of the first inverter to output the second control signal Pipe latch input and output control apparatus comprising a. The method of claim 3, The latch means, A second inverter outputting the second control signal by inverting the output signal of the first inverter; And A third inverter that inverts the output signal of the second inverter and feeds it back to the input terminal of the second inverter Pipe latch input and output control apparatus comprising a. The method of claim 2, The pipe latch output control unit, A first inverter for inverting the first control signal; An NMOS transistor receiving the output enable signal at a gate terminal to supply a ground voltage of the first inverter through a source-drain path; And Latch means for inverting and latching an output signal of the first inverter to output the third control signal Pipe latch input and output control apparatus comprising a. The method of claim 5, The latch means, A second inverter outputting a third control signal by inverting the output signal of the first inverter; And A third inverter that inverts the output signal of the second inverter and feeds it back to the input terminal of the second inverter Pipe latch input and output control apparatus comprising a.