KR20040090842A - Semiconductor memory device with selecting clock enable time - Google Patents

Abstract

PURPOSE: A semiconductor memory device selecting a clock enabling time is provided to perform a stable command and to assure a setup time and a hold time of a command signal stably under a high speed operation environment. CONSTITUTION: The semiconductor memory device comprises a delay latency generator(41), a CES setup circuit(45) and drivers(43,47). Signals(MS4 - MS6) applied to the delay latency generator are provided by an extended mode register set(EMRS) process. The delay latency generator generates delay latency signals(DL1¯DL3) in response to the EMRS signals. The delay latency signals are applied to the driver(43) and the CES setup circuit. The driver(43) controls a transfer path of a signal(TCS), and the CES setup circuit generates an enable selection information signal(CES) in response to the delay latency signals. The driver(47) generates a signal(TCES) in response to the enable select information signal.

Description

Semiconductor memory device that selects clock activation point {SEMICONDUCTOR MEMORY DEVICE WITH SELECTING CLOCK ENABLE TIME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a technology for adjusting the timing of generation of control signals in a DRAM.

When a semiconductor memory device such as a DRAM operates at a lower frequency, for example, 100 MHz or less, a set of inputs to a command for performing the operation of the DRAM when the clock cycle time (TCC) determining the operating range is 10 ns is set. Easy to set up and hold time. In other words, since the set-up and hold time of the command is about 2ns and 1ns in the state that the time required for the rising edge of the clock is 5ns, the DRAM can operate stably according to the input commands. have.

However, in an environment operating in the high frequency region of at least 100 MHz, the cycle time of the clock is further shortened, making it difficult to stably set and hold time of commands within the range of the rising edge of the clock. When it becomes difficult to ensure stable activation of commands (chip selection signal, clock enable signal, etc.) or control signals (low address strobe signal, column address strobe signal, etc.) for determining the operation of the DRAM under a high speed operating environment, malfunction Or problems such as deterioration of operation reliability may occur.

1 illustrates data input / output timing in a post CAS mode used in a current DRAM.

In post cascade mode, an additive latency (AL) scheme is used to efficiently use the command bus and data bus. According to the additional latency scheme, the next command that is subsequently input after one command CMD is input is immediately input without a separate delay. At this time, the data is output after a delay time equal to the TRCD margin, which is an AC variable necessary in the data input / output process, and the additional latency value AL and the cascade latency value CL corresponding to the input command.

The cascade latency value CL is set during the mode register set (MRS) process using the address pin, and the data matches the cascade latency value CL set according to the read and write commands received after the MRS is set. Is output.

2 shows a control scheme of buffers used in dual data rate (DDR) synchronous DRAM.

The buffer 10 generates the clock master signal PCK in response to the clock signal CK. One buffer 10, 20 buffers the output control clock CKDQ in response to the clock signal CK. The synchronization delay loop 30 allows the data output to be synchronized in response to the clock master signal PCK without distorting the output control clock CKDQ. The buffer 40 generates the chip select master signal PCS in response to the chip select signal CSB. The buffer 50 receives the column address strobe signal CASB to generate signals PCF, PC, and PCA for controlling the column chain. The buffer 60 inputs the address ADDi to generate the column address CAi. The buffer 70 generates signals PDQMA and PDQMF for controlling data output masking in response to the data output masking signal DQM. The buffer 80 inputs the write activation signal WEB to generate signals PWR and PWRCF for controlling data writing. Buffer 80 enters the input data DIN.

The buffers shown in FIG. 2 are activated by the master clock signal PCK generated at the rising edge of the clock signal CK from the clock signal buffer 10 to provide command or control signals (CSB, CASB, ADDi, DQM, WEB) provided from the outside of the chip. , Etc.) is converted into the CMOS level and provided inside the chip. On the other hand, the cascade latency signals CLi (i = 1, 2, 3, 4) are applied to the output control clock buffer 20 and the data output masking buffer 70 to control the timing of the data output.

Here, referring to FIG. 3, which illustrates the generation process of the chip select master signal PCS in response to the chip select signal CSB, which is one of the externally applied commands, the chip select master signal PCS includes the rising edge of the clock signal CK and the chip select signal. In response to the falling edge of the CSB, it is activated by a high level pulse.

As shown in FIG. 3, in the process of generating the chip select master signal PCS, the input of the external command chip select signal CSB must be completed within one clock cycle. This method can be a time burden in a high speed operating environment in which the operating frequency is gradually increased. In addition, since the chip select master signal PCS is generated only while the chip select signal CSB is activated only for a time corresponding to one clock, there is a limitation that the user can not select the time when the PCS occurs.

Meanwhile, referring to FIG. 4, in order to perform read and precharge operations on the DRAM, the chip select signal CSB should be made twice. At this time, it is important to ensure the time margin of the set and hold time in the clock 2 or 4 where the control on the chip select signal CSB and the corresponding command (read or precharge) are executed.

In addition, since not only the chip select signal but also other types of commands operate according to the clock signal cycle, it is increasingly difficult to secure time margins for set-up and hold time in a high-speed operating environment with a high operating frequency of the clock signal. Will lose.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of performing a stable command in a high speed operating environment.

Another object of the present invention is to provide a semiconductor memory device capable of stably securing set and hold time of a command signal in a high speed operating environment.

In order to achieve the above object of the present invention, the present invention is a semiconductor memory device for performing internal operations in response to a clock signal provided from the outside: a command provided from the outside in synchronization with the clock signal; A buffer provided inside the device; First means for generating a plurality of latency signals for setting a delay time based on a cycle period of the clock signal; And second means for selecting an activation time point of the command in response to the latency signals.

The first means generates the latency signals in response to input signals provided from a predetermined setting mode. The second means includes circuitry for generating an information signal relating to an activation time of the command in response to the latency signals; And a circuit for determining an activation time of the command in response to the latency signals and the information signal.

In the second means, the circuit for determining the activation time of the command selects the activation time of the command in response to the information signal when the output in response to the latency signals is a predetermined state, and the activation time of the command Is determined according to any one of the latency signals.

1 is a timing diagram showing an example of a data input / output method in a DRAM.

2 is a block diagram illustrating a control system of buffers used in a DRAM.

3 is a timing diagram showing generation of a chip select signal according to a conventional scheme.

4 is a timing diagram illustrating an operation of a chip select signal for performing read and precharge operations according to a conventional method.

5 is a block diagram illustrating a control system of buffers used in DRAM according to the present invention.

6 is a circuit diagram for generating latency signals in accordance with the present invention.

7 is a circuit diagram for generating a clock enable signal in accordance with the present invention.

8 is a circuit diagram illustrating an embodiment in which the present invention is applied to a chip select signal.

9 is a circuit diagram showing an embodiment in which the present invention is applied to a chip select signal.

10 is a timing diagram illustrating generation of a chip select signal according to an embodiment of the present invention.

11 is a timing diagram illustrating an operation of a chip select signal for performing read and precharge operations according to the present invention.

In the drawings according to the present invention, the same reference numerals are used for components having substantially the same configuration and function.

The present invention can be applied to a semiconductor memory device which operates in synchronization with a high frequency clock signal (at least 100 MHz).

Embodiments according to the present invention can be applied to semiconductor memory devices that use commands to perform internal operations of a chip in synchronization with a high frequency clock signal.

In the description of the embodiment of the present invention, the term “command” refers to control signals received from the outside of the semiconductor memory device chip to instruct and perform execution of related operations by activating functional circuits inside the device. . In addition, the term "external signals" will be used as a general term for an address or data received from the outside of the chip including the command.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 shows, as an overall configuration, a state in which an embodiment of the present invention is applied to buffers for receiving commands or external signals used in a DRAM according to the present invention.

In FIG. 5, commands (CSB, CASB, DQM, WEB, etc.), input data DIN and address ADDI, which are external signals applied from the outside of the chip of the DRAM, are received and provided to the chip. Information for determining the activation point of the output signal (hereinafter, "activation selection information" or "CES information") is provided, respectively. Herein, an operation state in which the activation selection information is provided to the buffer is referred to as "CES mode (Clock Enable time Selecton mode)".

The chip select buffer 40, which receives the chip select signal CSB and generates the chip select master signal PCS, is provided with a chip select activation selection information ICES _CS for selecting an activation time of the chip select master signal PCS.

In addition, the cas buffer 50, which receives the cas address (CAS) column CAS signal and generates the cas master signal PC, is provided with casing activation selection information ICES _CAS for selecting an activation time of the _cas master signal PC. The address buffer 60 is provided with column address activation selection information ICES _CA for selecting the occurrence point of the column address CAi. Data input and output buffer 70 is provided with a masking data mask _DQM ICES active selection information for selecting an activation time of the master signal and PDQMA PDQMF the data output masking signal DQM. The output activation buffer 80 is provided with output activation selection information ICES _WE for selecting the activation time of the master signal PWR of the output activation signal WEB. The data input buffer 90 is provided with the data input activation selection information ICES _DI for controlling the input time of the input data.

The activation selection information ICES _CS to IICE _DI , which selects the master signals of the commands and the time of activation of the input data and the input address, correspond to each signal having sufficient set and hold time for the cycle period of the clock signal CK. This function controls the buffers.

6 shows the overall configuration of circuits for providing the chip select activation selection information ICES _CS for controlling the chip select master signal PCS activation time, taking the case of the chip select signal as an example.

Referring to FIG. 6, a circuit configuration for providing the chip select activation selection information ICESCS includes a delay latency (DL) generator 41, a CES set circuit 45, and drivers 43 and 47. The signals MS4 to MS6 applied to the delay latency generator 41 are signals provided by an extended mode register set (EMRS) process. EMRS is for setting the CES mode used in the embodiment of the present invention, provided separately from the above-described MRS, but is set in the same manner as the existing MRS. The delay latency generator 41 generates delay latency signals DL1 to DL3 in response to the EMRS signals MS4 to MS6. The delay latency signals DL1 to DL3 enable the corresponding command or control signals to be activated after the delay time corresponding to the number of clocks set.

Delay latency signals DL1 to DL3 are applied to driver 43 and CES set circuit 45. The driver 43 controls the transmission path of the signal TCS informing the generation of the chip select master signal PCS in response to the delay latency signals DL1 to DL3. The CES set circuit 45 generates the activation selection information signal CES in response to the delay latency signals DL1 to DL3. The driver 47 generates the signal TCES in response to the activation selection information signal CES generated from the set circuit 45.

Signals informing the generation of the chip selection master signal PCS TCS and TCES are signals for the generation of the chip selection master signal PCS, which perform the same functions as each other, but the TCS is generated in the operating state where the CES information is not reflected. On the other hand, TCSES is generated in CES mode in which CES information is reflected. Therefore, one of the two will be selectively generated depending on whether the CES mode is applied.

FIG. 7 shows the circuit configuration of the delay latency generator 41 shown in FIG. Referring to FIG. 7, the EMRS signal MS6 is input to the NAND gates ND1 to ND3 through the inverter INV1. The EMRS signal MS5 is directly input to the NAND gates ND1 and ND2 and is input to the NAND gate ND3 through the inverter INV3. The EMRS signal MS4 is directly input to the NAND gates ND1 and ND3 and is input to the NAND gate ND2 through the inverter INV2.

The output of the NAND gate ND1 is generated as the redundancy signal DL3 through the inverters INV10 and INV11 connected in series after passing through the inverter INV4 and the transmission gate TG1. The output of the NAND gate ND2 is generated as the redundancy signal DL2 through the inverters INV12 and INV13 connected in series after passing through the inverter INV5 and the transmission gate TG2. The output of the NAND gate ND3 is generated as the redundancy signal DL1 through the inverters INV14 and INV15 connected through the inverter INV6 and the transmission gate TG3 and connected in series. The transfer gates TG1 to TG3 are CMOS gates and are turned on when the control signal PSF is at a high level.

Delay latency signals DL1 to DL3 generated from the delay latency generator 41 of FIG. 7 represent the number of delayed clock cycles. That is, DL1, DL2, and DL3 mean delay times of one, two, and three clock cycles, respectively. In FIG. 7, only three delay latency signals are generated. It should be understood that the circuit can be changed for the latency value 1.5 or 2.5 used in the dual data rate (DDR) DRAM.

FIG. 8 shows a detailed circuit of the CES set circuit 45 shown in FIG. In Fig. 8, the delay latency signal DL3 is input to the NAND gate ND11. The other input of the NAND gate ND11 is fixed to the supply voltage. The output of the NAND gate ND11 is input to the NAND gate ND21 through an inverter chain IC1 composed of an even number of inverters connected in series. The other input of the NAND gate ND21 is connected to the output of the NAND gate ND13 in response to the delay latency signal DL2. The output of the NAND gate ND12 is input to the NAND gate ND14 through an inverter chain IC2 composed of an odd number of series-connected inverters and a transmission gate TG12. The other input of the NAND gate ND14 is fixed to the supply voltage. The output of the NAND gate ND14 is the activation selection information signal CES. The delay latency signal DL1 is input to the NAND gate ND14 through the inverter INV21 and the transmission gate TG11.

The transmission gate TG11 is turned on when the delay latency signal D1 is activated to a high level so that the delay latency signal DL1 determines the activation selection information signal CES that is an output of the NAND gate ND14. The transmission gate TG12 is turned on when the delay latency signal DL1 is at a low level so that the activation selection information signal CES is determined in response to another delay latency signal DL2 or DL3.

9 and 10 show circuits for generating signals TCS and TCES as drivers shown in FIG. 6, respectively.

When the above-described CES mode by the EMRS is applied, TCES is used as a signal indicating the generation of the chip select master signal PCS. In the CES mode, one of the delay latency signals DL1 to DL3 is activated at a high level, and thus the activation selection information signal CES is activated at a high level.

Referring to FIG. 9, a typical signal generation path of the signal TCS indicating the generation of the chip select signal PCS simply follows the serial connection of the inverters INV21 to INV23. However, in the present invention, the transmission gates TG21 and TG22 are interposed between the inverters INV21 and INV22 and between the inverters INV22 and INV23, respectively, so that the transmission gates TG21 and TG22 respond to the states of the delay latency signals DL1 to DL3. Design. That is, when the output of the NOA gate NR1 for inputting the delay latency signals DL1 to DL3 is low, that is, in the CES mode, the transmission gates TG21 and TG22 are turned off so that the signal TCS responds to the state of the chip select master signal PCS. Do not do it. In contrast, when the output of the NOA gate NR1 is at a high level, the signal path is opened and the signal TCS is effectively generated.

Meanwhile, referring to FIG. 10 showing the driver 47 of FIG. 6, the selection information signal CES, which is activated at a high level when one of the delay latency signals DL1 to DL3 is activated, is input to the noah gate NR2. The other input of NOR gate NR2 is connected to ground voltage. The output of NORGATE NR2 is generated with signal TCES through serially connected inverters INV31 and INV32.

When delay latency information by the delay latency signals DL1 to DL3 exists, it can be seen that the signal TCES in response to the activation selection information signal CES is activated instead of the generation path of the signal TCS. That is, the signal TCES may be regarded as a TCS signal in the CES mode.

11 shows the generation timing of the chip select master signal PCS when the present invention is applied to the chip select signal CSB. As shown in Fig. 11, it is seen that the chip select master signal PCS is activated four times in synchronization with the rising edge of the clock signal CK while the chip select signal CSB is activated at a low level over four cycles of the clock signal CK. Can be.

As in the conventional case (Fig. 3) described above, there is no restriction that the input of the chip select signal CSB must be completed within one period of the clock signal CK, and the user selects the chip select master signal PCS according to the delay latency value in the CES mode. It is possible to select the activation time of. That is, in the first period 1 of the clock signal CK, the delay latency signal DL1 is selected so that the chip select master signal PCS is activated with a high level pulse at the same time as in the conventional case. In addition, the delay latency signals DL2, DL3 and DL4 The chip select master signal PCS is activated respectively in the second, third and fourth periods of the clock signal CK as are selectively activated.

As the unilateral limitation on the activation time of the chip select signal CSB is removed (the user can selectively determine the activation time), as shown in FIG. 12, read and precharge operations are performed. In order to do this, as shown in FIG. 4, the chip select signal CSB does not need to be independently activated twice in time constraints, and it is only necessary to maintain the low level activation state for four cycles of the clock signal CK. That is, Read operates according to DL1 and Precharge operates according to DL3. Then, the set and hold time margins for each operation command can be guaranteed by one clock. Therefore, even if the clock signal CK becomes short due to an increase in the frequency of the clock signal CK, the operation according to the command can be performed after the delayed clock, thereby overcoming the time limitation due to the high speed operation.

6 to 12 described above, the present invention has been applied only to the chip select signal. However, the present invention provides other types of commands or control signals driven in synchronization with a clock signal, that is, address strobe signals RASB and CASB. ) May be applied to signals indicating activation of a clock signal (eg, CKE), or signals (eg, WEB and DQM) that control data reading and writing and data input / output.

In addition, the present invention may be applied to a semiconductor integrated circuit device in which commands or control signals are input in synchronization with a clock signal as well as a DRAM.

Those skilled in the art according to the means or method of the present invention shown in the above-described embodiments are capable of modification and application of the present invention within the scope of the present invention.

According to the embodiment of the present invention described above, the present invention has the advantage of ensuring a stable setup and hold time margin of a command in a high speed operating environment in which the clock frequency is increased.

Claims (10)

A semiconductor memory device which performs internal operations in response to a clock signal provided from the outside: A buffer for providing a command provided from the outside to the semiconductor device in synchronization with the clock signal; First means for generating a plurality of latency signals for setting a delay time based on a cycle period of the clock signal; And And second means for selecting an activation time point of the command in response to the latency signals. The method of claim 1, And the first means generates the latency signals in response to input signals provided from a predetermined setting mode. The method of claim 1, The second means, A circuit for generating an information signal relating to an activation time of the command in response to the latency signals; And And a circuit for determining an activation time of the command in response to the latency signals and the information signal. The method of claim 3, And a circuit for determining an activation time of the command selects an activation time of the command in response to the information signal when an output in response to the latency signals is in a predetermined state. The method of claim 4, wherein And an activation time point of the command is determined according to any one of the latency signals. A semiconductor memory device which performs internal operations in response to a clock signal provided from the outside: A plurality of buffers respectively providing a plurality of commands provided from the outside in synchronization with the clock signal to the inside of the semiconductor device; Means for generating a plurality of latency signals for setting a delay time based on a cycle period of the clock signal; And And a plurality of information circuits for determining an activation time point of the commands in response to the latency signals. The method of claim 6, And said means generates said latency signals in response to input signals provided from a predetermined setting mode. The method of claim 1, Each of the information circuits, A circuit for generating an information signal relating to an activation time of the command in response to the latency signals; And And a circuit for determining an activation time of the command in response to the latency signals and the information signal. The method of claim 8, And a circuit for determining an activation time of the command selects an activation time of the command in response to the information signal when an output in response to the latency signals is in a predetermined state. The method of claim 8, And an activation time point of the command is determined according to any one of the latency signals.