KR20000073715A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20000073715A KR20000073715A KR1019990017168A KR19990017168A KR20000073715A KR 20000073715 A KR20000073715 A KR 20000073715A KR 1019990017168 A KR1019990017168 A KR 1019990017168A KR 19990017168 A KR19990017168 A KR 19990017168A KR 20000073715 A KR20000073715 A KR 20000073715A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 150000002500 ions Chemical class 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 230000002093 peripheral effect Effects 0.000 abstract description 9
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 description 10
- 229910008486 TiSix Inorganic materials 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 101000892301 Phomopsis amygdali Geranylgeranyl diphosphate synthase Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 더 구체적으로는 DC 콘택 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a DC contact.
반도체 메모리 장치에서, 전극은 폴리실리콘막과 금속 실리사이드막(metal silicide layer)을 함께 사용하는 폴리사이드(polycide) 구조가 사용된다.In the semiconductor memory device, a polycide structure using a polysilicon film and a metal silicide layer together is used.
COB(capacitor over bit line) 구조를 갖는 디램(danamic random access memory)에 있어서, 비트라인 형성 물질로 폴리사이드가 사용되고 있다. 최근들어, 메모리의 고속 동작을 위해 내화 금속물질인 텅스텐(tungsten : W)이 비트라인으로 사용되고있다. 그러나, 금속 비트 라인은 800℃ 이상의 고온 공정이 진행될때, 도 1에서 보여지는 바와 같이 콘택홀 형성후, Ti(14) 및 텅스텐(16)이 차례로 증착되어 800℃이상으로 공정이 진행되면 기판(10)의 P+ 도핑 영역(12)과 Ti(14)의 접촉부분에서 TiSix(A)가 형성된다. 이때, P+ 도핑영역(12)의 B이 상기 TiSix(A)와 결합하여 콘택 저항을 증가시킨다. 상기 콘택 저항의 증가는 칩 사이즈가 감소할수록 더욱 심각해진다.In DRAMs having a capacitor over bit line (COB) structure, polysides are used as bit line forming materials. Recently, tungsten (W), a refractory metal material, has been used as a bit line for high speed operation of a memory. However, when the metal bit line is subjected to a high temperature process of 800 ° C. or more, as shown in FIG. 1, after formation of the contact hole, Ti 14 and tungsten 16 are sequentially deposited to process the substrate at 800 ° C. or more. TiSix (A) is formed at the contact portion of the P + doped region 12 and Ti 14 in 10). At this time, B of the P + doped region 12 is combined with the TiSix (A) to increase the contact resistance. The increase in contact resistance becomes more severe as the chip size decreases.
도 2a를 참조하면, 폴리사이드 비트라인(polycide bit line)을 형성할 경우, 기판(1)의 불순물 영역과 비트라인(5)을 연결하는 DC(4)가 도전물질(3)로 채워져 콘택 플러그가 형성된다. 일반적으로 COB 디램에서는 N+ 영역에만 DC가 형성되고 P+영역에는 DC가 형성되지 않는다. 대신, P+ 영역은 후속 금속 콘택 공정에서 금속 브리지(6)를 통해 연결되므로 단차가 커지게 된다.Referring to FIG. 2A, when a polycide bit line is formed, a contact plug is filled with a conductive material 3 filled with a DC 4 connecting the impurity region of the substrate 1 and the bit line 5. Is formed. In general, in a COB DRAM, DC is formed only in the N + region, and DC is not formed in the P + region. Instead, the P + region is connected through the metal bridge 6 in a subsequent metal contact process, resulting in a large step.
다음 도 2b를 참조하면, P+ 및 N+ 영역(7, 8)에 대해 DC용 콘택 플러그(9, 10)가 형성된다. 상기 콘택 플러그(9, 10)는 불순물 영역에 따라 N+ 및 P+형 불순물 이온이 주입된다. 그러나, N+ 영역(8)에 대한 콘택 플러그(10)에 N+형 불순물 이온이 주입된후 P+형 불순물이 주입되면 P+형 불순물 이온의 Rp(projected range 로 인해 게이트 전극(2)을 이루는 N 형 폴리실리콘막(2a)의 이온이 상쇄되어 드레솔드 전압이 변화하게 된다. 상기 이온 상쇄는 게이트 전극(2)의 폴리실리콘막(2a)으로 N+ 불순물 이온이 주입된 도전막이 사용되기 때문이다. 상기 이온 상쇄를 줄이기 위해 P+형 불순물 이온의 주입시 에너지를 줄이게 되면 콘택 저항이 증가되는 문제점이 발생하게 된다.Referring next to FIG. 2B, contact plugs 9 and 10 for DC are formed for the P + and N + regions 7 and 8. The contact plugs 9 and 10 are implanted with N + and P + type impurity ions according to impurity regions. However, when N + type impurity ions are implanted into the contact plug 10 for the N + region 8 and then P + type impurities are implanted, the N type poly forming the gate electrode 2 due to the projected range of P + type impurity ions The ions of the silicon film 2a are canceled to change the dress voltage, since the ion canceling is performed by using a conductive film in which N + impurity ions are injected into the polysilicon film 2a of the gate electrode 2. If the energy is reduced during the implantation of the P + type impurity ions to reduce the offset, a problem arises in that the contact resistance is increased.
따라서, 본 발명의 목적은 상술한 제반 문제점을 해결하기 위해 제안된 것으로, 셀 영역과 주변 영역의 각기 다른 불순물 영역에 DC를 동시에 형성하므로서 공정을 단순화하고 단차를 줄일 수 있는 반도체 장치의 제조 방법을 제공하는데 있다.Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a method of manufacturing a semiconductor device which can simplify the process and reduce the step by simultaneously forming DC in different impurity regions of the cell region and the peripheral region. To provide.
도 1a 및 도 1b는 종래의 금속 비트라인과의 기판과의 콘택 형성시 문제를 보여주는 도면;1A and 1B illustrate problems in forming contact with a substrate with a conventional metal bitline;
도 2a는 종래 기술에 따른 DC 콘택이 형성된 반도체 장치의 단면도;2A is a cross-sectional view of a semiconductor device with a DC contact according to the prior art;
도 2b는 종래 기술에 따른 불순물 이온이 주입되는 DC 콘택을 보여주는 단면도;2B is a cross-sectional view showing a DC contact into which impurity ions are implanted according to the prior art;
도 3a 내지 도 3f는 본 발명에 따른 반도체 장치의 제조 방법의 공정들을 순차적으로 보여주는 흐름도 및;3A to 3F are flow charts sequentially showing processes of a method of manufacturing a semiconductor device according to the present invention;
도 4는 본 발명에 따른 콘택을 보여주는 반도체 장치의 단면도이다.4 is a cross-sectional view of a semiconductor device showing a contact according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1, 20 : 기판 2, 28 : 게이트 전극1, 20: substrate 2, 28: gate electrode
7, 8, 34, 34' : 소오스/드레인 9, 10, 40n, 40p : 콘택 플러그7, 8, 34, 34 ': source / drain 9, 10, 40n, 40p: contact plug
32 : SEG 44 : 비트 라인32: SEG 44: Bit Line
상술한 바와 같은 본 발명의 목적을 달성하기 위한 본 발명의 특징에 의하면, 반도체 장치의 제조 방법은 셀 영역과 주변 영역으로 정의된 반도체 기판상에 폴리실리콘막, 금속-실리사이드막 및 제 1 절연막의 다층막으로 이루어진 게이트 전극을 형성한다. 상기 비활성 영역 및 게이트 전극을 제외한 상기 기판의 활성 영역상에 상기 폴리실리콘막 두께의 0.5배 이상 그리고 상기 게이트 전극 높이보다 낮은 두께를 갖도록 SEG(selective epitaxial growth)막을 형성한다. 상기 기판에 소오스/드레인 형성을 위해 이온 주입한다. 상기 기판 전면에 제 2 절연막을 형성한다. 상기 소오스/드레인을 위한 콘택홀을 형성한다. 상기 콘택홀을 채우면서 상기 산화막상에 제 2 도전막을 형성한다. 적어도 상기 산화막의 상부 표면이 노출될때까지 상기 제 2 도전막을 평탄화 식각하여 콘택 플러그를 형성한다. 상기 콘택 플러그에 각각 N형, P형 불순물 이온을 주입한다. 그리고 상기 기판 전면에 금속 비트라인을 증착한다.According to a feature of the present invention for achieving the object of the present invention as described above, a method of manufacturing a semiconductor device is a method of manufacturing a polysilicon film, a metal-silicide film and a first insulating film on a semiconductor substrate defined by a cell region and a peripheral region A gate electrode made of a multilayer film is formed. A selective epitaxial growth (SEG) film is formed on the active region of the substrate excluding the inactive region and the gate electrode to have a thickness of at least 0.5 times the thickness of the polysilicon layer and a thickness lower than the gate electrode height. The substrate is ion implanted for source / drain formation. A second insulating film is formed on the entire surface of the substrate. A contact hole for the source / drain is formed. A second conductive film is formed on the oxide film while filling the contact hole. The second conductive layer is planarized and etched to form a contact plug until at least the upper surface of the oxide layer is exposed. N-type and P-type impurity ions are respectively injected into the contact plugs. The metal bit line is deposited on the entire surface of the substrate.
바람직한 실시예에 있어서, 상기 콘택 플러그 형성 단계후 산화막 상부 표면보다 낮은 높이를 갖도록 에치백을 더 수행하는 단계를 포함한다.In an exemplary embodiment, the method may further include performing etch back to have a lower height than the oxide upper surface after the contact plug forming step.
(실시예)(Example)
이하 본 발명에 따른 실시예를 첨부된 도면 도 3 및 도 4를 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 and 4.
본 발명의 신규한 반도체 장치의 제조 방법은 기판의 활성 영역상에 SEG막을 형성한후 DC를 형성한다. 그러므로 NMOS 및 PMOS 트랜지스터의 불순물 영역 및 게이트 폴리실리콘막에 불순물이 주입되더라도 P+와 N+ 이온의 상쇄를 막을 수 있다.The novel semiconductor device manufacturing method of the present invention forms a SEG film on an active region of a substrate and then forms a DC. Therefore, even if impurities are injected into the impurity regions of the NMOS and PMOS transistors and the gate polysilicon film, the offset of P + and N + ions can be prevented.
도 3a 내지 도 3f는 본 발명에 따른 반도체 장치의 제조 방법의 공정들을 순차적으로 보여주는 흐름도이다.3A to 3F are flowcharts sequentially showing processes of a method of manufacturing a semiconductor device according to the present invention.
도 3a를 참조하면, 본 발명의 실시예에 따른 반도체 메모리 장치의 제조 방법은 먼저, 셀 어레이 영역(cell array region)과 주변회로 영역(periphery region)을 갖는 반도체 기판(20) 상에 활성 영역(active region)과 비활성 영역(inactive region)을 정의하기 위해 소자격리막이 형성된다.Referring to FIG. 3A, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention may first include an active region on a semiconductor substrate 20 having a cell array region and a peripheral region. An isolation layer is formed to define an active region and an inactive region.
상기 셀 어레이 영역과 주변회로 영역에 각각의 게이트 전극층(28) 즉, 워드 라인(wordline)이 형성된다. 상기 게이트 전극층(28)은 예를 들어, 폴리실리콘막(22), 티타늄 실리사이드막(TiSix)(24), 그리고 게이트 마스크막인 실리콘 질화막(26)이 차례로 적층된 후, 패터닝(patterning)되어 형성된다. 상기 폴리실리콘막(22)에 N형 불순물 이온이 도핑된다. 상기 티타늄 실리사이드막 대신 텅스텐 실리사이드막(WSix)이 사용될 수 있다.Each gate electrode layer 28, that is, a wordline, is formed in the cell array region and the peripheral circuit region. The gate electrode layer 28 is formed by, for example, laminating a polysilicon layer 22, a titanium silicide layer (TiSix) 24, and a silicon nitride layer 26, which is a gate mask layer, in turn. do. N-type impurity ions are doped into the polysilicon film 22. A tungsten silicide film WSix may be used instead of the titanium silicide film.
상기 게이트 전극층(28)을 포함하여 반도체 기판 전면에 게이트 스페이서용 절연막이 증착 된다. 상기 절연막이 에치 백(etch back) 공정으로 식각되어 셀 어레이 영역 및 주변회로 영역의 각각에 게이트 스페이서(30)가 형성된다. 상기 게이트 스페이서(30)는 실리콘 산화막으로도 형성할 수 있다.An insulating film for a gate spacer is deposited on the entire surface of the semiconductor substrate including the gate electrode layer 28. The insulating layer is etched by an etch back process to form a gate spacer 30 in each of the cell array region and the peripheral circuit region. The gate spacer 30 may also be formed of a silicon oxide film.
도 3b를 참조하면, 상기 게이트 전극층을 제외한 기판의 활성 영역에 즉, 후속 소오스/드레인이 형성될 영역에 SEG(selective epitaxial growth)막(32)이 형성된다. 상기 SEG막(32)은 상기 게이트 전극층(28)의 폴리실리콘막(22) 절반의 두께보다 두껍고 전체 게이트 전극층보다는 얇은 두께 범위()로 형성된다. 상기 SEG막(32)은 후속 N+형 및 P+형 영역(34, 34')에 대한 콘택 플러그의 불순물 이온 주입 공정시 에너지를 낮출수 있어 불순물이 게이트 폴리실리콘막의 N+ 도핑 및 NMOS 및 PMOS 채널 영역에 영향을 미치지 않게 된다.Referring to FIG. 3B, a selective epitaxial growth (SEG) film 32 is formed in an active region of the substrate excluding the gate electrode layer, that is, in a region where a subsequent source / drain is to be formed. The SEG film 32 is thicker than the thickness of half of the polysilicon film 22 of the gate electrode layer 28 and thinner than the entire gate electrode layer. Is formed. The SEG film 32 can lower the energy during the impurity ion implantation process of the contact plugs for the subsequent N + type and P + type regions 34 and 34 ', so that impurities can be added to the N + doping and NMOS and PMOS channel regions of the gate polysilicon layer. It will not affect.
다음, 상기 반도체 기판(20) 전면에 포토레지스트 패턴을 마스크로 사용하여 NMOS 및 PMOS 영역 각각에 불순물 이온이 주입된다. 그러면, 셀 어레이 영역 및 주변회로 영역의 게이트 스페이서(30) 양측의 활성 영역 내에 소오스/드레인 영역(34, 34')이 형성된다. 도 3c에서는 NMOS 영역의 불순물 이온 주입을 보여주고 있다.Next, impurity ions are implanted into each of the NMOS and PMOS regions using a photoresist pattern as a mask on the entire surface of the semiconductor substrate 20. Then, source / drain regions 34 and 34 'are formed in the active regions on both sides of the gate spacer 30 in the cell array region and the peripheral circuit region. 3C shows impurity ion implantation in the NMOS region.
상기 기판(20) 전면에 산화막(38)이 증착되고, DC 형성용 마스크를 이용하여 상기 산화막(38)이 식각되므로서 콘택홀이 형성된다(미도시됨). 상기 콘택홀을 포함하여 산화막(38)상에 폴리실리콘막이 증착된다. 상기 콘택홀에 채워지는 콘택 플러그(40n, 40p)를 형성하기 위해 적어도 상기 산화막의 상부 표면이 노출될때까지 상기 폴리실리콘막이 평탄화 식각된다. 상기 폴리실리콘막의 평탄화 식각은 에치백(etch back)이나 CMP(chemical mechanical polishing)에 의해 수행된다. 상기 폴리실리콘막의 평탄화 식각은 후속 증착되는 금속 비트라인의 리프팅(lifting)을 방지하기 위함이다.An oxide film 38 is deposited on the entire surface of the substrate 20, and a contact hole is formed by etching the oxide film 38 using a DC forming mask (not shown). The polysilicon film is deposited on the oxide film 38 including the contact hole. The polysilicon film is flattened and etched until at least an upper surface of the oxide film is exposed to form contact plugs 40n and 40p filled in the contact hole. The planarization etching of the polysilicon film is performed by etch back or chemical mechanical polishing (CMP). The planarization etching of the polysilicon film is to prevent the lifting of the metal bit line which is subsequently deposited.
도 3d에 있어서, 상기 도전막은 에치백 시간을 늘려 콘택 플러그의 상부 표면이 상기 산화막(38)의 상부 표면보다 낮도록 과식각될 수 있다. 상기 도전막의 과식각은 플러그(40n, 40p)의 전체 높이를 줄여 후속 이온 주입 공정에서 이온 주입 에너지를 과도하게 높이지 않고도 불순물 이온을 플러그에 균일하게 주입할 수 있도록 한다. 상기 콘택 플러그(40n, 40p)의 상부 표면 과식각은 전체 콘택 플러그 높이의 1/3 이하가 되도록 한다.In FIG. 3D, the conductive film may be overetched such that the upper surface of the contact plug is lower than the upper surface of the oxide film 38 by increasing the etch back time. The overetching of the conductive film reduces the overall height of the plugs 40n and 40p so that impurity ions can be uniformly implanted into the plug without excessively increasing the ion implantation energy in a subsequent ion implantation process. The over surface overetch of the contact plugs 40n and 40p is less than one third of the height of the entire contact plug.
도 4를 참조하면, 후속공정으로 폴리사이드 비트 라인이 형성되는 경우, 상기 폴리실리콘막(40)이 상기 산화막(38) 상에 20∼80㎚의 두께범위로 남을 때 까지 평탄화 식각된다. 상기 폴리실리콘막(40)을 상기 산화막(38)상에 일정 두께로 남기는 이유는 후속 실리사이드막의 증착율을 높이기 위함이다. 이는 실리사이드막이 산화막상에서는 형성되기 어려운 특성을 갖기 때문이다.Referring to FIG. 4, when a polyside bit line is formed in a subsequent process, the polysilicon film 40 is flattened and etched until the polysilicon film 40 remains in the thickness range of 20 to 80 nm on the oxide film 38. The reason for leaving the polysilicon film 40 on the oxide film 38 at a predetermined thickness is to increase the deposition rate of the subsequent silicide film. This is because the silicide film has a characteristic that is difficult to be formed on the oxide film.
다음으로, 도 3e를 참조하면, NMOS 영역의 콘택 플러그(40n)에는 N+형 불순물 이온이 주입되고, PMOS 영역의 콘택 플러그(40p)에는 P+형 불순물 이온이 주입된다. 상기 N+형 불순물 이온 주입시, 예를 들어, P는 100∼300KeV의 이온 주입 에너지와 1∼5×1015의 도즈(dose)에 의해 콘택 플러그(40n)에 주입된다. 계속해서, 50∼200KeV의 에너지와 1∼5×1015의 도즈로 이온 주입이 수행되어 NMOS 영역의 콘택 플러그의 표면 불순물 농도가 증가된다.Next, referring to FIG. 3E, N + type impurity ions are implanted into the contact plug 40n of the NMOS region, and P + type impurity ions are implanted into the contact plug 40p of the PMOS region. In the N + type impurity ion implantation, for example, P is implanted into the contact plug 40n by ion implantation energy of 100 to 300 KeV and dose of 1 to 5x10 15 . Subsequently, ion implantation is performed at an energy of 50 to 200 KeV and a dose of 1 to 5 x 10 15 to increase the surface impurity concentration of the contact plug in the NMOS region.
반면에, P+형 불순물 이온 주입시, 예를 들어, B는 50∼150KeV의 이온 주입 에너지와 1∼5×1015의 도즈(dose)에 의해 콘택 플러그(40p)에 주입된다. 계속해서, 10∼30KeV의 에너지로 이온 주입이 수행되어 PMOS 영역의 콘택 플러그의 표면 불순물 농도가 증가된다.On the other hand, during P + type impurity ion implantation, for example, B is implanted into the contact plug 40p by ion implantation energy of 50 to 150 KeV and dose of 1 to 5 x 10 15 . Subsequently, ion implantation is performed at an energy of 10 to 30 KeV to increase the surface impurity concentration of the contact plug in the PMOS region.
상술한 바와 같이, 동시에 형성된 콘택 플러그들에 불순물 이온이 주입된 후, 상기 불순물의 활성화를 위해 어닐링 공정이 700℃∼850℃의 온도 범위에서 30∼60분간 진행된다. 그리고 N+ 및 P+ 불순물 영역상에 형성되는 콘택 플러그의 도판트(dopant)들의 활성화를 위해 RTA(rapid thermal anneal)가 900℃∼100℃의 범위에서 10∼30초간 진행된다.As described above, after the impurity ions are injected into the simultaneously formed contact plugs, an annealing process is performed for 30 to 60 minutes in the temperature range of 700 ° C to 850 ° C to activate the impurities. In addition, rapid thermal anneal (RTA) is performed for 10-30 seconds in the range of 900 ° C to 100 ° C to activate dopants of contact plugs formed on N + and P + impurity regions.
도 3f를 참조하면, 금속 비트라인 예를 들어, W, TiN, WN이 기판 전면에 증착되거나 또는 폴리사이드 비트라인(44) 예를 들어, WSix/폴리실리콘, TiSix/폴리실리콘이 증착된다.Referring to FIG. 3F, metal bit lines, eg, W, TiN, WN, are deposited over the substrate or polyside bitlines 44, eg, WSix / polysilicon, TiSix / polysilicon, are deposited.
도면에는 도시되진 않았지만 비트라인 패터닝후 금속 배선이 형성된다. 이때, P+ 불순물 영역에 대해 콘택 플러그가 형성되므로 P+의 콘택을 위한 금속 브리지에 비해 단차가 줄어들게 된다.Although not shown in the figure, metal wiring is formed after bit line patterning. At this time, since the contact plug is formed for the P + impurity region, the step difference is reduced compared to the metal bridge for the contact of P +.
이상과 같은 본 발명에 의하면, 셀 어레이 영역과 주변 영역의 활성 영역에 SEG막을 형성한후, 기판의 불순물 영역상에 DC가 동시에 형성되므로서 P+ 영역에 대한 면적이 줄어들게 된다.According to the present invention as described above, after the SEG film is formed in the active region of the cell array region and the peripheral region, the area for the P + region is reduced because DC is simultaneously formed on the impurity region of the substrate.
또, 본 발명에 따르면 셀 어레이 영역과 주변 영역에 대해 동시에 형성된 DC에 불순물 이온을 주입하므로 공정을 단순화하는 효과가 있다.In addition, according to the present invention, since impurity ions are implanted into DC formed at the same time in the cell array region and the peripheral region, the process is simplified.
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