KR20000015548A - Sub wordline driving circuit - Google Patents

Abstract

PURPOSE: A sub wordline driving circuit is provided to reduce the number of transistor forming the sub wordline circuit. CONSTITUTION: The sub word line driving circuit comprises: the 1st sub wordline driving part that the 1st output terminal, formed by the connection of a terminal of the 1st switch and a terminal of the 2nd switch, outputs the first sub wordline driving signal(SWL), that main wordline driving signal(MWL) is inputted to other terminal of the 1st switch, that other terminal of the 2nd switch is grounded and that the 1st and 2nd switches are switched by the 1st selection signal; the 2nd sub wordline driving part that the 2nd output terminal, formed by the connection of a terminal of the 3rd switch and a terminal of the 4th switch, outputs the 2nd sub wordline driving signal(SWL), that main wordline driving signal(MWL) is inputted to other terminal of the 3rd switch, that other terminal of the 4th switch is grounded and that the 3rd and 4th switches are switched by the 2nd selection signal; and the 5th switch, of which both terminals are connected between the 1st and 2nd output terminals, that is switched by main wordline driving bar signal(MWLB).

Description

Sub word line driver circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub word line driving circuit of a semiconductor memory and relates to a sub word line driving circuit configured to be driven by one main word line to drive a plurality of sub word lines.

In the semiconductor memory, the word line is driven to control the gate of the cell transistor, so the word line is the gate of the cell transistor. Therefore, since the word line has a large capacitance and is made of relatively high resistance polysilicon, the word line driving signal has a large delay.

To solve this problem, hierarchical word line structure is used. The hierarchical word line structure connects a plurality of sub word lines to a main word line and drives a plurality of sub word lines through a single main word line.

In the hierarchical word line structure, only sub word lines are made of polysilicon, and main word lines and sub word line selection signal lines are made of metal (such as aluminum) to minimize signal delay.

In order to drive each sub word line connected to the main word line, a sub word line driving circuit is required for each sub word line, which is shown in FIG. 1.

The PMOS transistor 102 and the NMOS transistor 104 are connected in series to form one sub word line driver. In the sub word line driver generating the first sub word line driving signal SWL1, the first sub word line selection signal FX1 is input to the source of the PMOS transistor 102, and the source of the NMOS transistor 104 is provided. Is grounded. Each gate of the PMOS transistor 102 and the NMOS transistor 104 is controlled by the main word line driver bar signal MWLB.

The drains of the PMOS transistor 102 and the NMOS transistor 104 are connected to each other to form an output terminal for outputting the first sub word line driving signal SWL1. An NMOS transistor 106 is connected between the output terminal and ground VSS, and the gate of the NMOS transistor 106 is complementary to the first sub word line select bar signal FXB1 (the first sub word line select signal). Signal).

Another sub word line driver is formed to drive the second sub word line symmetrically with the first sub word line driver. The second sub word line driver is formed by connecting the PMOS transistor 108 and the NMOS transistor 110 in series. The second sub word line selection signal FX2 is input to the source of the PMOS transistor 108, and the source of the NMOS transistor 110 is grounded. Each gate of the PMOS transistor 108 and the NMOS transistor 110 is controlled by the main word line driver bar signal MWLB.

The drains of the PMOS transistor 108 and the NMOS transistor 110 are connected to each other to form an output terminal for outputting the second sub word line driving signal SWL2. An NMOS transistor 112 is connected between the output terminal and the ground VSS, and the gate of the NMOS transistor 112 is the complement of the second sub word line select bar signal FXB2 (the second sub word line select signal). Signal).

When the main word line driving signal MWL is activated at a high level, the main word line selection bar signal MWLB, which is a complementary signal, is turned low to turn on the PMOS transistors 102 and 108 of each sub word line driver. Let's do it. Accordingly, the first and second sub word line driving signals SWL1 and SWL2 activated at high levels are output from the output terminal of each sub word line driver.

In practice, however, whether to activate each sub word line selection signal SWL1 or SWL2 is determined according to the on / off state of the NMOS transistors 106 and 112 connected to the output terminal of each sub word line driver.

That is, when the first sub word line selection signal FX1 is activated at a high level, the first sub word line selection bar signal FXB1, which is a complementary signal, is at a low level, thereby driving the NMOS transistor 106 of the first sub word line driver. Turn off. Accordingly, the first sub word line driving signal SWL1 may be activated to a high level.

At this time, since the second sub word line selection signal FX2 will be inactivated to a low level, the second sub word line selection bar signal FXB2, which is a complementary signal, is at a high level, so that the NMOS transistor 112 of the second sub word line driver is high. Turn on. Accordingly, the second sub word line driving signal SWL1 is inactivated to a low level by the ground voltage VSS.

In FIG. 1, only two sub word line driving signals SWL1 and SWL2 are generated by one main word line driving bar signal MWLB, but in reality, several sub word line driving bar signals MWLB are generated by one main word line driving bar signal. The sub word line drive signal is configured to be generated.

Referring to FIG. 1, it can be seen that the two sub word line driving circuits are composed of six MOS transistors. However, the degree of integration of semiconductor memories has been greatly improved, and memory cells have a tendency to greatly reduce their pitch (diagonal distance). Therefore, the size of the word line driver circuit also needs to be reduced.

Accordingly, an object of the present invention is to reduce the number of transistors constituting the sub word line driver circuit.

The present invention for this purpose comprises a first and second sub word line driver and a fifth switch.

The first sub word line driver outputs a first sub word line driving signal to a first output terminal formed by connecting one end of the first switch and one end of the second switch, and a main word line driving signal to the other end of the first switch. Input, the other end of the second switch is grounded, and the first and second switches are switched by the first selection signal.

The second sub word line driver outputs a second sub word line drive signal to a second output terminal formed by connecting one end of the third switch and one end of the fourth switch, and a main word line drive signal to the other end of the third switch. Input, the other end of the fourth switch is grounded, and the third and fourth switches are switched by the second selection signal.

The fifth switch has both ends connected between the first output terminal and the second output terminal, and is switched by a main word line driving bar signal.

1 is a diagram illustrating a sub word line driving circuit of a conventional semiconductor memory.

2 is a diagram illustrating a sub word line driving circuit of a semiconductor memory according to the present invention;

Explanation of symbols on the main parts of the drawings

MWL: Main word line drive signal MWLB: Main word line drive bar signal

SWL: Sub word line drive signal SWLB: Sub word line drive bar signal

FX: Sub word line selection signal FXB: Sub word line selection bar signal

The preferred embodiment of the present invention thus made will be described with reference to FIG. 2 as follows. 2 is a diagram illustrating a sub word line driving circuit of a semiconductor memory according to the present invention.

The PMOS transistor 202 and the NMOS transistor 204 are connected in series to form one sub word line driver. In the sub word line driver generating the first sub word line driving signal SWL1, the main word line driving signal MWL is input to the source of the PMOS transistor 202, and the source of the NMOS transistor 204 is grounded. do. Each gate of the PMOS transistor 202 and the NMOS transistor 204 is controlled by the first sub word line select bar signal FXB1.

Drains of the PMOS transistor 202 and the NMOS transistor 204 are connected to each other to form a first output terminal for outputting the first sub word line driving signal SWL1.

Another sub word line driver is formed to drive the second sub word line symmetrically with the first sub word line driver. The second sub word line driver is formed by connecting the PMOS transistor 206 and the NMOS transistor 208 in series. The main word line driving signal MWL is input to the source of the PMOS transistor 206, and the source of the NMOS transistor 208 is grounded. Each gate of the PMOS transistor 206 and the NMOS transistor 208 is controlled by the second sub word line select bar signal FXB2.

Drains of the PMOS transistor 206 and the NMOS transistor 208 are connected to each other to form a second output terminal for outputting the second sub word line driving signal SWL2.

The source and the drain of the NMOS transistor 210 are connected between the first output terminal of the first sub word line driver and the second output terminal of the second sub word line driver. The gate of the NMOS transistor 210 is controlled by the main word line driver bar signal MWLB.

The NMOS transistor 210 is turned on while the main word line driving signal MWL is at a low level (deactivation state), during which the first sub word line selection bar signal FXB1 or the second sub word line selection bar signal is turned on. When FXB2 is at a high level (also in an inactive state), the NMOS transistors 204 and 206 are turned on so that both the first sub word line driving signal SWL1 and the second sub word line driving signal SWL2 are low level. Is deactivated.

If the main word line driving signal MWL is activated at a high level (the NMOS transistor 210 is turned off) and the first sub word line select bar signal FXB1 is at a low level (activated state), the PMOS transistor 202 may be used. ) Is turned on and the high level voltage of the main word line driving signal MWL is output as the first sub word line driving signal SWL1 at the first output terminal.

When the second sub word line selection bar signal FXB2 is at a low level (activated state), the opposite PMOS transistor 206 is turned on so that the high level voltage of the main word line driving signal MWL is also reduced at the second output terminal. It is output as two sub word line driving signals SWL2.

The first and second sub word line driving signals SWL1 and SWL2 generated as described above drive the corresponding sub word line.

The sub word line driving circuit according to the present invention shown in FIG. 2 is configured to generate only two sub word line driving signals. The sub word line driving signal may be selectively generated.

As a result, it can be seen that the number of transistors constituting the sub word line driving circuit according to the present invention is reduced. In a memory having a storage capacity of 1 Mb (1k × 1k), all 1024 word lines must be driven, and thus 1024 sub word line driving circuits are required. In the sub word line driving circuit according to the present invention, one transistor is reduced for every two sub word line driving circuits. Thus, when the sub word line driving circuit according to the present invention is adopted, all 512 transistors are reduced. If the memory has a storage capacity of 16Mb, 8192 transistors (512 × 16) can be reduced.

Claims (4)

In the sub word line driving circuit, A first sub word line driving signal is output to a first output terminal formed by connecting one end of the first switch to one end of the second switch, and a main word line driving signal is input to the other end of the first switch. A first sub word line driver to which the other end of the ground is grounded and the first and second switches are switched by a first selection signal; A second sub word line driving signal is output to a second output terminal having one end of a third switch and one end of a fourth switch connected thereto, and the main word line driving signal is input to the other end of the third switch. A second sub word line driver to which the other end of the switch is grounded and the third and fourth switches are switched by a second selection signal; And a fifth switch coupled between the first output terminal and the second output terminal and switched by a main word line driving bar signal. The sub word line driver circuit of claim 1, wherein the first switch and the second switch are formed of a PMOS transistor and an NMOS transistor, respectively, so that the first switch and the second switch are turned on complementarily by the first selection signal. The sub word line driver circuit of claim 1, wherein the third switch and the fourth switch are formed of a PMOS transistor and an NMOS transistor, respectively, so that the third switch and the fourth switch are turned on complementarily by the second selection signal. The sub word line driver circuit according to claim 1, wherein the fifth switch is an NMOS transistor.