KR19990045050A - Semiconductor memory device having circuitry for generating different word line voltages - Google Patents

Abstract

The semiconductor memory device disclosed herein includes at least one memory cell having a threshold voltage of one of a plurality of threshold voltages and storing multi-bit data, at least one word line connected to the memory cell, and a data read operation. And a word line voltage generation circuit that sequentially generates other word line voltages to be applied to the word line when data is read from the memory cell. The other word line voltages are automatically adjusted by the word line voltage generation circuit so that the gate-source voltage of the memory cell remains constant when the threshold voltage or other word line voltages of the memory cell change.

Description

A SEMICONDUCTOR MEMORY DEVICE WITH A CIRCUIT FOR GENERATING DIFFERENT WORD LINE VOLTAGES

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to word line voltage generation circuits for use in semiconductor memory devices storing multi-bit data.

For example, a memory cell array of read-only memory (hereinafter referred to as ROM) includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A plurality of word lines extends along the rows of memory cells, and a plurality of bit lines extends along the columns of the memory cells. Each memory cell has a gate connected to a corresponding word line, a grounded source, and a drain connected to a corresponding bit line. To read data from an addressed (or selected) memory cell, a bit line connected to the addressed memory cell is selected, and a word line connected to the addressed memory cell is set to a word line voltage.

In general, a memory cell that stores 1-bit data has one transistor. The threshold voltage of the transistor is set at a high or low level such that the memory cell stores data. However, the memory cell stores one bit of data at a time. In order to store a large amount of data, the memory cell array must have more memory cells in proportion to the amount of data to be stored, which causes the chip size to inevitably increase.

In order to manufacture a memory device that stores a large amount of data without increasing the chip size, it has recently been proposed that two bits of data be stored in one memory cell. Such memory cells are called "multi-level memory" or "multi-bit memory". Several kinds of multi-level memories are provided. In one type, the gate length or gate width of each memory cell transistor is varied such that the current flowing when the memory cell is selected is set to various values. In another type, the amount of impurity ions injected into the MOS transistor of each memory cell is varied so that the threshold voltage of the MOS transistor is varied to various values. Each memory cell of a multi-level memory device may store two or more bits when set to two or more states. Therefore, the storage capacity of the multi-level memory device is increased.

1 shows the relationship between word line voltage and threshold voltage distributions according to multi-level data states when one memory cell stores 2-bit data. Each memory cell of a multi-bit ROM has one of four different threshold voltages Vth1-Vth4. The threshold voltages Vth1 to Vth4 have a relationship of Vth1 <Vth2 <Vth3 <Vth4. The memory cell having the threshold voltage Vth1 is determined as the memory cell M00, the memory cell having the threshold voltage Vth2 is determined as the memory cell M01, and the memory cell having the threshold voltage Vth3. Is determined as the memory cell M10, and the memory cell having the threshold voltage Vth4 will be determined as the memory cell M11. Assume that the memory cells M00, M01, M10, and M11 store "0", "1", "10", and "11", respectively.

2 is a diagram illustrating a voltage change applied to a word line during a data read operation. 1 and 2, a data read operation of a memory cell that stores two bits of data will be described below.

First, a word line connected to a selected memory cell that stores 2-bit data is driven with a first word line voltage WL0, and then whether current flows through the selected memory cell is determined by the sense amplifier circuit 17 (Fig. 3). Then, after the second word line voltage WL1 higher than the first word line voltage WL0 is applied to the word line associated with the selected memory cell, whether or not the cell current flows through the memory cell is thereby determined. Is determined. Finally, a third word line voltage WL2 higher than the first and second word line voltages WL0 and WL1 is applied to the word line, and then cell current flows through the memory cell. Is determined. As mentioned above, in the case where the memory cell stores 2-bit data (ie, one of "0", "1", "10" and "11"), other word line voltages WL0, Three sensing operations are sequentially performed using WL1 and WL2, and then the results thus sensed are logically combined, resulting in a data read operation being completed. It is very important in a memory device to store multi-bit data that the word line voltage with such different levels is accurately controlled to the required level as shown in FIG. 2 during the data read operation. A scheme for controlling word line voltage in a conventional semiconductor memory device 1 storing multi-bit data is shown in FIG.

Referring to FIG. 3, the semiconductor memory device 1, although not shown in the figures, is arranged at the intersection of a plurality of word lines, a plurality of bit lines, the word lines and the bit lines, and each two or more. It includes a memory cell array 10 composed of a plurality of memory cells that store a lot of bit data. One of the word lines is selected by the row free decoder circuit 11 and the block decoder circuit 12 in accordance with the address Ai, the word line voltage generator circuit 13 generates a voltage VP and performs a data read operation. While supplying the voltage VP through the circuits 11 and 12 to the selected word line. The voltage VP has different voltage levels WL0, WL1 and WL2 as shown in FIG. 2. When the device 1 operates under a low power supply voltage, the word line voltage generation circuit 13 is a power supply voltage (VCC) from the word line voltage source 14 or a voltage VPP higher than the voltage VCC. The voltage source 14 is a high voltage generator, which then generates other voltages as a word line voltage VP. The bit line connected to the selected memory cell is selected through column decoder circuit 15 and column pass gate circuit 16, and then the sense amplifier circuit 17 selects a memory cell whose cell current is connected to the selected bit line. Determine whether it flows through.

A word line voltage generator circuit 13 for use in the semiconductor memory device 1 of FIG. 3 according to the prior art is shown in detail in FIG. The word line voltage generator circuit 13 was published in US Patent Publication No. 5457650 entitled "APPARATUS AND METHOD FOR READING MULTI-BIT DATA STORED IN A SEMICONDUCTOR MEMORY."

As shown in Fig. 4, the word line voltage generation circuit 13 has three dummy cells M01, M10 and M11, each including an NMOS transistor. The dummy cells M01, M10, and M11 have threshold voltages Vth2, Vth3, and Vth4, respectively. The dummy cells M01, M10 and M11 have grounded sources and drains and gates connected to the PMOS transistor 47 through resistors RM11, RM22 and RM33. The transistor 47 has a gate connected to receive a signal CEB and a source connected to a power supply voltage VCC / VPP from the word line voltage source 14 of FIG. Drains of the dummy cells M01, M10, and M11 are connected to gates of the NMOS transistors 41, 42, and 43, respectively. The sources of the transistors 41, 42, and 43 are grounded through a resistor RM44. The drains of the transistors 41, 42, and 43 are connected to the drains of the PMOS transistors 44, 45, and 46, respectively. The transistors 44, 45, and 46 have gates connected to receive signals NO_ACT1, NO_ACT2, and NO_ACT3, and their sources are connected to the power supply voltage VCC / VPP. . The output voltage VP is applied from a node where the sources of the transistors 41, 42 and 43 are connected to the resistor RM44.

The resistors RM11, RM22 and RM33 have a large resistance value. The transistors 41, 42, and 43 are enhancement-type transistors with threshold voltages near zero volts. When the signal CEB supplied to the gate of the PMOS transistor 47 is at the low level, the voltage of the node 4B is almost the threshold voltage Vth2 for two reasons. First, almost no current flows through the dummy cell M01 because the resistor RM11 has a large resistance value. Secondly, when the voltage of the node 4B is increased above the threshold voltage Vth2 of the dummy cell M01 because the gate and the drain of the dummy cell M01 are connected to each other, the current suddenly becomes a dummy cell ( M01). When the power supply voltage changes, the voltage of the node 4B is also Vth2. This is due to the current flowing through the dummy cell M01 when the voltage at the node 4B increases above Vth2.

For a similar reason, the voltage of the node 4C is equal to the threshold voltage Vth3 of the dummy cell M10, and the voltage of the node 4D is equal to the threshold voltage Vth4 of the dummy cell M11. The transistors 41, 42, and 43 are incremental transistors having threshold voltages almost equal to 0V as mentioned above, and the resistor RM44 has a large resistance value. Therefore, the output voltage VP is almost equal to the voltage of Vth2 when the signal NO_ACT1 is at the low level, and almost equal to the voltage of Vth3 (the voltage at the node 4C) when the signal NO_ACT2 is at the low level. Same), and Vth4 (nearly equal to the voltage of the node 4D) when the signal NO_ACT3 is at the low level.

The output voltage VP of the word line voltage generator circuit 13 is applied to the row pre decoder circuit 11. Therefore, the word line voltage is Vth2 when the signal NO_ACT1 is low level, the word line voltage is Vth3 when the signal NO_ACT2 is low level, and the word line voltage is low level when the signal NO_ACT3 is low level. Is Vth4.

The aforementioned word line voltage generation circuit 13 according to the prior art is designed such that when the output voltage VP becomes higher, the output voltage VP is lowered through the resistor RM44 by that increased level. . On the other hand, when the output voltage VP becomes lower than the required word line voltage, it is impossible to cause the output voltage VP to increase. The threshold voltages Vth2, Vth3, and Vth4 of the dummy cells M01, M10, and M11 and the threshold voltages of the transistors 41, 42, and 43 Because it is fixed. In addition, when the threshold voltages of the transistors 41, 42, and 43 are changed due to a process change, the output voltage VP, that is, the word line voltage, will be changed even more.

If the source voltages of the NMOS transistors 41, 42 and 43 are changed, their dress voltages change according to body effects well known in the art. Since the source voltages are different in each sensing operation, the amount of change in the threshold voltage of each of the transistors 41, 42, and 43 is also different. As a result, the gate-source voltage Vgs of the selected memory cell is different in each sensing operation. Therefore, the cell current flowing through the selected memory cell is different in each sensing period, and as a result, the sensing margin of the selected memory cell will be reduced. That is, the reliability of the data read operation is worse, and in the worst case, the data read operation is failed. Therefore, there is a need for a word line voltage generation circuit of a semiconductor memory device in which the gate-source voltage of each memory cell is kept constant.

Accordingly, an object of the present invention is to provide a semiconductor memory device having improved reliability for storing multi-bit data in one memory cell.

Another object of the present invention is to provide a multi-bit semiconductor memory device having a word line voltage generation circuit capable of keeping the gate-source voltage of a memory cell constant regardless of process variations.

1 shows the relationship between word line voltages and threshold voltage distributions according to multi-level data states when one memory cell stores 2-bit data;

2 is a diagram showing a voltage change applied to a word line during a data read operation;

3 is a block diagram of a conventional semiconductor memory device having a word line voltage generation circuit;

4 illustrates a word line voltage generation circuit of the semiconductor memory device of FIG. 3 according to the prior art;

FIG. 5 shows a word line voltage generation circuit of the semiconductor memory device of FIG. 3 according to the first preferred embodiment of the present invention; FIG.

FIG. 6 is a timing diagram for describing an operation of the word line voltage generation circuit of FIG. 5; FIG.

FIG. 7 shows a word line voltage generating circuit of the semiconductor memory device of FIG. 3 in accordance with a second preferred embodiment of the present invention; FIG. And

FIG. 8 is a diagram illustrating a word line voltage generation circuit of the semiconductor memory device of FIG. 3 according to the second embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

10: memory cell array 11: row predecoder circuit

12: block decoder circuit 13: word line voltage generation circuit

14 word line voltage source 15 column decoder circuit

16: thermal pass gating circuit 17 sense amplifier circuit

According to an aspect of the present invention for achieving the above object, the semiconductor memory device of the present invention has at least one memory cell having one of the plurality of threshold voltages and storing multi-bit data At least one word line coupled to the memory cell, and a word line voltage generation circuit that sequentially generates other word line voltages to be applied to the word line when data is read from the memory cell during a data read operation.

According to such a semiconductor memory device, the other word line voltages are connected to the word line voltage generation circuit so that the gate-source voltage of the memory cell is kept constant when the threshold voltage or other word line voltages of the memory cell are changed. Is adjusted automatically.

Embodiments of the present invention are described in detail below with reference to the drawings.

FIG. 5 is a circuit diagram showing a word line voltage generation circuit 13-1 for use in the semiconductor memory device 1 for storing multi-bit data according to the first preferred embodiment of the present invention. In the first embodiment, it is apparent to those skilled in the art that the circuit 13-1 is implemented in the semiconductor memory device 1 of Fig. 3, and the description of other components is therefore omitted. As shown in Fig. 5, the word line voltage generation circuit 13-1 obtains an optimal word line voltage VP for reading data even if the power supply voltage changes or the memory cells have different characteristics from those designed. Three dummy cells M00, M01, and M10 having the threshold voltages Vth1, Vth2, and Vth3 are used to generate them.

5, the circuit 13-1 includes a reference voltage generator 62 and first to third word line voltage generators 100a, 100b and 100c. The reference voltage generator 62 generates a reference voltage Vref of a constant level, for example, 2V, regardless of a power supply voltage change, and converts the reference voltage Vref into the first to third word line voltage generators. It supplies to (100a), (100b), and (100c). The first to third word line voltage generators 100a, 100b, and 100c are connected to a node VP1, that is, a node ND1 for outputting a word line voltage. Each of the generators 100a, 100b and 100c accepts the voltage (VCC / VPP) from the word line voltage source 14 of FIG. 3 as the power supply voltage. In addition, the node ND1 is discharged through the NMOS transistor 59 which is switched on / off in accordance with the signal STG before and after the data read operation. The first word line voltage generator 100a generates the voltage VP of the first word line voltage WL0 level of FIG. 2 when the first sensing operation is performed, and the second word line voltage generator 100b. The second word line voltage generator 100c generates a voltage VP of the second word line voltage WL1 level when the second sensing operation is performed, and the third word line voltage generator 100c performs the third sensing operation when the third sensing operation is performed. A voltage VP of the third word line voltage WL2 level of two is generated.

The first word line voltage generator 100a includes a detection circuit 110a, a dummy cell M00, a PMOS transistor 54, an NMOS transistor 58, and a capacitor 60. The detection circuit 110a consists of three PMOS transistors 51, 52 and 53 and two NMOS transistors 56 and 57. The PMOS transistors 51 and 53 function as current mirror circuits. The PMOS transistor 51 whose gate accepts the signal NO_ACT1 has one current electrode which receives the voltage VCC / VPP from the voltage source 14 of FIG. 3 and another current electrode connected to the node 5C. The signal NO_ACT1 is activated to a high level only during the period in which the first sensing operation is performed. The PMOS transistor 52 has a current path formed between the voltage VCC / VPP and the node 5C and a gate connected to the node 5C, that is, the drain. PMOS transistor 53 having a gate connected to node 5C has a current path formed between the voltage VCC / VPP and node ND1. NMOS transistors 56 and 57 in which current paths are formed in series between the node 5C and ground, respectively, have gates connected to node 5A and receiving a signal NO_ACT1. The dummy cell M00 is set to have a threshold voltage Vth1 and has a gate connected to one end of the capacitor 60. One current electrode of the cell M00 is grounded and its other current electrode is connected to the reference voltage generator 62 through a gated PMOS transistor 54. The other end of the capacitor 60 is connected to the node ND1. The NMOS transistor 58 whose gate is supplied with the signal STG has a current path formed between the gate of the node 5B, that is, the dummy cell M00 and ground.

In the first embodiment, the current driving capability of the PMOS transistor 54 is smaller than that of the dummy cell M00. In other words, the PMOS transistor 54 functions as a transistor for precharging the node 5A. The signal STG is activated to a high level before and after the data read operation is performed, and the signal NO_ACT1 indicates a first sensing operation (or interval).

In the second and third word line voltage generators 100b and 100c, the same components as those of the first word line voltage generator 100a are denoted by the same reference numerals. For convenience, descriptions of such components are not repeated. The second word line voltage generator 100b differs from the first word line voltage generator 100a in that the dummy cell M01 has a threshold voltage Vth2 higher than the threshold voltage of the dummy cell M00. . Therefore, when the signal NO_ACT2 is activated, that is, during the second sensing period, the voltage VPP becomes higher than the first sensing period. In addition, the third word line voltage generator 100c includes the first and the second points that the dummy cell M10 has a higher threshold voltage Vth3 than the threshold voltages of the dummy cells M00 and M01. Is different from the two word line voltage generators 100a and 100b. Therefore, when signal NO_ACT3 is activated, that is, during the third sensing period, the voltage VPP becomes higher than the second sensing period.

Fig. 6 is a timing chart for explaining the operation of the word line voltage generation circuit 13-1 according to the first preferred embodiment of the present invention. The operation of the word line voltage generation circuit 13-1 will be described below with reference to Figs.

When the voltage VP, that is, the word line voltage to be supplied to the selected memory cell is not generated from the word line voltage generation circuit 13-1, as shown in Fig. 6, the signal STG is in a high level state. And the signals NO_ACT1, NO_ACT2 and NO_ACT3 are in a low level state. This causes transistors 51 and 56 to be electrically conductive and transistor 57 is not electrically conductive, as a result node 5C is charged up to voltage VCC / VPP through PMOS transistor 51. As a result, the current path of the PMOS transistor 53 does not occur. At this time, the gates of the dummy cells M00, M01, and M10 are initialized to a low level, that is, 0V through the NMOS transistor 58 switched on by the signal STG. In the first embodiment, there is no current consumed by the word line voltage generators 100a, 100b, and 100c when the data read operation is not performed, so that no current path of the transistor 57 is formed. Because it does not.

If the data read operation starts, as shown in Fig. 6, the signal STG goes from the high level to the low level, and the signal NO_ACT1 goes to the high level. At the same time, the signals NO_ACT2 and NO_ACT3 continue to be at a low level. This causes the first word line voltage generator 100a to be activated and the second and third word line voltage generators 100b and 100c to be deactivated. The PMOS transistor 51 of the first word line voltage generator 100a is deactivated and its NMOS transistor 57 is activated according to the activated signal NO_ACT1, so that the node 5C is connected to the NMOS transistors ( Discharge through 56) and (57).

When the gate potential of the PMOS transistor 53 becomes the ground voltage, the potential of the node ND1 is gradually increased to the required word line voltage. As the node ND1 potential is increased, the gate potential of the dummy cell M00 is also increased by the boosting capacitor 60. That is, a voltage Vg proportional to the coupling ratio between the gate capacitance and the capacitor 60 capacitance is applied to the gate of the dummy cell M00. The voltage Vg thus increased is expressed as follows.

Here, the symbol Ccap represents the capacitance of the capacitor 60 and the symbol Ccel represents the gate capacitance of the dummy cell M00.

As the potential of the node ND1 continues to increase, the gate voltage Vg of the dummy cell M00 becomes the threshold voltage Vth1 of the dummy cell M00, and as a result, the dummy cell M00 is turned on. do. Node 5A having a reference voltage Vref is discharged below the threshold voltage of the NMOS transistor 56 through the dummy cell M00, which causes the NMOS transistor 56 to be turned off. The node 5C becomes the voltage of (VCC / VPP-Vtp) (Vtp is the threshold voltage of the transistor 52), and then the PMOS transistor 53 is turned off. That is, the detection circuit 110a detects whether or not current flows through the dummy cell M00, and then supplies current to the node ND1 according to the detection result. As a result, the voltage VP, that is, the word line voltage WL0 is set to a voltage of (Vth1 + Voffset). The voltage Voffset represents a sensing margin as the gate-source voltage Vgs of the memory cell. The voltage Voffset is determined by the coupling ratio and remains constant.

Subsequently, the signal NO_ACT1 is deactivated to the low level while the signal NO_ACT2 is activated to the high level as shown in FIG. The second and third word line voltage generators 100b and 100c generate voltages of (Vth2 + Voffset) and (Vth3 + Voffset). Operation descriptions of the generators 100b and 100c are omitted to avoid duplication of description. After three sensing operations are completed, the signal STG goes from low level to high level. This causes the node ND1 to become the ground voltage (0V), and as a result, the word line voltage generation circuit 13-1 is deactivated.

In the first embodiment, each of the word line voltage generators 100a, 100b, and 100c includes dummy cells M00 and M00 set to the threshold voltages Vth1, Vth2, and Vth3, respectively. M10) and M10 are provided. For this reason, even if the dress voltage of the memory cell is changed due to the process change, the dress voltages of the dummy cells are also changed in the same manner. In particular, it should be noted that the voltage VP, that is, the word line voltage is maintained at the voltage of (Vth1 / 2/3 + Voffset). This means that the gate-source voltage Vgs of the memory cell is fixed at the voltage Voffset during each sensing operation (meaning that the cell current flows constantly through the memory cell). Therefore, the data read operation can be reliably performed.

Furthermore, in the first embodiment, the capacitances of the capacitors 60 in the first to third word line voltage generators 100a, 100b, and 100c are set such that the sensing margins are equal to each other during each sensing operation. do. However, it is apparent to those skilled in the art that the sensing margin can be set differently in each sensing operation by setting the values of the capacitors 60 differently.

FIG. 7 is a circuit diagram of a word line voltage generator circuit 13-2 for use in the semiconductor memory device 1 of FIG. 3 according to the second preferred embodiment of the present invention. In FIG. 7, the same components as those of FIG. 5 are denoted by the same reference numerals.

As shown in Fig. 7, the word line voltage generation circuit 13-2 has three words commonly connected to the reference voltage generator 62 and the voltage VP, that is, the node ND2 for outputting the word line voltage. Line voltage generators 120a, 120b, and 120c. The second embodiment is characterized in that the coupling capacitor 60 of FIG. 5 has been removed and that the PMOS transistors 61 of each of the generators 120a, 120b and 120c are used as resistive elements instead of precharge transistors. It differs from the first embodiment in that it functions. Like the circuit 13-1 of FIG. 5, the word line voltage generation circuit 13-2 also operates in accordance with the timing diagram of FIG.

When the voltage VP, that is, the word line voltage to be supplied to the selected memory cell is not generated from the word line voltage generation circuit 13-2, as shown in Fig. 6, the signal STG is in a high level state. And the signals NO_ACT1, NO_ACT2 and NO_ACT3 are in a low level state. This causes transistors 51 and 56 to be electrically conductive and transistor 57 is not electrically conductive, as a result node 5E is charged up to voltage VCC / VPP through PMOS transistor 51. As a result, the current path of the PMOS transistor 53 does not occur. At this time, the node ND2 is initialized to a low level, that is, 0V through the NMOS transistor 59 switched on by the signal STG. As in the first embodiment, there is no current consumed by the word line voltage generators 120a, 120b, and 120c when the data read operation is not performed, so that no current path of the transistor 57 is formed. Because it does not.

If the data read operation starts, as shown in Fig. 6, the signal STG goes from the high level to the low level, and the signal NO_ACT1 goes to the high level. At the same time, the signals NO_ACT2 and NO_ACT3 continue to be at a low level. This causes the first word line voltage generator 120a to be activated and the second and third word line voltage generators 120b and 120c to be deactivated. The PMOS transistor 51 of the first word line voltage generator 120a is deactivated and its NMOS transistor 57 is activated according to the activated signal NO_ACT1, so that the node 5E is connected to the NMOS transistors ( Discharge through 56) and (57).

After a predetermined time has elapsed, that is, when the gate potential of the PMOS transistor 53 becomes the ground voltage, the potential of the node ND2 is gradually increased to the required word line voltage. As the potential of the node ND2 increases, the gate potential of the dummy cell M00 also rises to the potential of the node ND2, and as a result, the dummy cell M00 is turned on. Since the current driving capability of the PMOS transistor 61 is larger than that of the dummy cell M00, the node 5D voltage is continuously maintained at a voltage higher than the threshold voltage of the transistor 56.

As the potential of the node ND2 continues to increase, the gate voltage of the dummy cell M00 becomes higher than the threshold voltage Vth1 of the dummy cell M00, so that the node 5D voltage becomes higher than the transistor 56. Decreases below the threshold voltage. As a result, the NMOS transistor 56 is turned off, and the node 5E becomes the voltage of (VCC / VPP-Vtp) (Vtp is the threshold voltage of the transistor 52), and the PMOS transistor 53 Is turned off. That is, the detection circuit 130a detects whether or not current flows through the dummy cell M00, and then supplies current to the node ND2 in accordance with the detection result. Therefore, the voltage VP, that is, the word line voltage WL0 is set to a voltage of (Vth1 + Voffset). The voltage Voffset represents a sensing margin as the gate-source voltage Vgs of the memory cell. The voltage Voffset is determined by the ratio of the turn-on resistance of the PMOS transistor 61 and the dummy cell M00 and is kept constant.

Subsequently, the signal NO_ACT1 is deactivated to the low level while the signal NO_ACT2 is activated to the high level as shown in FIG. The second and third word line voltage generators 120b and 120c operate in the same manner as the first word line voltage generator 120a and generate voltages of (Vth2 + Voffset) and (Vth3 + Voffset), respectively. do. Operation descriptions of the generators 100b and 100c are omitted to avoid duplication of description. After three sensing operations are completed, the signal STG goes from low level to high level. This causes the node ND2 to become the ground voltage (0V), and as a result, the word line voltage generation circuit 13-2 is deactivated.

Here, it should be noted that the voltage VP, that is, the word line voltage is maintained at the voltage of (Vth1 / 3/3 + Voffset). This means that the gate-source voltage Vgs of the memory cell is fixed at the voltage Voffset during each sensing operation (meaning that the cell current flows constantly through the memory cell). Therefore, the data read operation can be reliably performed.

In the above-described second embodiment, the resistance values of the respective PMOS transistors 61 in the first to third word line voltage generators 120a, 120b, and 120c have the same sensing margin as each other during each sensing operation. Is set to. However, it is apparent to those skilled in the art that the sensing margins may be set differently in each sensing operation by setting the turn-on resistance values of the PMOS transistors 61 differently.

FIG. 8 is a circuit diagram of a word line voltage generator circuit 13-3 for use in the semiconductor memory device 1 of FIG. 3 according to the third preferred embodiment of the present invention. In Fig. 8, the same components as those in Fig. 5 are denoted by the same reference numerals. The third embodiment has two resistors (R0, R1), (R0, R2) in which the capacitors of each of the generators 100a, 100b, and 100c of FIG. 5 are each connected as shown in FIG. And the voltage dividers 160a, 160b, and 160c constituted of (R0, R3) and one NMOS transistor 62, and differ from the first embodiment. Each NMOS transistor 62 of the voltage dividers 160a, 160b and 160c is switched on / off in accordance with corresponding signals NO_ACT1, NO_ACT2 and NO_ACT3. In the third embodiment, the resistors R0 of each of the voltage dividers 160a, 160b, and 160c have the same value, and the resistors R1, R2, and R3 have different resistance values. Have Like the circuit 13-1 of FIG. 5, the word line voltage generation circuit 13-3 also operates in accordance with the timing diagram of FIG.

The operation of the word line voltage generation circuit 13-3 according to the third embodiment will be described below with reference to Figs.

When the voltage VP, that is, the word line voltage to be supplied to the selected memory cell is not generated from the word line voltage generation circuit 13-3, as shown in Fig. 6, the signal STG is in a high level state. And the signals NO_ACT1, NO_ACT2 and NO_ACT3 are in a low level state. This causes transistors 51 and 56 to be electrically conductive and transistor 57 is not electrically conductive, as a result node 5H is charged up to voltage VCC / VPP through PMOS transistor 51. As a result, the current path of the PMOS transistor 53 does not occur. At this time, the node ND3 is initialized to a low level, that is, 0V through the NMOS transistor 59 switched on by the signal STG. As in the first embodiment, there is no current consumed by the word line voltage generators 140a, 140b, and 140c when no data read operation is performed, which means that no current path of the transistor 57 is formed. Because it does not.

If the data read operation starts, as shown in Fig. 6, the signal STG goes from the high level to the low level, and the signal NO_ACT1 goes to the high level. At the same time, the signals NO_ACT2 and NO_ACT3 continue to be at a low level. This causes the first word line voltage generator 140a to be activated and the second and third word line voltage generators 140b and 140c to be deactivated. The PMOS transistor 51 of the first word line voltage generator 140a is deactivated and its NMOS transistor 57 is activated according to the activated signal NO_ACT1, so that node 5H is connected to NMOS transistors ( Discharge through 56) and (57).

After a predetermined time has elapsed, that is, when the gate potential of the PMOS transistor 53 becomes the ground voltage, the potential of the node ND3 is gradually increased to the required word line voltage. As the potential of the node ND3 increases, the gate potential of the dummy cell M00 also increases through the voltage divider 160a to the potential of the node ND3. However, since the output voltage of the voltage divider 160a is lower than the voltage of the node ND3, the dummy cell M00 even if the node ND3 voltage reaches the threshold voltage Vth1 of the dummy cell M00. Is not challenged.

As the potential of the node ND3 continues to increase, the gate voltage of the dummy cell M00 is equal to or higher than the threshold voltage Vth1 of the dummy cell M00, so that the node 5F voltage becomes higher. It is lowered below the threshold voltage of the transistor 56. As a result, the NMOS transistor 56 is turned off, and the node 5H becomes the voltage of (VCC / VPP-Vtp) (Vtp is the threshold voltage of the transistor 52), and the PMOS transistor 53 Is turned off. That is, the detection circuit 150a detects whether or not current flows through the dummy cell M00, and then supplies current to the node ND3 according to the detection result. Therefore, the voltage VP, that is, the word line voltage WL0 is set to a voltage of (Vth1 + Voffset). The voltage Voffset represents a sensing margin as the gate-source voltage Vgs of the memory cell. The voltage Voffset is determined by the resistance ratio between the resistors R0 and R1 and remains constant.

Subsequently, the signal NO_ACT1 is deactivated to the low level while the signal NO_ACT2 is activated to the high level as shown in FIG. The second and third word line voltage generators 140b and 140c operate in the same manner as the first word line voltage generator 140a and generate voltages of (Vth2 + Voffset) and (Vth3 + Voffset), respectively. do. Operational descriptions of the generators 140b and 140c are omitted to avoid duplication of description. After three sensing operations are completed, the signal STG goes from low level to high level. This causes the node ND3 to be the ground voltage (0V), and as a result, the word line voltage generation circuit 13-3 is inactivated.

Here, it should be noted that the voltage VP, that is, the word line voltage is maintained at the voltage of (Vth1 / 3/3 + Voffset). This means that the gate-source voltage Vgs of the memory cell is fixed at the voltage Voffset during each sensing operation (meaning that the cell current flows constantly through the memory cell). Therefore, the data read operation can be reliably performed.

In the above-described second embodiment, the values of the resistors R1, R2, and R3 in the first to third word line voltage generators 140a, 140b, and 140c are the sensing margins, respectively. It is set to be equal to each other during the sensing operation. However, it is apparent to those skilled in the art that the sensing margin can be set differently in each sensing operation by changing the resistance values of the resistors R1, R2 and R3.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

As described above, as the word line voltage is maintained at a voltage of (Vth1 / 3/3 + Voffset), the gate-source voltage of the memory cell is fixed to the voltage Voffset during each sensing operation. That is, cell current flows constantly through the memory cell. Therefore, the data read operation can be reliably performed.

Claims (47)

At least one memory cell having one threshold voltage among the plurality of threshold voltages and storing multi-bit data; At least one word line coupled to the memory cell; Means for sequentially generating other word line voltages to be applied to the word line when data is read from the memory cell during a data read operation, And when the threshold voltage or other word line voltages of the memory cell change, the other word line voltages are automatically adjusted by the means such that the gate-source voltage of the memory cell remains constant. The method of claim 1, The means includes: an output terminal for outputting the other word line voltages; And a plurality of word line voltage generators commonly connected to the output terminal, the plurality of word line voltage generators generating the other word line voltages to maintain a constant current flowing through the memory cell when the memory cell is in a conductive state. The method of claim 2, The means additionally comprises a reset transistor coupled between the output terminal and a ground voltage, the reset transistor being switched on before and after the data read operation. The method of claim 2, Each word line voltage generator, A dummy cell having a gate connected to the output terminal, a grounded one current electrode and another current electrode receiving a reference voltage, the dummy cell being set to one of the threshold voltages of the memory cell; A coupling capacitor coupled between the gate of the dummy cell and the output terminal; And a detection circuit connected to one current electrode of the dummy cell and detecting whether the dummy cell is conductive and supplying current to the output terminal according to a detection result. The method of claim 4, wherein Each word line voltage generator further comprises a reset transistor coupled between the gate and ground voltages of the dummy cell and switched on before and after the data read operation. The method of claim 5, Wherein each word line voltage generator further comprises a PMOS transistor having a grounded gate, one current electrode receiving the reference voltage, and another current electrode connected to another current electrode of the dummy cell. The method of claim 6, And the current driving capability of the PMOS transistor is smaller than that of the dummy cell. The method of claim 4, wherein And the coupling capacitors of the word line voltage generators have the same value so that the cell current amount of the memory cell is equal to each other during each sensing period of the data read operation. The method of claim 4, wherein And the coupling capacitors of the word line voltage generators are set differently so that the cell current amount of the memory cell is different during each sensing period of the data read operation. The method of claim 2, Each word line voltage generator, A dummy cell having a gate connected to the output terminal, a grounded one current electrode and another current electrode receiving a reference voltage, the dummy cell being set to one of the threshold voltages of the memory cell; A resistance element connected between the other current electrode of the dummy cell and the reference voltage; And a detection circuit connected to another current electrode of the dummy cell and one end of the resistance element, and detecting whether the dummy cell is conductive and supplying current to the output terminal according to the detection result. The method of claim 10, And the resistor element comprises a PMOS transistor having a current path and a grounded gate formed between the reference voltage and another current electrode of the dummy cell. The method of claim 11, And the current driving capability of the dummy cell is smaller than that of the PMOS transistor. The method of claim 12, And the values of the resistance elements of the word line voltage generators are equally set such that the cell current amount of the memory cell is equal to each other during each sensing period of the data read operation. The method of claim 12, And the values of the resistance elements of the word line voltage generators are set differently so that the cell current amount of the memory cell is different during each sensing period of the data read operation. The method of claim 2, Each word line voltage generator, A dummy cell having a gate connected to the output terminal, a grounded one current electrode and another current electrode receiving a reference voltage, the dummy cell being set to one of the threshold voltages of the memory cell; A voltage divider connected between the gate of the dummy cell and the output terminal and distributing a voltage of the output terminal to supply the divided voltage to the gate of the dummy cell; And a detection circuit connected to another current electrode of the dummy cell and detecting whether the dummy cell is conductive and supplying current to the output terminal according to a detection result. The method of claim 15, Wherein each word line voltage generator further comprises a PMOS transistor having a grounded gate, one current electrode receiving the reference voltage, and another current electrode connected to another current electrode of the dummy cell. The method of claim 16, And said PMOS transistor current driving capability is less than that of said dummy cell. The method of claim 16, The voltage divider, A first resistor element having one end connected to the output terminal and the other end connected to a gate of the dummy cell; And a second resistance element having one end connected to the gate of the dummy cell and the other end of the first resistance element and the other end grounded. The method of claim 18, And a first resistor element of each word line voltage generator having the same value, and a second resistor element having different values. The method of claim 19, The voltage divider further comprises a transistor connected between the other end of the second resistor element and a ground voltage and switched on only during a corresponding sensing period. The method according to claim 4, 11 or 15, The detection circuit, A first PMOS transistor having a source connected to a power supply voltage and a gate and a drain connected to each other; A second PMOS transistor having a source connected to the power supply voltage, a gate connected to the gate of the first PMOS transistor, and a drain connected to the output terminal; A third PMOS transistor having a source connected to the power supply voltage, a drain connected to the drain of the first PMOS transistor, and a gate receiving the selection signal; A first NMOS transistor having a drain connected to the drain of the first PMOS transistor, a gate and a source connected to the reference voltage and another current electrode of the dummy cell; A second NMOS transistor having a drain connected to the source of the first NMOS transistor, a grounded source, and a gate receiving the selection signal, And the first and second PMOS transistors function as current mirror circuits. A plurality of memory cells arranged in rows and columns each storing multi-bit data representing at least two bits of information and having a gate and a current path; A plurality of word lines connected to gates of the memory cells; A row decoder circuit coupled to the word lines and selecting one of the word lines in accordance with an address signal; A word line voltage generation circuit coupled to said row decoder circuit for generating other word line voltages to be applied to said selected word line when data is read from a selected memory cell during a data read operation, When the threshold voltage or other word line voltages of the memory cell are changed, the other word line voltages are automatically adjusted by the means such that the gate-source voltage of the memory cell remains constant; And The word line voltage generation circuit includes an output terminal for outputting the other word line voltages; A plurality of word line voltage generators for generating said different word line voltages, respectively; A reference voltage generator commonly connected to each of the word line voltage generators; And a first reset transistor connected to the output terminal and a ground voltage and switched on before and after a data read operation. The method of claim 22, Each word line voltage generator, A dummy cell having a gate connected to the output terminal, a grounded one current electrode, and another current electrode connected to the reference voltage generator, the dummy cell being set to one of the threshold voltages of each memory cell; A coupling capacitor connected between the gate of the dummy cell and the output terminal; A detection circuit connected to another current electrode of the dummy cell, detecting whether the dummy cell is conductive and supplying current to the output terminal according to a detection result; And a second reset transistor connected between the gate of the dummy cell and a ground voltage and switched on before and after the data read operation. The method of claim 23, Each word line voltage generator additionally includes a PMOS transistor having a grounded gate, one current electrode connected to the reference voltage generator, and another current electrode connected to another current electrode of the dummy cell, wherein the driving capability of the PMOS transistor is provided. Is smaller than that of the dummy cell. The method of claim 24, And the coupling capacitors of the word line voltage generators have the same value so that the cell current amount of the memory cell is equal to each other during each sensing period of the data read operation. The method of claim 24, And the coupling capacitors of the word line voltage generators are set differently so that the cell current amount of the memory cell is different during each sensing period of the data read operation. The method of claim 22, Each word line voltage generator, A dummy cell having a gate connected to the output terminal, a grounded one current electrode, and another current electrode connected to the reference voltage generator, the dummy cell being set to one of the threshold voltages of each memory cell; A resistance element connected between the other current electrode of the dummy cell and the reference voltage generator; And a detection circuit connected to another current electrode of the dummy cell and the resistance element, and detecting whether the dummy cell is conductive and supplying current to the output terminal according to a detection result. The method of claim 27, The resistor element comprises a transistor having a current path and a grounded gate formed between the reference voltage generator and another current electrode of the dummy cell, wherein the current driving capability of the dummy cell is smaller than that of the transistor. . The method of claim 28, And the values of the resistance elements of the word line voltage generators are equally set such that the cell current amount of the memory cell is equal to each other during each sensing period of the data read operation. The method of claim 28, And the values of the resistance elements of the word line voltage generators are set differently so that the cell current amount of the memory cell is different during each sensing period of the data read operation. The method of claim 22, Each word line voltage generator, A dummy cell having a gate connected to the output terminal, a grounded one current electrode, and another current electrode connected to a reference voltage generator, the dummy cell being set to one of the threshold voltages of the memory cell; A voltage divider connected between the gate of the dummy cell and the output terminal and distributing a voltage of the output terminal to supply the divided voltage to the gate of the dummy cell; And a detection circuit connected to another current electrode of the dummy cell and detecting whether the dummy cell is conductive and supplying current to the output terminal according to a detection result. The method of claim 31, wherein Each word line voltage generator additionally includes a PMOS transistor having a grounded gate, one current electrode connected to the reference voltage generator, and another current electrode connected to another current electrode of the dummy cell, wherein the PMOS transistor current driving capability Is smaller than that of the dummy cell. The method of claim 32, The voltage divider, A first resistor element having one end connected to the output terminal and the other end connected to a gate of the dummy cell; A second resistance element having one end connected to the gate of the dummy cell and the other end of the first resistance element and the other end grounded; And an NMOS transistor connected between the other end of the second resistance element and a ground voltage and switched on only during a corresponding sensing period. The method of claim 33, wherein And a first resistor element of each word line voltage generator having the same value, and a second resistor element having different values. The method of claim 23, 27 or 31, The detection circuit includes a first PMOS transistor having a source connected to a power supply voltage, and a gate and a drain connected to each other; A second PMOS transistor having a source connected to the power supply voltage, a gate connected to the gate of the first PMOS transistor, and a drain connected to the output terminal; A third PMOS transistor having a source connected to the power supply voltage, a drain connected to the drain of the first PMOS transistor, and a gate receiving the selection signal; A first NMOS transistor having a drain connected to the drain of the first PMOS transistor, a gate and a source connected to the reference voltage and another current electrode of the dummy cell; And a second NMOS transistor having a drain connected to the source of the first NMOS transistor, a grounded source, and a gate receiving the selection signal, wherein the first and second PMOS transistors function as current mirror circuits. . A plurality of memory cells arranged in rows and columns each storing multi-bit data representing at least two bits of information and having a gate and a current path; A plurality of word lines connected to gates of the memory cells; A row decoder circuit coupled to the word lines and selecting one of the word lines in accordance with an address signal; A word line voltage generation circuit coupled to said row decoder circuit for generating other word line voltages to be applied to said selected word line when data is read from a selected memory cell during a data read operation; The word line voltage generation circuit includes an output terminal for outputting the other word line voltages; A plurality of word line voltage generators for generating said different word line voltages, respectively; A first reset transistor coupled to the output terminal and a ground voltage and switched on before and after a data read operation; And Each word line voltage generator having a gate connected to the output terminal, a grounded one current electrode, and another current electrode to receive the reference voltage, the dummy cell being set to one of the threshold voltages of each memory cell; A coupling capacitor connected between the gate of the dummy cell and the output terminal; A detection circuit connected to another current electrode of the dummy cell, detecting whether the dummy cell is conductive and supplying current to the output terminal according to a detection result; And a second reset transistor connected between the gate of the dummy cell and a ground voltage and switched on before and after the data read operation. The method of claim 36, Each word line voltage generator additionally includes a PMOS transistor having a grounded gate, one current electrode receiving the reference voltage, and another current electrode connected to another current electrode of the dummy cell, wherein the PMOS transistor has a driving capability. Is smaller than that of the dummy cell. The method of claim 37, And the coupling capacitors of the word line voltage generators have the same value so that the cell current amount of the memory cell is equal to each other during each sensing period of the data read operation. The method of claim 37, And the coupling capacitors of the word line voltage generators are set differently so that the cell current amount of the memory cell is different during each sensing period of the data read operation. A plurality of memory cells arranged in rows and columns each storing multi-bit data representing at least two bits of information and having a gate and a current path; A plurality of word lines connected to gates of the memory cells; A row decoder circuit coupled to the word lines and selecting one of the word lines in accordance with an address signal; A word line voltage generation circuit coupled to said row decoder circuit for generating other word line voltages to be applied to said selected word line when data is read from a selected memory cell during a data read operation, The word line voltage generation circuit includes an output terminal for outputting the other word line voltages; A plurality of word line voltage generators for generating said different word line voltages, respectively; A reset transistor coupled to the output terminal and a ground voltage and switched on before and after a data read operation; And Each word line voltage generator having a gate connected to the output terminal, a grounded one current electrode, and another current electrode for receiving a reference voltage, the dummy cell being set to one of the threshold voltages of each memory cell; A resistance element connected between the other current electrode of the dummy cell and the reference voltage; And a detection circuit connected to the other current electrode of the dummy cell and the resistance element, and detecting whether the dummy cell is conductive and supplying current to the output terminal according to a detection result. The method of claim 40, And the resistor element comprises a transistor having a current path and a grounded gate formed between the reference voltage and another current electrode of the dummy cell, wherein the current driving capability of the dummy cell is smaller than that of the transistor. 42. The method of claim 41 wherein And the values of the resistance elements of the word line voltage generators are equally set such that the cell current amount of the memory cell is equal to each other during each sensing period of the data read operation. The method of claim 42, And the values of the resistance elements of the word line voltage generators are set differently so that the cell current amount of the memory cell is different during each sensing period of the data read operation. A plurality of memory cells arranged in rows and columns each storing multi-bit data representing at least two bits of information and having a gate and a current path; A plurality of word lines connected to gates of the memory cells; A row decoder circuit coupled to the word lines and selecting one of the word lines in accordance with an address signal; A word line voltage generation circuit coupled to said row decoder circuit for generating other word line voltages to be applied to said selected word line when data is read from a selected memory cell during a data read operation, The word line voltage generation circuit includes an output terminal for outputting the other word line voltages; A plurality of word line voltage generators for generating said different word line voltages, respectively; A reset transistor coupled to the output terminal and a ground voltage and switched on before and after a data read operation; And Each word line voltage generator having a gate connected to the output terminal, a grounded one current electrode and another current electrode for receiving a reference voltage, the dummy cell being set to one of the threshold voltages of the memory cell; A voltage divider connected between the gate of the dummy cell and the output terminal and distributing a voltage of the output terminal to supply the divided voltage to the gate of the dummy cell; And a detection circuit connected to another current electrode of the dummy cell and detecting whether the dummy cell is conductive and supplying current to the output terminal according to a detection result. The method of claim 31, wherein Each word line voltage generator additionally includes a PMOS transistor having a grounded gate, one current electrode receiving the reference voltage, and another current electrode connected to another current electrode of the dummy cell, wherein the PMOS transistor current driving capability Is smaller than that of the dummy cell. The method of claim 32, The voltage divider includes: a first resistor element having one end connected to the output terminal and the other end connected to a gate of the dummy cell; A second resistance element having one end connected to the gate of the dummy cell and the other end of the first resistance element and the other end grounded; And a transistor connected between the other end of the second resistance element and a ground voltage and switched on only during a corresponding sensing period. The method of claim 46, And a first resistor element of each word line voltage generator having the same value, and a second resistor element having different values.