KR19980037415A - High Voltage Generation Circuit of Nonvolatile Semiconductor Memory Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. Specifically, a high voltage generation of a semiconductor memory device for generating a plurality of desired high voltages using one pumping circuit without using a high voltage pumping circuit each required to obtain required high voltage levels. The present invention relates to a circuit, comprising: a charge pump unit for outputting a high voltage of a highest level among a plurality of high voltage levels required in response to a clock signal and a high voltage enable signal having a predetermined period applied from the outside; A switch charge pumping means for receiving the high voltage output from the charge pumping unit and outputting a high voltage in response to the clock signal, a first signal applied from the outside, and a predetermined second signal, and from the switch charge pumping means A plurality of high voltage generators are configured to receive the output high voltage and detect the output signal of the second signal input to the switch charge pumping means when the level of the high voltage is higher than a predetermined voltage level. As a result, when a plurality of high voltage levels are required, a high integration is achieved by minimizing the chip area occupied by the high voltage generation circuit by realizing the generation of a plurality of high voltage levels using one high voltage generator without using each high voltage generation circuit. Can be realized.

Description

A high voltage generation circuit of a nonvolatile semiconductor memory device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. Specifically, a high voltage generation of a semiconductor memory device for generating a plurality of desired high voltages using one pumping circuit without using a high voltage pumping circuit each required to obtain required high voltage levels. It is about a circuit.

The semiconductor memory device requires voltages other than the power supply voltage according to its operation. In general, the semiconductor memory device may be divided into a reference voltage lower than the power supply voltage and a high voltage higher than the power supply voltage. In particular, in the nonvolatile semiconductor memory, a high voltage higher than a power supply voltage is necessary to perform an erase or write operation of data. Typically, a cell array for storing data in a nonvolatile semiconductor memory device is composed of a plurality of strings, although not shown in the figure. Each string includes a predetermined number of memory cell transistors connected in series between a first select transistor connected to a first select line and a second select transistor connected to a second select line. A bit line is connected to each drain terminal of each of the first select transistors. Here, the bit line corresponding to the first string is referred to as the first bit line, and the bit line corresponding to the second string is referred to as the second bit line. Corresponding word lines are connected to the control gate terminals of the memory cell transistors in the strings, respectively. Each of the memory cell transistors has a source and a drain region formed with a channel between the semiconductor substrate and the semiconductor substrate. A gate oxide film, a floating gate, an ONO film, and a control gate are sequentially formed over a portion of the source and drain regions over the channel.

However, according to the conventional high voltage generation circuit, the high voltages require respective high voltage generation circuits to generate a plurality of voltages. As a result, when all the required high voltage generation circuits are implemented in the semiconductor memory device, a problem arises in that the chip area occupied by the high voltage generation circuits is increased and high integration cannot be realized.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, and the pumping circuit is generated by generating a plurality of desired high voltages using one pumping circuit, without using a high voltage pumping circuit each required to obtain required high voltage levels. It is an object of the present invention to provide a high voltage generation circuit of a semiconductor memory device capable of realizing high integration by reducing the area occupied.

1 is a block diagram showing a configuration of a high voltage generation circuit of a nonvolatile semiconductor memory device according to the present invention;

2 is an operation timing diagram according to a preferred embodiment of the present invention;

3 is a circuit diagram showing a detailed circuit of a switch charge pumping means according to a preferred embodiment of the present invention;

4 is a circuit diagram showing a detailed circuit of a voltage detecting means according to a preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

100: charge pumping unit 200: high voltage generating unit

210: switch charge pumping means 220: detection means

According to one aspect of the present invention for achieving the above object, in response to a clock signal and a high voltage enable signal having a predetermined period applied from the outside, a high voltage of the highest level among a plurality of high voltage levels required A charge pumping unit for outputting; A switch charge pumping means for receiving the high voltage output from the charge pumping unit and outputting a high voltage in response to the clock signal, a first signal applied from the outside, and a predetermined second signal, and from the switch charge pumping means And a plurality of high voltage generators configured to receive the output high voltage and output the second signal input to the switch charge pumping means when the level of the high voltage is higher than a predetermined voltage level.

In this embodiment, the switch charge pumping means is composed of a plurality of NAND gates, an inverter, a coupling capacitor, and a plurality of NMOS transistors.

In this embodiment, the detecting means comprises: comparing means for receiving a reference voltage and a predetermined distribution voltage applied from the outside and outputting a comparison signal comparing the same; Voltage dividing means for receiving the high voltage output from the switch charge pumping means and outputting the divided voltage converted to the reference voltage level; And an output means for amplifying and outputting the comparison signal output from the comparison means.

In this embodiment, the comparing means is composed of a plurality of PMOS transistors and NMOS transistors.

In this embodiment, the voltage distribution means is composed of resistors.

In this embodiment, the output means consists of a plurality of inverters.

By such a circuit, it is possible to realize high integration by reducing the area occupied by the pumping circuit by generating a plurality of desired high voltages by using one pumping circuit instead of using the high voltage pumping circuit each required to obtain the required high voltage levels. It became.

Hereinafter, reference will be made in detail with reference to FIGS. 1 to 4 according to an embodiment of the present invention.

1 is a block diagram showing a configuration of a high voltage generation circuit of a nonvolatile semiconductor memory device according to the present invention.

The high voltage generation circuit according to the present invention shown in FIG. 1 includes a charge pumping unit 100 and a plurality of high voltage generation units 200. The charge pumping unit 100 receives a high voltage HVmout of the highest level among a plurality of required high voltage levels in response to a clock signal ψ hv and a high voltage enable signal HVen having a predetermined period applied from the outside. Output Each of the high voltage generators 200 includes a switch charge pumping means 210 and a detection means 220. The switch charge pumping unit 210 receives the high voltage HVmout output from the charge pumping unit 100, the clock signal ψ hv, an enable signal HVSi applied from the outside, and a predetermined de-energization signal. The high voltage HVi is output in response to the sable signal DISi. The detection means 220 receives the high voltage HVi output from the switch charge pumping means 210, and the switch charge pumping when the level of the high voltage HVi is higher than a predetermined voltage level. The disable signal DISi input to the means 210 is output.

2 is an operation timing diagram according to a preferred embodiment of the present invention.

3 shows a switch charge pump circuit according to a preferred embodiment of the present invention. The switch charge pump circuit 210 illustrated in FIG. 3 receives the high voltage HVmout output from the charge pumping unit 100 of FIG. 2 and has control signals DISi and HVSi applied from the outside and a predetermined period. The high voltage is output in response to the clock signal .phi.v. In addition, the switch charge pump circuit 210 includes first and second NAND gates 220 and 222, an inverter 221, a coupling capacitor C, and a plurality of NMOS transistors 233 to 256. .

4 shows a voltage detection circuit according to a preferred embodiment of the present invention.

As shown in FIG. 4, the voltage detection circuit 220 receives a high voltage output from the switch charge pumping circuit 210 shown in FIG. 3, and when the level of the high voltage is higher than a predetermined voltage level. The disable signal DISi is output to the switch charge pump circuit 210 to disable the pumping operation of the switch charge pump circuit 210. In addition, the voltage detection circuit 220 is composed of a comparison means 270, a voltage distribution means 280, and an output means 290. The comparison means 270 receives a reference voltage Vref and a distribution voltage V_div output from the voltage distribution means 280, and outputs a comparison signal S_com comparing the voltage levels thereof. That is, when the reference voltage Vref is higher than the distribution voltage V_div, the comparison means 270 outputs a high level comparison signal S_com. On the other hand, when the reference voltage Vref is at a level lower than the division voltage V_div, the comparison means 270 outputs the comparison signal S_com having a low level.

Here, the comparing means 270 is PMOS transistors 259 and 260 operating as load transistors and NMOS transistors 257 and 258 enabled in response to the reference voltage Vref and the distribution voltage V_div, respectively. And an NMOS transistor 261 for uniformly flowing a current transmitted through the NMOS transistors 257 and 258. The distribution means 280 receives the high voltage HV output from the switch charge pump circuit 210 shown in FIG. 3 and outputs the distribution voltage V_div converted to the reference voltage level. The distribution means 280 includes resistors 262 and 263 connected in series between the line to which the high voltage is applied and the ground terminal to which the ground voltage VSS is applied. The output means 290 amplifies the comparison signal S_com output from the comparison means 270 and outputs the disable signal DISi to the switch charge pump circuit 210 shown in FIG. 3.

Hereinafter, an operation according to the present invention will be described with reference to FIGS. 1 to 4.

First, when the activation signal HVen of the charge pumping unit 100 transitions from the low level to the high level, the output HVmout of the charge pumping unit 100 is generated by the charge pump clock signal ψhv which oscillates with a certain period. It is the highest voltage level among the required high voltages. Here, the detailed operation of the charge pumping unit 100 will be omitted. Subsequently, an activation signal of the plurality of switch charge pumping means 210 connected in parallel to the output of the charge pumping unit 100 (assuming that CPsub1 is activated for convenience of description) 'HVsub1' is at a low level. When the transition to the high level the switch charge pumping means 210 is activated. The output voltage HVmout of the charge pumping unit 100 is transmitted to the output HV1 of the switch charge pumping unit 210 through the switch charge pumping unit 210 to increase the voltage level of the output HV1. .

When the output HV1 of the switch charge pumping means 210 rises to a certain high voltage level, the disable signal DIS1 is low from the high level from the detection means 220 connected to the output terminal of the switch charge pumping means 210. Transition to level. As a result, the switch charge pumping means 210 is deactivated to prevent the output HV1 of the switch charge pumping means 210 from being above a certain high voltage level. That is, the distribution voltage V_div corresponding to the high voltage HV1 outputted to the switch charge pumping means 210 through the distribution means 280 of the detection means 220 is converted to the reference voltage Vref level. Output At this time, when the converted divided voltage is higher than the reference voltage level, the comparison means 270 outputs a low level comparison signal S_com. In addition, the output means 290 amplifies the comparison signal S_com and outputs it to the switch charge pumping means 210 so that the charge pumping means 210 is disabled and no pumping operation is performed anymore.

Thereafter, when the output HV1 of the switch charge pumping means 210 falls below a predetermined high voltage level, the disable signal DIS1 of the detection means 220 for detecting the output of the switch charge pumping means 210 is low. Output from level to high level. As a result, the switch charge pumping means 210 is activated again to bring the output HV1 of the switch charge pumping means 210 to a constant high voltage level. This operation is repeated to maintain the output HV1 of the switch charge pumping means 210 at a constant high voltage level. When a plurality of high voltage levels are required, the switch charge pumping means 210 according to the present invention may be operated in the above manner to generate a plurality of high voltages.

As described above, the chip area occupied by the high voltage generation circuit is realized by implementing a plurality of high voltage levels by using a single high voltage generator without using each high voltage generation circuit when a plurality of high voltage levels are required. By minimizing, high integration can be realized.

Claims (6)

The charge pumping unit 100 outputs the highest voltage HVmout of the plurality of required high voltage levels in response to the clock signal ψ hv and the high voltage enable signal HVen having a predetermined period applied from the outside. Wow; In response to the high voltage HVmout output from the charge pumping unit 100, the clock signal ψhv, a first signal HVSi applied from the outside, and a predetermined second signal DISi are responded to. Switch charge pumping means 210 for outputting (HVi), Receiving the high voltage (HVi) output from the switch charge pumping means 210, when the level of the high voltage (HVi) is higher than the predetermined voltage level is input to the switch charge pumping means 210 A high voltage generation circuit of a nonvolatile semiconductor memory device including a plurality of high voltage generation units (200) comprising detection means (220) for outputting two signals (DISi). The method of claim 1, The switch charge pumping means 210 includes a plurality of NAND gates 220 and 222, an inverter 221, a coupling capacitor C, and a plurality of NMOS transistors 233 to 256. High voltage generator circuit. The method of claim 1, The detection means 220 includes a comparison means 270 for receiving a reference voltage Vref and a predetermined distribution voltage V_div applied from the outside and outputting a comparison signal S_com comparing the received voltage; A voltage dividing means (280) for receiving the high voltage output from the switch charge pumping means (210) and outputting the divided voltage (V_div) converted to the reference voltage level; A high voltage generation circuit of a nonvolatile semiconductor memory device comprising an output means (290) for amplifying and outputting the comparison signal (S_com) output from the comparison means (270). The method of claim 3, wherein The comparing means (270) is a high voltage generation circuit of a nonvolatile semiconductor memory device consisting of a plurality of PMOS transistors (259, 260) and NMOS transistors (257, 258, 261). The method of claim 3, wherein The voltage dividing means (280) is a high voltage generation circuit of a nonvolatile semiconductor memory device consisting of resistors (262, 263). The method of claim 3, wherein The output means (290) is a high voltage generation circuit of a nonvolatile semiconductor memory device consisting of a plurality of inverters (264, 265).