KR102656430B1 - Shift Register and Display Device Using the same - Google Patents

Abstract

The present invention provides a display device including a display panel and a shift register. The display panel displays images. The shift register supplies a gate signal to the display panel. The shift register has one input terminal and the other input terminal that receive signals and voltage supplied from the outside, a first circuit unit that charges and discharges the Q node in response to the signal and voltage, and a first circuit unit that charges the QB node in response to the potential of the Q node. A second circuit unit that discharges, a third circuit unit that receives at least one clock signal from the outside and sends out at least one clock signal as its output in response to the potential of the Q node, and sets the Q node to a potential lower than the potential of the QB node. It includes a compensation circuit unit that applies a voltage lower than 0 between the gate and source of the N-type thin film transistor constituting the first circuit unit when maintained at .

Description

Shift register and display device using the same {Shift Register and Display Device Using the same}

The present invention relates to a shift register and a display device using the same.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Accordingly, the use of display devices such as light emitting display (LED), liquid crystal display (LCD), and plasma display panel (PDP) is increasing.

Some of the display devices described above, such as liquid crystal displays and electroluminescence displays, include a display panel including a plurality of subpixels arranged in a matrix and a driver that drives the display panel. The driver includes a gate driver that supplies a gate signal (or scan signal) to the display panel and a data driver that supplies data signals to the display panel.

In the above display device, when gate signals and data signals are supplied to subpixels arranged in a matrix form, the selected subpixels emit light, allowing images to be displayed.

The gate driver that outputs the gate signal is divided into an external type that is mounted on the external substrate of the display panel in the form of an integrated circuit and an internal type that is formed in the display panel in the form of a gate in panel (GIP) made with a thin film transistor process.

The built-in gate driver sequentially outputs gate signals based on dependently connected shift registers. Since the shift register is made up of multiple thin film transistors, it is affected by the voltage continuously applied to the gate electrode. For example, when a negative voltage is continuously received, the threshold voltage moves in the negative (-) direction.

In the conventional structure, when turning off the N-type thin film transistor that charges and discharges the Q node, a logic low voltage is applied to the gate node. When the Q node potential is logic low, the gate source voltage (Vgs) is necessarily 0. If the threshold voltage of a thin film transistor is negative, it cannot be completely turned off. For this reason, unless the leakage current problem caused by the threshold voltage shift of the thin film transistor is not supplemented or compensated for, charging and discharging of the Q node does not occur normally. And due to this effect, an error may occur in which the shift register cannot properly output the gate signal. Ultimately, this problem requires improvement as it can be a factor that prevents the display device from operating normally.

The present invention to solve the problems of the background technology described above is to ensure that the Q node is charged and discharged normally and to output a gate signal in one direction or two directions under stable driving conditions. In addition, the present invention improves the driving reliability of the display device by setting and maintaining stable driving conditions even if the threshold voltage of the thin film transistor changes.

As a means of solving the above-described problem, the present invention provides a display device including a display panel and a shift register. The display panel displays images. The shift register supplies a gate signal to the display panel. The shift register has one input terminal and the other input terminal that receive signals and voltage supplied from the outside, a first circuit unit that charges and discharges the Q node in response to the signal and voltage, and a first circuit unit that charges the QB node in response to the potential of the Q node. A second circuit unit that discharges, a third circuit unit that receives at least one clock signal from the outside and sends out at least one clock signal as its output in response to the potential of the Q node, and sets the Q node to a potential lower than the potential of the QB node. It includes a compensation circuit unit that applies a voltage lower than 0 between the gate and source of the N-type thin film transistor constituting the first circuit unit when maintained at .

The compensation circuit may include a compensation capacitor that receives voltages of two different levels applied from the outside at both ends to provide a compensation voltage.

The compensation circuit unit includes a first compensation transistor that transmits a ground voltage to one end of the first compensation capacitor and a 1b compensation transistor that transmits a first low potential voltage to the other end of the first compensation capacitor, and a second compensation unit. and a second compensation unit including a 2a compensation transistor for transferring a ground voltage to one end of the compensation capacitor and a 2b compensation transistor for transferring a first low potential voltage to the other end of the second compensation capacitor, wherein the first low potential voltage is It may be a first negative voltage that is lower than the ground voltage.

The compensation circuit unit includes a 1a compensation transistor with a gate electrode connected to a reset signal line, a first electrode connected to a ground voltage line, and a second electrode connected to the first output terminal of the N-k (k is an integer greater than 1) stage circuit unit; A 1b compensation transistor with a gate electrode connected to the reset signal line, a first electrode connected to the first low potential voltage line, and a second electrode connected to one input terminal of the first circuit part of the N stage circuit part, and an N-k (k is an integer greater than or equal to 1) a first compensation capacitor with one end connected to the first output terminal of the stage circuit part and the other end connected to one input terminal of the first circuit part of the N-th stage circuit part, a gate electrode connected to the reset signal line, and a ground voltage A 2a compensation transistor whose first electrode is connected to the line and whose second electrode is connected to the first output terminal of the N+k (k is an integer greater than 1) stage circuit part, and whose gate electrode is connected to the reset signal line and the first low A 2b compensation transistor with a first electrode connected to the potential voltage line and a second electrode connected to the other input terminal of the first circuit section of the N-th stage circuit section, and a first N+k (k is an integer greater than 1) stage circuit section It may include a second compensation capacitor with one end connected to the output terminal and the other end connected to the other input terminal of the first circuit part of the N-th stage circuit part.

The first circuit unit includes a 1a transistor whose gate electrode is connected to the second electrode of the 1b compensation transistor included in one side compensation part of the fifth circuit unit and the other end of the first compensation capacitor, and whose first electrode is connected to the forward high potential voltage line. , a 1b transistor whose gate electrode is connected to the gate electrode of the 1a transistor and whose first electrode is connected to the second electrode of the 1a transistor, a first electrode of the 2b compensation transistor included in the compensation unit on the other side of the 5th circuit unit, and A 2a transistor whose gate electrode is connected to the other end of the second compensation capacitor and whose first electrode is connected to the second electrode of the 1b transistor, and whose gate electrode is connected to the gate electrode of the 2a transistor and the second electrode of the 2a transistor It may include a 2b transistor in which a first electrode is connected and a second electrode is connected to a reverse high potential voltage line.

The second circuit unit has a gate electrode connected to the Q node, a first electrode connected to the high potential voltage line, and a third circuit unit whose second electrode is connected to the second electrode of the 1a transistor and the first electrode of the 1b transistor of the first circuit unit. A transistor, a fourth transistor having a first electrode connected to a high potential voltage line and a second electrode connected to the QB node, a gate electrode and a first electrode connected to a high potential voltage line, and a second electrode connected to the gate electrode of the fourth transistor. A fifth transistor with an electrode connected to it, a sixth transistor with a gate electrode connected to the Q node, a first electrode connected to the second electrode of the fifth transistor, and a second electrode connected to a second low-potential voltage line, and a Q node A seventh transistor with a gate electrode connected, a first electrode connected to the QB node, and a second electrode connected to a second low-potential voltage line, and a gate electrode to the first output terminal of the N-k (k is an integer greater than 1) stage circuit part. It may include an eighth transistor with a first electrode connected to the QB node and a second electrode connected to the second low-potential voltage line.

The third circuit unit has a gate electrode connected to the Q node, a first electrode connected to the first clock signal line, a ninth transistor whose second electrode is connected to the first output terminal of the N stage circuit unit, and one end connected to the Q node. The first boot capacitor has its other end connected to the first output terminal of the N-th stage circuit, its gate electrode is connected to the Q node, the first electrode is connected to the second clock signal line, and the other end is connected to the second output terminal of the N-th stage circuit. A 10th transistor with a second electrode connected to it, a second boot capacitor with one end connected to the Q node and the other end connected to the second output terminal of the N stage circuit unit, and a gate electrode connected to the Q node and a third clock signal line. An 11th transistor with a first electrode connected and a second electrode connected to the third output terminal of the N stage circuit part, and a third boot capacitor with one end connected to the Q node and the other end connected to the third output terminal of the N stage circuit part. may include.

The fourth circuit unit includes a 12a transistor with a gate electrode connected to the QB node and a first electrode connected to the Q node, a 12a transistor with a gate electrode connected to the QB node, a first electrode connected to the second electrode of the 12a transistor, and a second low electrode. A 12b transistor with a second electrode connected to the potential voltage line, a gate electrode connected to the QB node, a first electrode connected to the first output terminal of the N stage circuit unit, and a second electrode connected to the second low potential voltage line. A 13th transistor, a 14th transistor with a gate electrode connected to the QB node, a first electrode connected to the second output terminal of the N stage circuit unit, and a second electrode connected to the first low potential voltage line, and a gate to the QB node It may include a 15th transistor to which electrodes are connected, the first electrode is connected to the third output terminal of the N-th stage circuit unit, and the second electrode is connected to the first low-potential voltage line.

In another aspect, the present invention provides a shift register including a first circuit, a second circuit, a third circuit, and a compensation circuit. The first circuit unit has one input terminal and another input terminal that receive signals and voltages supplied from the outside, and charges and discharges the Q node in response to the signals and voltages. The second circuit unit charges and discharges the QB node in response to the potential of the Q node. The third circuit unit receives at least one clock signal from the outside and sends out at least one clock signal as its output in response to the potential of the Q node. The compensation circuit unit applies a compensation voltage lower than the threshold voltage of the thin film transistor constituting the first circuit unit to the gate electrode of the thin film transistor.

The compensation circuit may include a compensation capacitor that receives voltages of two different levels applied from the outside at both ends to provide a compensation voltage.

The compensation circuit unit includes a first compensation transistor that transmits a ground voltage to one end of the first compensation capacitor and a 1b compensation transistor that transmits a first low potential voltage to the other end of the first compensation capacitor, and a second compensation unit. and a second compensation unit including a 2a compensation transistor for transferring a ground voltage to one end of the compensation capacitor and a 2b compensation transistor for transferring a first low potential voltage to the other end of the second compensation capacitor, wherein the first low potential voltage is It may be a first negative voltage that is lower than the ground voltage.

The compensation circuit unit includes a 1a compensation transistor with a gate electrode connected to a reset signal line, a first electrode connected to a ground voltage line, and a second electrode connected to the first output terminal of the N-k (k is an integer greater than 1) stage circuit unit; A 1b compensation transistor with a gate electrode connected to the reset signal line, a first electrode connected to the first low potential voltage line, and a second electrode connected to one input terminal of the first circuit part of the N stage circuit part, and an N-k (k is an integer greater than or equal to 1) a first compensation capacitor with one end connected to the first output terminal of the stage circuit part and the other end connected to one input terminal of the first circuit part of the N-th stage circuit part, a gate electrode connected to the reset signal line, and a ground voltage A 2a compensation transistor whose first electrode is connected to the line and whose second electrode is connected to the first output terminal of the N+k (k is an integer greater than 1) stage circuit part, and whose gate electrode is connected to the reset signal line and the first low A 2b compensation transistor with a first electrode connected to the potential voltage line and a second electrode connected to the other input terminal of the first circuit section of the N-th stage circuit section, and a first N+k (k is an integer greater than 1) stage circuit section It may include a second compensation capacitor with one end connected to the output terminal and the other end connected to the other input terminal of the first circuit part of the N-th stage circuit part.

The present invention has the effect of supplementing or compensating for the problem of leakage current caused by the threshold voltage shift of the thin film transistor and ensuring normal charging and discharging of the Q node, allowing gate signals to be output in one direction or two directions under stable driving conditions. In addition, the present invention has the effect of improving the driving reliability of the display device by setting and maintaining stable driving conditions even if the threshold voltage of the thin film transistor changes.

1 is a schematic block diagram of a display device.
FIG. 2 is an exemplary configuration diagram of the subpixel shown in FIG. 1.
3 is a first example diagram of stage circuit portions arranged in a display panel.
Figure 4 is a second example diagram of stage circuit portions arranged in a display panel.
Figure 5 is a diagram schematically showing the N-th stage circuit unit according to the first embodiment of the present invention.
Figure 6 is a first example diagram showing a blocked part in Figure 5.
Figure 7 is a second example diagram showing the blocked portion in Figure 5.
Figure 8 is a simulation waveform diagram showing the output state when the compensation circuit part is removed from the N-th stage circuit part according to the second example.
Figure 9 is a diagram showing the N-th stage circuit unit in detail according to the second embodiment of the present invention.
Figures 10 to 16 are signal waveform diagrams for explaining the driving characteristics of each section of the N-th stage circuit unit.
17 to 19 are simulation waveform diagrams showing waveforms during first-direction scan, second-direction scan, and bidirectional scan driving.

Hereinafter, specific details for implementing the present invention will be described with reference to the attached drawings.

The display device according to the present invention can be implemented as a television, video player, personal computer (PC), home theater, smartphone, etc. The display device described below is implemented as a liquid crystal display (LCD), electroluminescent display (LED), or electrophoretic display (EPD). Electroluminescent displays are implemented based on organic light emitting diodes or inorganic light emitting diodes.

FIG. 1 is a schematic block diagram of a display device, and FIG. 2 is an exemplary configuration diagram of the subpixel shown in FIG. 1.

As shown in Figures 1 and 2, the display device includes a display panel 100, a timing control unit 110, a data driver 120, and gate drivers 130, 140B, and 140A.

The display panel 100 includes subpixels connected to data lines DL and gate lines GL that intersect each other. The display panel 100 includes a display area (AA) where subpixels are formed and a non-display area (LNA, RNA) where various signal lines or pads are formed outside the display area (AA).

One subpixel (SP) has a switching transistor (SW) connected to the first gate line (GL1) and the first data line (DL1) and a data signal supplied in response to the gate signal supplied through the switching transistor (SW) ( It includes a pixel circuit (PC) that operates in response to DATA). The subpixel (SP) is implemented as a liquid crystal display panel including a liquid crystal device or an organic light emitting display panel including an organic light emitting device, depending on the configuration of the pixel circuit (PC).

If the display panel 100 is composed of a liquid crystal display panel, it can be used in Twisted Nematic (TN) mode, Vertical Alignment (VA) mode, In Plane Switching (IPS) mode, Fringe Field Switching (FFS) mode, or Electrically Controlled Birefringence (ECB) mode. It is implemented in mode. For example, when the display panel 100 is composed of an organic light emitting display panel, it is implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

The timing control unit 110 receives timing signals such as a vertical synchronization signal, horizontal synchronization signal, data enable signal, and dot clock through an LVDS or TMDS interface reception circuit connected to the video board. The timing control unit 110 generates timing control signals to control the operation timing of the data driver 120 and the gate driver 130, 140B, and 140A based on the input timing signal.

The data driver 120 includes a plurality of source drive ICs (Integrated Circuits). The source drive ICs receive a data signal (DATA) and a source timing control signal (DDC) from the timing control unit 110. The source drive ICs convert the data signal (DATA) from a digital signal to an analog signal in response to the source timing control signal (DDC) and supply it through the data lines (DL) of the display panel 100. The source drive ICs may be connected to the data lines DL of the display panel 100 through a Chip On Glass (COG) process or a Tape Automated Bonding (TAB) process, but are not limited to this.

The gate drivers 130, 140B, and 140A include a level shifter 130 and shift registers 140B and 140A. The level shifter 130 is formed on an external substrate connected to the display panel 100 in the form of an IC. The level shifter 130 shifts the levels of signals and voltages supplied through the clock signal line, start signal line, high potential voltage line, and low potential voltage line under the control of the timing controller 11, and then registers the shift register (140B). , 140A).

The shift registers 140B and 140A are formed in the display panel 100 using a gate in panel (GIP) method. The shift registers 140B and 140A include stage circuits formed in the form of thin film transistors in the non-display area (LNA, RNA) of the display panel 100. Stage circuit units are formed separately in the left non-display area (LNA) and the right non-display area (RNA) of the display panel 100. There are multiple stage circuit units, from the first stage circuit unit to the Nth stage circuit unit (N is an integer greater than 10). The stage circuit units are connected in a dependent manner so that they can receive output signals from the stage circuit unit located at the top or bottom.

FIG. 3 is a first example diagram of stage circuit parts arranged in a display panel, and FIG. 4 is a second example diagram of stage circuit parts arranged in a display panel.

As shown in FIG. 3, the shift registers 140B and 140A are stage circuit units (GIPL1, GIPR1, It consists of GIPL2, GIPR2).

The method shown in FIG. 3 is a structure in which shift registers are placed on both sides of the display area AA to reduce signal delay due to line load of the gate line when implementing a display device with a large area and high resolution.

The first left stage circuit part GIPL1 and the first right stage circuit part GIPR1 are disposed facing each other on the first gate line GL1 of the display panel 110. The first gate line GL1 is prepared by the operation of the first left stage circuit unit GIPL1 disposed in the left non-display area (LNA) and the first right stage circuit unit GIPR1 disposed in the right non-display area (RNA). Transmits the gate signal.

The second left stage circuit part GIPL2 and the second right stage circuit part GIPR2 are disposed facing each other on the second gate line GL2 of the display panel 110. The second gate line GL2 is prepared by the operation of the second left stage circuit part GIPL2 arranged in the left non-display area (LNA) and the second right stage circuit part GIPR2 arranged in the right non-display area (RNA). Transmits the gate signal.

As shown in FIG. 4, the shift registers 140B and 140A are stage circuit units (GIPL1 and GIPL2) that shift and output gate signals in response to signals and voltages (e.g., clk, vst, etc.) supplied from the level shifter. It consists of

The method shown in FIG. 4 slightly reduces the output characteristics of the gate signal compared to the method shown in FIG. 3, but in order to reduce the area occupied by the circuit when implementing a narrow bezel, the shift register is installed on one side (left or right) of the display area (AA). It is a structure placed only in .

A first left stage circuit unit GIPL1 is disposed on the first gate line GL1 of the display panel 110. The first gate line GL1 transmits a gate signal provided by the operation of the first left stage circuit unit GIPL1 disposed in the left non-display area LNA.

A second left stage circuit unit GIPL2 is disposed on the second gate line GL2 of the display panel 110. The second gate line GL2 transmits a gate signal provided by the operation of the second left stage circuit unit GIPL2 disposed in the left non-display area LNA.

The stage circuit units shown in FIGS. 3 and 4 output a gate signal in the first scan direction (y2) (unidirectional scan) or output gate signals in the first scan direction (y2) and the second scan direction (y1) (bidirectional scan). scan) can be done. Meanwhile, in FIGS. 3 and 4 , to simplify the explanation, it is shown and explained that the stage circuit units are disposed only on the first gate line GL1 and the second gate line GL2. However, the stage circuit parts are arranged up to the last gate line of the display panel 110.

Meanwhile, the previously described built-in gate driver implements shift registers 140B and 140A using oxide or amorphous silicon thin film transistors. Oxide thin film transistors have excellent current movement characteristics and have the advantage of being able to design a smaller circuit compared to amorphous silicon thin film transistors. Amorphous silicon thin film transistors have the advantage of being able to maintain a constant threshold voltage over time and have better threshold voltage recovery characteristics due to stress bias compared to oxide thin film transistors.

A shift register made of an oxide thin film transistor has the above advantages, but its threshold voltage recovery characteristics are not as good as those of an amorphous silicon thin film transistor, so it is affected by the voltage continuously applied to the gate electrode. For example, when a negative voltage is continuously received, the threshold voltage moves in the negative (-) direction.

For this reason, unless the problem of leakage current generation due to the threshold voltage shift of the oxide thin film transistor is not supplemented or compensated for, charging and discharging of the Q node does not occur normally. And due to this effect, an error may occur in which the shift register cannot properly output the gate signal. Ultimately, this problem requires improvement as it can be a factor that prevents the display device from operating normally.

<First embodiment>

Figure 5 is a diagram schematically showing the N-th stage circuit unit according to the first embodiment of the present invention, Figure 6 is a first example diagram showing the blocked part in Figure 5, and Figure 7 is a diagram showing the blocked part in Figure 5. This is a second example diagram, and Figure 8 is a simulation waveform diagram showing the output state when the compensation circuit part is removed from the N-th stage circuit part according to the second example.

As shown in FIG. 5, the N-stage circuit unit (GIP n) according to the first embodiment of the present invention includes a first circuit unit (CIR1), a second circuit unit (CIR2), a third circuit unit (CIR3), and a fourth circuit unit. (CIR4) and a fifth circuit (CIR5).

The first circuit unit (CIR1) is a Q node charge/discharge circuit that charges or discharges the Q node (Q) in response to signals input from the outside, such as a start signal, a reset signal, and a voltage, such as a high potential voltage. When the Q node (Q) is in a charged state, the QB node (QB) is in a discharge state.

The second circuit unit (CIR2) is a QB node charging/discharging circuit that discharges or charges the QB node (QB) in response to the potential of the Q node (Q). When the QB node (QB) is in a charged state, the Q node (Q) is in a discharge state. The second circuit unit (CIR2) serves to switch charging and discharging between the Q node (Q) and the QB node (QB), so it is also defined as an inverter circuit unit.

The third circuit unit (CIR3) is an output buffer that uses the potential of the Q node (Q) as the signal of the gate electrode and sends the externally applied clock signal as its output (stage circuit unit) in response to the potential of the Q node (Q). It is a circuit. The third circuit unit (CIR3) has a bootstrap function using a capacitor provided therein. The third circuit unit (CIR3) includes the first and second clock signals supplied through the first clock signal line (CRCLK[n]), the second clock signal line (SCCLK[n]), and the third clock signal line (SECLK[n]). The 2nd and 3rd clock signals are output through their output terminals (C[n], SCOUT[n], SEOUT[n]).

The fourth circuit unit (CIR4) uses the potential of the QB node (QB) as the signal of the gate electrode and operates the Q node (Q) and output terminal in the section where it (the stage circuit unit) does not drive in response to the potential of the QB node (QB). It is a stabilization circuit that stabilizes ripple. A QB node (QH) exists between the first circuit unit (CIR1) and the fourth circuit unit (CIR4).

The fifth circuit unit (CIR5) is a compensation circuit unit that complements or compensates for the problem of leakage current occurring due to a shift in the threshold voltage of the oxide thin film transistor constituting the first circuit unit (CIR1). The fifth circuit unit (CIR5) serves to form a compensation voltage (Vc1) lower than the threshold voltage (Vth) of the oxide thin film transistor constituting the first circuit unit (CIR1). More specifically, when the fifth circuit unit (CIR5) maintains the Q node at a potential lower than the potential of the QB node, a voltage lower than 0 is applied between the gate source (Vgs) of the N-type thin film transistor constituting the first circuit unit (CIR1). It plays a role in authorizing. The compensation voltage formed by the fifth circuit part CIR5 is applied to the gate electrode of the oxide thin film transistor constituting the first circuit part CIR1. Because of this, the oxide thin film transistor constituting the first circuit part CIR1 maintains the turned-off state for a certain period of time.

Meanwhile, in the first embodiment of the present invention, the N-stage circuit unit (GIP n) having the first circuit unit (CIR1), the second circuit unit (CIR2), the third circuit unit (CIR3), and the fourth circuit unit (CIR4) has a fifth circuit unit (GIP n). Although the circuit unit (CIR5) is added as an example, this is only an example and the present invention is not limited to this. The main part of the first embodiment of the present invention is the fifth circuit unit (CIR5), which supplements or compensates for the problem of leakage current caused by the threshold voltage shift of the oxide thin film transistor, and the description hereinafter will focus on this.

The fifth circuit unit (CIR5) includes a one-side compensation unit including a 1a compensation transistor (TRS1a), a 1b compensation transistor (TRS1b), and a first compensation capacitor (C1), a 2a compensation transistor (TRS2a), and a 2b compensation transistor. (TRS2b) and a second compensation capacitor (C1).

The first compensation transistor (TRS1a) has a gate electrode connected to the reset signal line (RESET), a first electrode connected to the ground voltage line (GND), and a first output terminal (C[n-3) of the N-3 stage circuit part. ]) The second electrode is connected to the The N-3 carry signal is output from the first output terminal (C[n-3]) of the N-3 stage circuit unit.

The 1b compensation transistor TRS1b has a gate electrode connected to the reset signal line RESET, a first electrode connected to the first low potential voltage line GVSS1, and a first circuit part CIR1 of the N stage circuit part GIP n. ) The second electrode is connected to one input terminal.

The first compensation capacitor (C1) has one end connected to the first output terminal (C[n-3]) of the N-3 stage circuit unit and one end of the first circuit unit (CIR1) of the N-th stage circuit unit (GIP n). The other end is connected to the terminal.

The 2a compensation transistor (TRS2a) has a gate electrode connected to the reset signal line (RESET), a first electrode connected to the ground voltage line (GND), and a first output terminal (C[n+3) of the N+3 stage circuit unit. ]) The second electrode is connected to the The N+3th carry signal is output from the first output terminal (C[n+3]) of the N+3th stage circuit unit.

The 2b compensation transistor TRS2b has a gate electrode connected to the reset signal line RESET, a first electrode connected to the first low potential voltage line GVSS1, and a first circuit part CIR1 of the N stage circuit part GIP n. ) The second electrode is connected to the other input terminal.

The second compensation capacitor (C1) has one end connected to the first output terminal (C[n+3]) of the N+3 stage circuit unit and the other end of the first circuit unit (CIR1) of the N stage circuit unit (GIP n). The other end is connected to the terminal.

As above, one side and the other side of the fifth circuit part (CIR5) have a 2T (transistor) 1C (capacitor) structure. And the compensation transistors (TRS1a, TRS1b, TRS2a, TRS2b) included in one side and the other side of the compensation section all have their gate electrodes commonly connected to the reset signal line (RESET). Accordingly, one side of the compensator and the other side of the compensator operate in response to the logic state of the reset signal applied through the reset signal line (RESET).

And, based on the operation of the compensation transistors (TRS1a, TRS1b, TRS2a, TRS2b) and the voltage applied to both ends of the first and second compensation capacitors (C1, C2), the first circuit part (GIP n) of the N stage circuit part (GIP n) This prevents the problem of leakage current occurring in the oxide thin film transistor included in CIR1). To this end, the compensation voltage (Vc1) initialized between the first and second compensation capacitors (C1, C2) is set to Vc1 < Vth. Here, Vc1 is the voltage formed by one side compensation part of the fifth circuit part CIR5 (the other side compensation part is also set to the same voltage type), and Vth is the threshold voltage of the oxide thin film transistor constituting the first circuit part CIR1.

When the N-3th and N+3th carry signals are input to one side and the other side of the fifth circuit unit (CIR5), respectively, the first and second compensation capacitors are connected to the A node (a) and B node (b). It is boosted by the voltage initialized at (C1, C2). For this reason, the compensation voltages Vc1 and Vc2 stored in the first and second compensation capacitors C1 and C2 are lower than the threshold voltage of the oxide thin film transistor constituting the first circuit part CIR1. Therefore, even if the threshold voltage of the oxide thin film transistor constituting the first circuit part CIR1 moves in the negative (-) direction, the turn-off state without leakage current can be maintained.

Both ends of the first and second compensation capacitors C1 and C2 may be initialized or reset at least once per frame by the operation of the compensation transistors TRS1a, TRS1b, TRS2a, and TRS2b, but the present invention is not limited to this.

Meanwhile, in the above explanation, it was explained as an example that the N-3th and N+3th carry signals are input to one side of the compensation section and the other side of the fifth circuit section (CIR5), respectively. However, this is only an example, and the carry signal input to one side of the compensation section and the other side of the fifth circuit section (CIR5) may vary depending on the input/output signal and design method of the stage circuit section. Therefore, it should be understood that the N-kth and N+kth (k is an integer greater than 1) carry signal is input to one side and the other side of the compensation section of the fifth circuit unit (CIR5), respectively.

As shown in FIG. 6, according to the first example, the circuits of the first circuit part (CIR1), the second circuit part (CIR2), the third circuit part (CIR3), and the fourth circuit part (CIR4) are configured to enable unidirectional scanning. . For example, the transistors included in the first circuit part (CIR1), the second circuit part (CIR2), the third circuit part (CIR3), and the fourth circuit part (CIR4) are all N-type, but the present invention is not limited thereto. N-type transistors turn on when a high potential voltage is applied to the gate electrode and turn off when a low potential voltage or ground voltage is applied.

The first circuit unit (CIR1) includes a 1st transistor (T1a), a 1b transistor (T1b), a 2a transistor (T2a), and a 2b transistor (T2b). The 1a transistor (T1a) and the 1b transistor (T1b) form one input terminal of the first circuit part (CIR1), and the 2a transistor (T2a) and the 2b transistor (T2b) form the other side of the first circuit part (CIR1). Configure the input terminal.

The 1st transistor (T1a) has a gate electrode and a first electrode connected to the first output terminal (C[n-3]) of the N-3 stage circuit part, and a second electrode is connected to the first electrode of the 1b transistor (T1b). This is connected. The 1b transistor (T1b) has a gate electrode connected to the first output terminal (C[n-3]) of the N-3 stage circuit unit, a first electrode connected to the second electrode of the 1a transistor (T1a), and a The second electrode is connected to the first electrode of the 2a transistor (T2a). The 2a transistor (T2a) has a gate electrode connected to the first output terminal (C[n+3]) of the N+3 stage circuit unit, a first electrode connected to the second electrode of the 1b transistor (T1b), and a first electrode connected to the second electrode of the 1b transistor (T1b). The second electrode is connected to the first electrode of the 2b transistor (T2b). The 2b transistor (T2b) has its gate electrode connected to the first output terminal (C[n+3]) of the N+3 stage circuit unit, its first electrode connected to the second electrode of the 2a transistor (T2a), and the 2The second electrode is connected to the low-potential voltage line (GVSS2).

The second circuit unit (CIR2) includes a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and an eighth transistor (T8). Includes. The third transistor (T3), fourth transistor (T4), fifth transistor (T5), sixth transistor (T6), seventh transistor (T7), and eighth transistor (T8) are connected to Q node (Q) and QB. Controls charging and discharging of the node (QB).

The third transistor (T3) has a gate electrode connected to the Q node (Q), a first electrode connected to the high potential voltage line (GVDD), a second electrode of the 1st transistor (T1a) of the first circuit part (CIR1), and The second electrode is connected to the first electrode of the 1b transistor T1b. The fourth transistor (T4) has a gate electrode connected to the second electrode of the fifth transistor (T5) and the first electrode of the sixth transistor (T6), a first electrode connected to the high potential voltage line (GVDD), and a QB node. The second electrode is connected to (QB). The gate electrode and first electrode of the fifth transistor T5 are connected to the high potential voltage line GVDD, and the second electrode is connected to the first electrode of the sixth transistor T6. The sixth transistor (T6) has its gate electrode connected to the Q node (Q), its first electrode connected to the second electrode of the fifth transistor (T5), and its second electrode connected to the second low-potential voltage line (GVSS2). do. The seventh transistor T7 has a gate electrode connected to the Q node (Q), a first electrode connected to the QB node (QB), and a second electrode connected to the second low potential voltage line (GVSS2). The eighth transistor (T8) has a gate electrode connected to the first output terminal (C[n-3]) of the N-3 stage circuit unit, a first electrode connected to the QB node (QB), and a second low-potential voltage line. The second electrode is connected to (GVSS2).

The third circuit unit (CIR3) includes a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11), a first boot capacitor (CB1), a second boot capacitor (CB2), and a third boot capacitor (CB3). ) includes. The 9th transistor (T9) outputs the first clock signal through the first output terminal (C[n]) of the N-th stage circuit unit (GIP n), and the 10th transistor (T10) outputs the first clock signal through the first output terminal (C[n]) of the N-th stage circuit unit (GIP n). ) outputs the second clock signal through the second output terminal (SCOUT[n]), and the 11th transistor (T11) outputs the second clock signal through the third output terminal (SEOUT[n]) of the N-th stage circuit unit (GIP n). Outputs the third clock signal.

The ninth transistor (T9) has a gate electrode connected to the Q node (Q), a first electrode connected to the first clock signal line (CRCLK[n]), and a first output terminal ( The second electrode is connected to C[n]). The first boot capacitor CB1 has one end connected to the Q node (Q) and the other end connected to the first output terminal (C[n]) of the N-th stage circuit unit (GIP n). The tenth transistor T10 has a gate electrode connected to the Q node (Q), a first electrode connected to the second clock signal line (SCCLK[n]), and a second output terminal ( The second electrode is connected to SCOUT[n]). The second boot capacitor CB2 has one end connected to the Q node (Q) and the other end connected to the second output terminal (SCOUT[n]) of the N-th stage circuit unit (GIP n). The 11th transistor (T11) has a gate electrode connected to the Q node (Q), a first electrode connected to the third clock signal line (SECLK[n]), and a third output terminal ( The second electrode is connected to SEOUT[n]). The third boot capacitor CB3 has one end connected to the Q node (Q) and the other end connected to the third output terminal (SEOUT[n]).

The fourth circuit unit (CIR4) includes a 12a transistor (T12a), a 12b transistor (T12b), a 13th transistor (T13), a 14th transistor (T14), and a 15th transistor (T15). The 12a transistor (T12a), 12b transistor (T12b), 13th transistor (T13), 14th transistor (T14), and 15th transistor (T15) stabilize ripple.

The 12a transistor (T12a) has a gate electrode connected to the QB node (QB), a first electrode connected to the Q node (Q), and a second electrode connected to the first electrode of the 12b transistor (T12b). The 12b transistor (T12b) has a gate electrode connected to the QB node (QB), a first electrode connected to the second electrode of the 12a transistor (T12a), and a second electrode connected to the second low potential voltage line (GVSS2). do. The node where the second electrode of the 12a transistor (T12a) and the first electrode of the 12b transistor (T12b) are connected is the QH node (QH). The QH node QH is also connected to the second electrode of the 2a transistor T2a and the first electrode of the 2b transistor T2b of the first circuit unit CIR1.

The thirteenth transistor T13 has a gate electrode connected to the QB node (QB), a first electrode connected to the first output terminal (C[n]), and a second electrode connected to the second low-potential voltage line (GVSS2). do. The 14th transistor (T14) has a gate electrode connected to the QB node (QB), a first electrode connected to the second output terminal (SCOUT[n]) of the N-stage circuit unit (GIP n), and a first low-potential voltage line. The second electrode is connected to (GVSS1). The 15th transistor (T15) has a gate electrode connected to the QB node (QB), a first electrode connected to the third output terminal (SEOUT[n]) of the N-stage circuit unit (GIP n), and a first low-potential voltage line. The second electrode is connected to (GVSS1).

The shift registers having the N-th stage circuit unit according to the first example above sequentially output gate signals in one direction when a signal is input to the input terminal of the first circuit unit (CIR1).

As shown in FIG. 7, according to the second example, the circuits of the first circuit part (CIR1), the second circuit part (CIR2), the third circuit part (CIR3), and the fourth circuit part (CIR4) are configured to enable bidirectional scanning. . For example, the transistors included in the first circuit part (CIR1), the second circuit part (CIR2), the third circuit part (CIR3), and the fourth circuit part (CIR4) are all N-type, but the present invention is not limited thereto. N-type transistors turn on when a high potential voltage is applied to the gate electrode and turn off when a low potential voltage or ground voltage is applied.

The first circuit unit (CIR1) includes a 1st transistor (T1a), a 1b transistor (T1b), a 2a transistor (T2a), and a 2b transistor (T2b). The 1a transistor (T1a) and the 1b transistor (T1b) form one input terminal of the first circuit part (CIR1), and the 2a transistor (T2a) and the 2b transistor (T2b) form the other side of the first circuit part (CIR1). Configure the input terminal.

The 1st transistor (T1a) has a gate electrode connected to the first output terminal (C[n-3]) of the N-3 stage circuit unit, a first electrode connected to the forward high potential voltage line (GVDD_F), and a 1b transistor. The second electrode is connected to the first electrode of (T1b). The 1b transistor (T1b) has a gate electrode connected to the first output terminal (C[n-3]) of the N-3 stage circuit unit, a first electrode connected to the second electrode of the 1a transistor (T1a), and a The second electrode is connected to the first electrode of the 2a transistor (T2a). The 2a transistor (T2a) has a gate electrode connected to the first output terminal (C[n+3]) of the N+3 stage circuit unit, a first electrode connected to the second electrode of the 1b transistor (T1b), and a first electrode connected to the second electrode of the 1b transistor (T1b). The second electrode is connected to the first electrode of the 2b transistor (T2b). The 2b transistor (T2b) has its gate electrode connected to the first output terminal (C[n+3]) of the N+3 stage circuit unit, its first electrode connected to the second electrode of the 2a transistor (T2a), and the reverse direction. The second electrode is connected to the high potential voltage line (GVDD_R).

The second circuit unit (CIR2) includes a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and an eighth transistor (T8). Includes. The third transistor (T3), fourth transistor (T4), fifth transistor (T5), sixth transistor (T6), seventh transistor (T7), and eighth transistor (T8) are connected to Q node (Q) and QB. Controls charging and discharging of the node (QB).

The third transistor (T3) has a gate electrode connected to the Q node (Q), a first electrode connected to the high potential voltage line (GVDD), a second electrode of the 1st transistor (T1a) of the first circuit part (CIR1), and The second electrode is connected to the first electrode of the 1b transistor T1b. The fourth transistor (T4) has a gate electrode connected to the second electrode of the fifth transistor (T5) and the first electrode of the sixth transistor (T6), a first electrode connected to the high potential voltage line (GVDD), and a QB node. The second electrode is connected to (QB). The gate electrode and first electrode of the fifth transistor T5 are connected to the high potential voltage line GVDD, and the second electrode is connected to the first electrode of the sixth transistor T6. The sixth transistor (T6) has its gate electrode connected to the Q node (Q), its first electrode connected to the second electrode of the fifth transistor (T5), and its second electrode connected to the second low-potential voltage line (GVSS2). do. The seventh transistor T7 has a gate electrode connected to the Q node (Q), a first electrode connected to the QB node (QB), and a second electrode connected to the second low potential voltage line (GVSS2). The eighth transistor (T8) has a gate electrode connected to the first output terminal (C[n-3]) of the N-3 stage circuit unit, a first electrode connected to the QB node (QB), and a second low-potential voltage line. The second electrode is connected to (GVSS2).

The third circuit unit (CIR3) includes a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11), a first boot capacitor (CB1), a second boot capacitor (CB2), and a third boot capacitor (CB3). ) includes. The 9th transistor (T9) outputs the first clock signal through the first output terminal (C[n]) of the N-th stage circuit unit (GIP n), and the 10th transistor (T10) outputs the first clock signal through the first output terminal (C[n]) of the N-th stage circuit unit (GIP n). ) outputs the second clock signal through the second output terminal (SCOUT[n]), and the 11th transistor (T11) outputs the second clock signal through the third output terminal (SEOUT[n]) of the N-th stage circuit unit (GIP n). Outputs the third clock signal.

The ninth transistor (T9) has a gate electrode connected to the Q node (Q), a first electrode connected to the first clock signal line (CRCLK[n]), and a first output terminal ( The second electrode is connected to C[n]). The first boot capacitor CB1 has one end connected to the Q node (Q) and the other end connected to the first output terminal (C[n]) of the N-th stage circuit unit (GIP n). The tenth transistor T10 has a gate electrode connected to the Q node (Q), a first electrode connected to the second clock signal line (SCCLK[n]), and a second output terminal ( The second electrode is connected to SCOUT[n]). The second boot capacitor CB2 has one end connected to the Q node (Q) and the other end connected to the second output terminal (SCOUT[n]) of the N-th stage circuit unit (GIP n). The 11th transistor (T11) has a gate electrode connected to the Q node (Q), a first electrode connected to the third clock signal line (SECLK[n]), and a third output terminal ( The second electrode is connected to SEOUT[n]). The third boot capacitor CB3 has one end connected to the Q node (Q) and the other end connected to the third output terminal (SEOUT[n]) of the N stage circuit unit (GIP n).

The fourth circuit unit (CIR4) includes a 12a transistor (T12a), a 12b transistor (T12b), a 13th transistor (T13), a 14th transistor (T14), and a 15th transistor (T15). The 12a transistor (T12a), 12b transistor (T12b), 13th transistor (T13), 14th transistor (T14), and 15th transistor (T15) stabilize ripple.

The 12a transistor (T12a) has a gate electrode connected to the QB node (QB), a first electrode connected to the Q node (Q), and a second electrode connected to the first electrode of the 12b transistor (T12b). The 12b transistor (T12b) has a gate electrode connected to the QB node (QB), a first electrode connected to the second electrode of the 12a transistor (T12a), and a second electrode connected to the second low potential voltage line (GVSS2). do. The node where the second electrode of the 12a transistor (T12a) and the first electrode of the 12b transistor (T12b) are connected is the QH node (QH). The QH node QH is also connected to the second electrode of the 2a transistor T2a and the first electrode of the 2b transistor T2b of the first circuit unit CIR1.

The 13th transistor (T13) has a gate electrode connected to the QB node (QB), a first electrode connected to the first output terminal (C[n]) of the N-stage circuit unit (GIP n), and a second low-potential voltage line. The second electrode is connected to (GVSS2). The 14th transistor (T14) has a gate electrode connected to the QB node (QB), a first electrode connected to the second output terminal (SCOUT[n]) of the N-stage circuit unit (GIP n), and a first low-potential voltage line. The second electrode is connected to (GVSS1). The 15th transistor (T15) has a gate electrode connected to the QB node (QB), a first electrode connected to the third output terminal (SEOUT[n]) of the N-stage circuit unit (GIP n), and a first low-potential voltage line. The second electrode is connected to (GVSS1).

The shift registers having the N-th stage circuit unit according to the second example above have a signal input to the input terminal of the first circuit unit (CIR1) and a voltage applied to the forward high potential voltage line (GVDD_F) and the reverse high potential voltage line (GVDD_R). Accordingly, the gate signals are sequentially output in the first scan direction or the second scan direction.

Meanwhile, the N-th stage circuit unit according to the first and second examples described above receives the N-3th carry signal as a set signal and the N+3th carry signal as a reset signal. And the Q node (Q) operates at logic high by the N-3rd carry signal, which is a set signal, and the second clock signal of the second clock signal line (SCCLK[n]) is output correspondingly. .

During the output and non-output periods of the second clock signal line (SCCLK[n]), the Q node (Q) operates at logic high or logic low by the set signal and reset signal. The N-th stage circuit unit according to the first example forms the 1a transistor T1a of the first circuit unit CIR1 in a diode connection state in order to maintain the Q node Q at logic low.

In this case, operation is possible even if the threshold voltage of the first transistor T1a moves in the negative direction. For this reason, in the case of the N-stage circuit unit according to the first example, it is possible to omit the fifth circuit unit (CIR5) to complement or compensate for the problem of leakage current generation due to a shift in the threshold voltage of the oxide thin film transistor. That is, the N-th stage circuit according to the first example can compensate or complement even if the threshold voltage of the 1st transistor T1a moves in the negative direction.

The N-stage circuit according to the second example includes a forward high-potential voltage line (GVDD_F) and a reverse high-potential voltage line (GVDD_R) capable of varying the voltage of the transistors (T1a and T2b) that receive set and reset signals for bidirectional scan driving. ) connect. However, in the case of the N-th stage circuit unit according to the second example, the Q node (Q) does not have a diode connection state to maintain logic low.

For this reason, in the case of the N-stage circuit unit according to the second example, it is impossible to omit the fifth circuit unit (CIR5) to complement or compensate for the problem of leakage current generation due to a shift in the threshold voltage of the oxide thin film transistor. That is, the N-th stage circuit unit according to the second example cannot compensate or supplement when the threshold voltage of the 1a transistor (T1a) moves in the negative direction.

When the fifth circuit part (CIR5) is removed from the N stage circuit part according to the second example and the N stage circuit part is driven for a long time, a high direct current voltage is continuously applied to the drain electrode of the first transistor T1a. As a result, the threshold voltage of the first transistor T1a moves in the negative direction. Due to this effect, the voltage of the Q node (Q) decreases as shown in (a) of FIG. 8. And due to this effect, the output waveform becomes lower as shown in (b) of FIG. 8.

Hereinafter, in the second embodiment, as an example of the N stage circuit part, the first circuit part (CIR1), the second circuit part (CIR2), the third circuit part (CIR3), the fourth circuit part (CIR4), and the fifth circuit part (CIR5) The circuit configuration is specified and its operation is explained.

<Second Embodiment>

Figure 9 is a diagram showing the N-th stage circuit unit in detail according to the second embodiment of the present invention, Figures 10 to 16 are signal waveform diagrams for explaining the driving characteristics of each section of the N-th stage circuit unit, and Figures 17 to 17 19 is a simulation waveform diagram showing the waveforms during first direction scan, second direction scan, and bidirectional scan operation.

As shown in FIG. 9, the N-stage circuit unit (GIP n) according to the second embodiment of the present invention includes a first circuit unit (CIR1), a second circuit unit (CIR2), a third circuit unit (CIR3), and a fourth circuit unit. (CIR4) and a fifth circuit (CIR5).

The first circuit unit (CIR1) charges or discharges the Q node (Q) in response to signals and voltages input from the fifth circuit unit (CIR5), the forward high potential voltage line (GVDD_F), and the reverse high potential voltage line (GVDD_R). It is a Q node charge/discharge circuit. When the Q node (Q) is in a charged state, the QB node (QB) is in a discharge state. The first circuit unit (CIR1) includes a 1st transistor (T1a), a 1b transistor (T1b), a 2a transistor (T2a), and a 2b transistor (T2b). The 1a transistor (T1a) and the 1b transistor (T1b) form one input terminal of the first circuit part (CIR1), and the 2a transistor (T2a) and the 2b transistor (T2b) form the other side of the first circuit part (CIR1). Configure the input terminal.

The second circuit unit (CIR2) is a QB node charging/discharging circuit that discharges or charges the QB node (QB) in response to the potential of the Q node (Q). When the QB node (QB) is in a charged state, the Q node (Q) is in a discharge state. The second circuit unit (CIR2) serves to switch charging and discharging between the Q node (Q) and the QB node (QB), so it is also defined as an inverter circuit unit. The second circuit unit (CIR2) includes a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and an eighth transistor (T8). Includes. The third transistor (T3), fourth transistor (T4), fifth transistor (T5), sixth transistor (T6), seventh transistor (T7), and eighth transistor (T8) are connected to Q node (Q) and QB. Controls charging and discharging of the node (QB).

The third circuit unit (CIR3) is an output buffer that uses the potential of the Q node (Q) as the signal of the gate electrode and sends the externally applied clock signal as its output (stage circuit unit) in response to the potential of the Q node (Q). It is a circuit. The third circuit unit (CIR3) has a bootstrap function using a capacitor provided therein. The third circuit unit (CIR3) includes the first and second clock signals supplied through the first clock signal line (CRCLK[n]), the second clock signal line (SCCLK[n]), and the third clock signal line (SECLK[n]). The 2nd and 3rd clock signals are output through their output terminals (C[n], SCOUT[n], SEOUT[n]). The third circuit unit (CIR3) includes a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11), a first boot capacitor (CB1), a second boot capacitor (CB2), and a third boot capacitor (CB3). ) includes. The 9th transistor (T9) outputs the first clock signal through the first output terminal (C[n]) of the N-th stage circuit unit (GIP n), and the 10th transistor (T10) outputs the first clock signal through the first output terminal (C[n]) of the N-th stage circuit unit (GIP n). ) outputs the second clock signal through the second output terminal (SCOUT[n]), and the 11th transistor (T11) outputs the second clock signal through the third output terminal (SEOUT[n]) of the N-th stage circuit unit (GIP n). Outputs the third clock signal.

The fourth circuit unit (CIR4) uses the potential of the QB node (QB) as the signal of the gate electrode and operates the Q node (Q) and output terminal in the section where it (the stage circuit unit) does not drive in response to the potential of the QB node (QB). It is a stabilization circuit that stabilizes ripple. A QB node (QH) exists between the first circuit unit (CIR1) and the fourth circuit unit (CIR4). The fourth circuit unit (CIR4) includes a 12a transistor (T12a), a 12b transistor (T12b), a 13th transistor (T13), a 14th transistor (T14), and a 15th transistor (T15). The 12a transistor (T12a), 12b transistor (T12b), 13th transistor (T13), 14th transistor (T14), and 15th transistor (T15) stabilize ripple.

The fifth circuit unit (CIR5) is a compensation circuit unit that complements or compensates for the problem of leakage current occurring due to a shift in the threshold voltage of the oxide thin film transistor constituting the first circuit unit (CIR1). The fifth circuit unit (CIR5) serves to form a compensation voltage (Vc1) lower than the threshold voltage (Vth) of the oxide thin film transistor constituting the first circuit unit (CIR1). In other words, the fifth circuit unit CIR5 forms a gate source voltage (Vgs) lower than the threshold voltage (Vth) of the oxide thin film transistor constituting the first circuit unit (CIR1). The fifth circuit unit (CIR5) includes a one-side compensation unit including a 1a compensation transistor (TRS1a), a 1b compensation transistor (TRS1b), and a first compensation capacitor (C1), a 2a compensation transistor (TRS2a), and a 2b compensation transistor. (TRS2b) and a second compensation capacitor (C1).

The connection relationship between the elements included in the first circuit part (CIR1) to the fifth circuit part (CIR5) is explained as follows.

The 1a transistor (T1a) has a gate electrode connected to the second electrode of the 1b compensation transistor (TRS1b) included in one side compensation part of the fifth circuit unit (CIR5) and the other end of the first compensation capacitor (C1), and has a forward high potential. The first electrode is connected to the voltage line (GVDD_F) and the second electrode is connected to the first electrode of the 1b transistor (T1b). The 1b transistor (T1b) has a gate electrode connected to the gate electrode of the 1a transistor (T1a), a first electrode connected to the second electrode of the 1a transistor (T1a), and a first electrode connected to the first electrode of the 2a transistor (T2a). The second electrode is connected. The 2a transistor (T2a) has a gate electrode connected to the first electrode of the 2b compensation transistor (TRS2b) included in the other compensation part of the fifth circuit unit (CIR5) and the other end of the second compensation capacitor (C2), and the 1b transistor The first electrode is connected to the second electrode of (T1b) and the second electrode is connected to the first electrode of the 2b transistor (T2b). The 2b transistor (T2b) has a gate electrode connected to the gate electrode of the 2a transistor (T2a), a first electrode connected to the second electrode of the 2a transistor (T2a), and a second electrode connected to the reverse high potential voltage line (GVDD_R). Electrodes are connected.

The third transistor (T3) has a gate electrode connected to the Q node (Q), a first electrode connected to the high potential voltage line (GVDD), a second electrode of the 1st transistor (T1a) of the first circuit part (CIR1), and The second electrode is connected to the first electrode of the 1b transistor T1b. The fourth transistor (T4) has a gate electrode connected to the second electrode of the fifth transistor (T5) and the first electrode of the sixth transistor (T6), a first electrode connected to the high potential voltage line (GVDD), and a QB node. The second electrode is connected to (QB). The gate electrode and first electrode of the fifth transistor T5 are connected to the high potential voltage line GVDD, and the second electrode is connected to the first electrode of the sixth transistor T6. The sixth transistor (T6) has its gate electrode connected to the Q node (Q), its first electrode connected to the second electrode of the fifth transistor (T5), and its second electrode connected to the second low-potential voltage line (GVSS2). do. The seventh transistor T7 has a gate electrode connected to the Q node (Q), a first electrode connected to the QB node (QB), and a second electrode connected to the second low-potential voltage line (GVSS2). The eighth transistor (T8) has a gate electrode connected to the first output terminal (C[n-3]) of the N-3 stage circuit unit, a first electrode connected to the QB node (QB), and a second low-potential voltage line. The second electrode is connected to (GVSS2).

The ninth transistor (T9) has a gate electrode connected to the Q node (Q), a first electrode connected to the first clock signal line (CRCLK[n]), and a first output terminal ( The second electrode is connected to C[n]). The first boot capacitor CB1 has one end connected to the Q node (Q) and the other end connected to the first output terminal (C[n]) of the N-th stage circuit unit (GIP n). The tenth transistor T10 has a gate electrode connected to the Q node (Q), a first electrode connected to the second clock signal line (SCCLK[n]), and a second output terminal ( The second electrode is connected to SCOUT[n]). The second boot capacitor CB2 has one end connected to the Q node (Q) and the other end connected to the second output terminal (SCOUT[n]) of the N-th stage circuit unit (GIP n). The 11th transistor (T11) has a gate electrode connected to the Q node (Q), a first electrode connected to the third clock signal line (SECLK[n]), and a third output terminal ( The second electrode is connected to SEOUT[n]). The third boot capacitor CB3 has one end connected to the Q node (Q) and the other end connected to the third output terminal (SEOUT[n]) of the N stage circuit unit (GIP n).

The 12a transistor (T12a) has a gate electrode connected to the QB node (QB), a first electrode connected to the Q node (Q), and a second electrode connected to the first electrode of the 12b transistor (T12b). The 12b transistor (T12b) has a gate electrode connected to the QB node (QB), a first electrode connected to the second electrode of the 12a transistor (T12a), and a second electrode connected to the second low potential voltage line (GVSS2). do. The node where the second electrode of the 12a transistor (T12a) and the first electrode of the 12b transistor (T12b) are connected is the QH node (QH). The QH node QH is also connected to the second electrode of the 2a transistor T2a and the first electrode of the 2b transistor T2b of the first circuit unit CIR1. The 13th transistor (T13) has a gate electrode connected to the QB node (QB), a first electrode connected to the first output terminal (C[n]) of the N-stage circuit unit (GIP n), and a second low-potential voltage line. The second electrode is connected to (GVSS2). The 14th transistor (T14) has a gate electrode connected to the QB node (QB), a first electrode connected to the second output terminal (SCOUT[n]) of the N-stage circuit unit (GIP n), and a first low-potential voltage line. The second electrode is connected to (GVSS1). The 15th transistor (T15) has a gate electrode connected to the QB node (QB), a first electrode connected to the third output terminal (SEOUT[n]) of the N-stage circuit unit (GIP n), and a first low-potential voltage line. The second electrode is connected to (GVSS1).

The first compensation transistor (TRS1a) has a gate electrode connected to the reset signal line (RESET), a first electrode connected to the ground voltage line (GND), and a first output terminal (C[n-3) of the N-3 stage circuit part. ]) The second electrode is connected to the The N-3 carry signal is output from the first output terminal (C[n-3]) of the N-3 stage circuit unit. The 1b compensation transistor (TRS1b) has a gate electrode connected to the reset signal line (RESET), a first electrode connected to the first low potential voltage line (GVSS1), and a second electrode connected to one input terminal of the first circuit unit (CIR1). This is connected. The first compensation capacitor C1 has one end connected to the first output terminal (C[n-3]) of the N-3 stage circuit part and the other end connected to one input terminal of the first circuit part CIR1. The 2a compensation transistor (TRS2a) has a gate electrode connected to the reset signal line (RESET), a first electrode connected to the ground voltage line (GND), and a first output terminal (C[n+3) of the N+3 stage circuit unit. ]) The second electrode is connected to the The N+3th carry signal is output from the first output terminal (C[n+3]) of the N+3th stage circuit unit. The 2b compensation transistor (TRS2b) has a gate electrode connected to the reset signal line (RESET), a first electrode connected to the first low potential voltage line (GVSS1), and a second electrode connected to the other input terminal of the first circuit unit (CIR1). This is connected. The second compensation capacitor C1 has one end connected to the first output terminal (C[n+3]) of the N+3 stage circuit unit and the other end connected to the other input terminal of the first circuit unit CIR1.

Meanwhile, a positive voltage, for example, a voltage of approximately 24V, may be applied to the forward high potential voltage line (GVDD_F) and the reverse high potential voltage line (GVDD_R) in a switching form. A first negative voltage lower than the ground voltage, for example, a voltage of approximately -6V, may be applied to the first low-potential voltage line (GVSS1), and the first low-potential voltage line (GVSS1) may be applied to the second low-potential voltage line (GVSS2). ) A second negative voltage lower than ), for example, a voltage of approximately -12V, may be applied. However, this is only one example and the present invention is not limited to this.

Hereinafter, the operation of the N-th stage circuit unit (GIP n) according to the second embodiment of the present invention will be described step by step as shown in FIGS. 10 to 16. However, to aid understanding of the explanation, refer to FIG. 9 for all steps.

During the first step (S1) of FIG. 10, only the reset signal (reset) is input at logic high. At this time, other signals remain logic low or are not input. When the reset signal (reset) is input as logic high, one side of the compensation section and the other side of the fifth circuit section (CIR5) are initialized. Due to the initialization operation of one side of the compensation section and the other side of the fifth circuit section (CIR5), the first and second compensation capacitors (C1, C2) are connected to the transistors (T1a, T1b, T2a, T2b) of the first circuit section (CIR1). A voltage lower than the threshold voltage is formed. The reset signal (reset) forms a logic high at least once per frame and remains logic low thereafter.

As described above, the voltage applied across the first and second compensation capacitors C1 and C2 is lower than the threshold voltage of the transistors T1a, T1b, T2a, and T2b of the first circuit unit CIR1. Therefore, the transistors T1a, T1b, T2a, and T2b of the first circuit part CIR1 are prevented from generating leakage current by the fifth circuit part CIR5. To this end, the compensation voltage (Vc1) initialized between the first and second compensation capacitors (C1, C2) is set to Vc1 < Vth. Here, Vc1 is the voltage formed by one side compensation part of the fifth circuit part CIR5 (the other side compensation part is also set to the same voltage type), and Vth is the threshold voltage of the oxide thin film transistor constituting the first circuit part CIR1.

During the second step (S2) of FIG. 11, the reset signal (reset) becomes logic low. And the N-3th carry signal (c[n-3]) is input as logic high, but the N+3th carry signal (c[n+3]) is input as logic low. During the second step (S2) of FIG. 11, a logic high voltage begins to be applied to the Q node (Q). Like the Q node (Q), a logic high voltage is applied to the QH node (QH). However, a logic low voltage is applied to the QB node (QB).

During the third step (S3) of FIG. 12, the N-3th carry signal (c[n-3]) and the N+3th carry signal (c[n+3]) are input as logic low. During the third step (S3) of FIG. 12, the Q node (Q) is charged to a logic high voltage. The QH node (QH) is charged by a logic high voltage like the Q node (Q). However, the QB node (QB) is discharged by the logic low voltage.

During the fourth step (S4) of FIG. 13, the first and second clock signals (crclk and scclk) are input at logic high. The third clock signal is omitted, but it may be the same as or different from the first and second clock signals (crclk and scclk). During the fourth step (S4) of FIG. 13, bootstrapping occurs by the first boot capacitor (CB1), the second boot capacitor (CB2), and the third boot capacitor (CB3), so that the potential of the Q node (Q) is rises compared to And in response to the potential of the Q node (Q), the first and second clock signals (crclk, scclk) are connected to the first output terminal (C[n]) and the second output terminal ( It is output through SCOUT[n]).

During the fifth step (S5) of FIG. 14, charging of the Q node (Q) and QH node (QH) is maintained and discharging of the QB node (QB) is maintained. Accordingly, the output of the first output terminal (C[n]) and the second output terminal (SCOUT[n]) of the N-th stage circuit unit (GIP n) is stably achieved.

During the sixth step (S6) of FIG. 15, the N-3th carry signal (c[n-3]) is maintained at logic low, but the N+3th carry signal (c[n+3]) is input at logic high. do. During the sixth step (S6) of FIG. 15, the Q node (Q) begins to discharge as a logic low voltage is applied. As the logic low voltage is applied to the QH node (QH), like the Q node (Q), it begins to discharge. However, the QB node (QB) begins to charge as a logic high voltage is applied.

During the seventh step (S7) of FIG. 16, the N-3th carry signal (c[n-3]) and the N+3th carry signal (c[n+3]) are maintained at logic low. Accordingly, the first output terminal (C[n]) and the second output terminal (SCOUT[n]) of the N-th stage circuit unit (GIP n) are maintained at logic low output.

The second embodiment of the present invention can supplement or compensate for the problem of leakage current occurring due to a shift in the threshold voltage of the oxide thin film transistor constituting the first circuit part CIR1 due to the operation of the fifth circuit part CIR5. This can also be seen through the simulation waveforms in FIGS. 17 to 19.

Figure 17 is a simulation waveform showing the potential of the Q node (Figure 17a) and the output of the second output terminal (Figure 17b) when the second embodiment is driven in the first scan direction (forward direction). Figure 18 is a simulation waveform showing the potential of the Q node (Figure 18a) and the output of the second output terminal (Figure 18b) when the second embodiment is driven in the second scan direction (reverse direction). Figure 19 is a simulation waveform showing the output of the second output terminal when driven in bidirectional scan.

The present invention has the effect of supplementing or compensating for the problem of leakage current caused by the threshold voltage shift of the thin film transistor and ensuring that the Q node is charged and discharged normally, thereby outputting a gate signal in one or two directions under stable driving conditions. . In addition, the present invention has the effect of improving the driving reliability of the display device by setting and maintaining stable driving conditions even if the threshold voltage of the thin film transistor changes.

Although embodiments of the present invention have been described with reference to the accompanying drawings, the technical configuration of the present invention described above can be modified by those skilled in the art in the technical field to which the present invention belongs in other specific forms without changing the technical idea or essential features of the present invention. You will understand that it can be done. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the claims described later rather than the detailed description above. In addition, the meaning and scope of the patent claims and all changes or modified forms derived from the equivalent concept should be construed as being included in the scope of the present invention.

CIR1: 1st circuit CIR2: 2nd circuit
CIR3: 3rd circuit CIR4: 4th circuit
CIR5: 5th circuit TRS1a: 1a compensation transistor
TRS1b: 1b compensation transistor C1: 1st compensation capacitor
TRS2a: 2a compensation transistor TRS2b: 2b compensation transistor
C1: Second compensation capacitor C[n]: First output terminal
SCOUT[n]: 2nd output terminal SEOUT[n]: 3rd output terminal

Claims (12)

A display panel that displays images; and
It includes a shift register that supplies a gate signal to the display panel,
The shift register is
A first circuit unit having one input terminal and another input terminal that receives signals and voltages supplied from the outside, and charging and discharging the Q node in response to the signals and voltages,
A second circuit unit that charges and discharges the QB node in response to the potential of the Q node,
A third circuit unit that receives at least one clock signal from the outside and outputs the at least one clock signal as its output in response to the potential of the Q node,
A display device including a compensation circuit unit that applies a compensation voltage lower than 0 to the gate electrode of at least one transistor of the first circuit unit that charges and discharges the Q node when the Q node is maintained at a potential lower than the potential of the QB node. . According to paragraph 1,
The compensation circuit is
A display device including a compensation capacitor that receives voltages of two different levels applied from the outside at both ends to provide the compensation voltage. According to paragraph 1,
The compensation circuit is
One side compensation unit including a 1a compensation transistor that transmits a ground voltage to one end of the first compensation capacitor and a 1b compensation transistor that transmits a first low potential voltage to the other end of the first compensation capacitor;
Comprising a second compensation transistor that transmits a ground voltage to one end of the second compensation capacitor and a second compensation transistor that transmits a first low-potential voltage to the other end of the second compensation capacitor;
The display device wherein the first low potential voltage is a first negative voltage lower than the ground voltage. According to paragraph 1,
The compensation circuit is
A 1a compensation transistor with a gate electrode connected to a reset signal line, a first electrode connected to a ground voltage line, and a second electrode connected to the first output terminal of the Nk (k is an integer greater than 1) stage circuit section;
a 1b compensation transistor with a gate electrode connected to the reset signal line, a first electrode connected to a first low-potential voltage line, and a second electrode connected to one input terminal of the first circuit part of the N-th stage circuit part;
A first compensation capacitor with one end connected to the first output terminal of the Nk (k is an integer greater than 1) stage circuit unit and the other end connected to one input terminal of the first circuit unit of the Nth stage circuit unit;
A 2a compensation transistor with a gate electrode connected to the reset signal line, a first electrode connected to the ground voltage line, and a second electrode connected to the first output terminal of the N+k (k is an integer greater than 1) stage circuit part. ,
a 2b compensation transistor having a gate electrode connected to the reset signal line, a first electrode connected to the first low-potential voltage line, and a second electrode connected to the other input terminal of the first circuit section of the N-th stage circuit section;
A display device including a second compensation capacitor with one end connected to a first output terminal of the N+k (k is an integer greater than or equal to 1) stage circuit unit and the other end connected to the other input terminal of the first circuit unit of the Nth stage circuit unit. . According to clause 4,
The first circuit part is
a 1a transistor whose gate electrode is connected to the second electrode of the 1b compensation transistor and the other end of the first compensation capacitor and whose first electrode is connected to a forward high potential voltage line;
a 1b transistor whose gate electrode is connected to the gate electrode of the 1a transistor and whose first electrode is connected to the second electrode of the 1a transistor;
a 2a transistor whose gate electrode is connected to the first electrode of the 2b compensation transistor and the other end of the second compensation capacitor and whose first electrode is connected to the second electrode of the 1b transistor;
A display device comprising a 2b transistor whose gate electrode is connected to the gate electrode of the 2a transistor, whose first electrode is connected to the second electrode of the 2a transistor, and whose second electrode is connected to a reverse high potential voltage line. According to clause 5,
The second circuit part is
A gate electrode is connected to the Q node, a first electrode is connected to a high potential voltage line, and a third electrode is connected to the second electrode of the first a transistor and the first electrode of the first b transistor of the first circuit part. transistor,
a fourth transistor having a first electrode connected to the high potential voltage line and a second electrode connected to the QB node;
a fifth transistor having a gate electrode and a first electrode connected to the high potential voltage line and a second electrode connected to the gate electrode of the fourth transistor;
a sixth transistor with a gate electrode connected to the Q node, a first electrode connected to the second electrode of the fifth transistor, and a second electrode connected to a second low-potential voltage line;
a seventh transistor with a gate electrode connected to the Q node, a first electrode connected to the QB node, and a second electrode connected to the second low-potential voltage line;
It includes an eighth transistor with a gate electrode connected to the first output terminal of the Nk (k is an integer greater than 1) stage circuit unit, a first electrode connected to the QB node, and a second electrode connected to the second low-potential voltage line. display device. According to clause 6,
The third circuit is
a ninth transistor with a gate electrode connected to the Q node, a first electrode connected to the first clock signal line, and a second electrode connected to the first output terminal of the N-th stage circuit unit;
a first boot capacitor with one end connected to the Q node and the other end connected to the first output terminal of the N-th stage circuit unit;
a tenth transistor with a gate electrode connected to the Q node, a first electrode connected to a second clock signal line, and a second electrode connected to a second output terminal of the N-th stage circuit unit;
a second boot capacitor with one end connected to the Q node and the other end connected to the second output terminal of the N-th stage circuit unit;
an 11th transistor with a gate electrode connected to the Q node, a first electrode connected to a third clock signal line, and a second electrode connected to a third output terminal of the N stage circuit unit;
A display device comprising a third boot capacitor, one end of which is connected to the Q node and the other end of which is connected to a third output terminal of the N-th stage circuit unit. In clause 7,
The shift register further includes a fourth circuit section,
The fourth circuit is
A 12a transistor with a gate electrode connected to the QB node and a first electrode connected to the Q node,
a 12b transistor with a gate electrode connected to the QB node, a first electrode connected to the second electrode of the 12a transistor, and a second electrode connected to the second low-potential voltage line;
a 13th transistor with a gate electrode connected to the QB node, a first electrode connected to the first output terminal of the N-th stage circuit unit, and a second electrode connected to the second low-potential voltage line;
a 14th transistor with a gate electrode connected to the QB node, a first electrode connected to the second output terminal of the N-th stage circuit unit, and a second electrode connected to the first low-potential voltage line;
A display device including a 15th transistor with a gate electrode connected to the QB node, a first electrode connected to a third output terminal of the N-th stage circuit unit, and a second electrode connected to the first low-potential voltage line. A first circuit unit having one input terminal and the other input terminal for receiving signals and voltages supplied from the outside, and charging and discharging the Q node in response to the signals and voltages;
a second circuit unit that charges and discharges the QB node in response to the potential of the Q node;
a third circuit unit that receives at least one clock signal from the outside and outputs the at least one clock signal as its output in response to the potential of the Q node; and
A shift register comprising a compensation circuit unit that applies a compensation voltage lower than a threshold voltage of the at least one transistor of the first circuit unit that charges and discharges the Q node to the gate electrode of the at least one transistor. According to clause 9,
The compensation circuit is
A shift register including a compensation capacitor that receives voltages of two different levels applied from the outside at both ends to provide the compensation voltage. According to clause 9,
The compensation circuit is
One side compensation unit including a 1a compensation transistor that transmits a ground voltage to one end of the first compensation capacitor and a 1b compensation transistor that transmits a first low potential voltage to the other end of the first compensation capacitor;
Comprising a second compensation transistor that transmits a ground voltage to one end of the second compensation capacitor and a second compensation transistor that transmits a first low-potential voltage to the other end of the second compensation capacitor;
A shift register wherein the first low potential voltage is a first negative voltage lower than the ground voltage. According to clause 9,
The compensation circuit is
A 1a compensation transistor with a gate electrode connected to a reset signal line, a first electrode connected to a ground voltage line, and a second electrode connected to the first output terminal of the Nk (k is an integer greater than 1) stage circuit section;
a 1b compensation transistor with a gate electrode connected to the reset signal line, a first electrode connected to a first low-potential voltage line, and a second electrode connected to one input terminal of the first circuit part of the N-th stage circuit part;
A first compensation capacitor with one end connected to the first output terminal of the Nk (k is an integer greater than 1) stage circuit unit and the other end connected to one input terminal of the first circuit unit of the Nth stage circuit unit;
A 2a compensation transistor with a gate electrode connected to the reset signal line, a first electrode connected to the ground voltage line, and a second electrode connected to the first output terminal of the N+k (k is an integer greater than 1) stage circuit part. ,
a 2b compensation transistor having a gate electrode connected to the reset signal line, a first electrode connected to the first low-potential voltage line, and a second electrode connected to the other input terminal of the first circuit section of the N-th stage circuit section;
A shift register including a second compensation capacitor with one end connected to the first output terminal of the N+k (k is an integer greater than or equal to 1) stage circuit part and the other end connected to the other input terminal of the first circuit part of the Nth stage circuit part. .

Images