KR102185119B1 - Display Device - Google Patents

Abstract

The display device of the present invention includes a display panel including a gate line and a shift register supplying a gate pulse to the gate line, wherein the shift register is the potential of the Q node and the Q B node in response to the gate start pulse or the output of the previous stage. In the non-display period, the output control signal of the first voltage level is applied and the output control signal of the second voltage level is applied to the output terminal according to the potentials of the Q node and the QB node. And a reset circuit that outputs or discharges the output terminal, and a gate pulse output unit that does not output a gate pulse in response to an output control signal of a first voltage level and outputs a gate pulse in response to an output control signal of a second voltage level.

Description

Display Device

The present invention relates to a display device.

In the display device, data lines and gate lines are arranged to be orthogonal, and pixels are arranged in a matrix form. A video data voltage to be displayed is supplied to the data lines, and a gate pulse is sequentially supplied to the gate lines. Video data voltages are supplied to pixels of a display line to which a gate pulse is supplied, and all display lines are sequentially scanned by the gate pulse to display video data.

A gate driver for supplying gate pulses to gate lines of a flat panel display device generally includes a plurality of gate integrated circuits (hereinafter referred to as “IC”). Since each gate drive IC must sequentially output gate pulses, it basically includes a shift register, and may include circuits and output buffers for adjusting an output voltage of the shift register according to a driving characteristic of a display panel.

Since driving of the gate drive ICs is very important in driving a display device as related to the scanning of horizontal lines, accuracy and stability are being emphasized. In order to stably drive the gate drive ICs, the shift registers are an initialization circuit (RESET) that initializes the node voltage of the node control circuit (NCON) and a control circuit that prevents the gate pulse from being output due to a malfunction. Includes (CONTROL). The initialization circuit (RESET) and the control circuit (CONTROL) operate using a low potential voltage (VSS) and a high potential constant voltage (VDD), respectively, and each uses four transistors.

In recent years, in order to simplify the driving drive IC, a method of forming a shift register of the gate drive IC on the panel is also used, and the initialization circuit (RESET) and control circuit (CONTROL) added to the shift register are used in the non-display area of the panel. It causes the size of the bezel to increase. This drawback is worsened when the screen of the display panel is enlarged or the resolution of the display panel is increased, and consequently, it is difficult to apply to a display panel having a large screen/high resolution, which is a trend of recent display devices.

In order to solve the above-described problems, the present invention is to provide a display device capable of stably driving a gate driver while minimizing additional semiconductor devices.

As a means for solving the above-described problems, the display device of the present invention includes a display panel including a gate line and a shift register supplying a gate pulse to the gate line, wherein the shift register is Q in response to the gate start pulse or the output of the previous stage. The node control circuit that controls the potentials of the node and the QB node receives the output control signal of the first voltage level during the non-display period, and receives the output control signal of the second voltage level during the display period according to the potentials of the Q node and the QB node. A reset circuit that outputs an output control signal to the output terminal or discharges the output terminal, and a gate pulse that does not output a gate pulse in response to an output control signal of the first voltage level and outputs a gate pulse in response to an output control signal of the second voltage level. Includes an output section.

The shift register of the present invention uses a reset signal that divides the display period and the non-display period to control the shift register so that the scan pulse is not output at an undesired timing, thereby reducing the number of transistors and stably driving the scan. . In addition, according to the present invention, the output terminal of the shift register can be initialized at once by using the reset signal during the driving preparation period, thereby further enhancing the reliability of scan driving.

As described above, the present invention performs a dual initialization process without increasing the number of transistors compared to the conventional reset circuit, so that the area occupied by the shift register in the panel can be reduced, and accordingly, a display having a high PPI (pixel per inch). It provides a display device that is advantageous to be applied to a panel.

1 is a block diagram showing a reset circuit and a control circuit included in a conventional shift register.
2 is a diagram illustrating a configuration of a display device according to an embodiment.
3 is a diagram showing a shift register according to an embodiment.
4 is a diagram showing a stage of a shift register according to an embodiment.
5 is a diagram illustrating embodiments of a gate pulse output unit.
6 is a circuit diagram showing a reset circuit according to the first embodiment.
7 is a waveform diagram showing input and output signals of the stage.
8 to 10 are circuit diagrams showing reset circuits according to the second to fourth embodiments, respectively.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, focusing on a liquid crystal display. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. The names of the constituent elements used in the following description are selected in consideration of ease of preparation of the specification, and may be different from the names of actual products.

2 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 2, the display device of the present invention includes a display panel 100, a data driving circuit 120, a level shifter 150, a shift register 130, a timing controller 110, and the like.

The display panel 100 includes data lines and gate lines intersecting each other, and pixels arranged in a matrix form. The display panel 100 may be a liquid crystal display (LCD), an organic light emitting diode display (OLED), an electrophoretic display (EPD), or the like.

The data driving circuit includes a plurality of source drive ICs 120. The source drive ICs 120 receive digital video data RGB from the timing controller 110. The source drive ICs 120 convert digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 110 to generate a data voltage, and synchronize the data voltage with the gate pulse. It is supplied to the data lines of the display panel 100 as possible. The source drive ICs may be connected to data lines of the display panel 100 through a chip on glass (COG) process or a tape automated bonding (TAB) process.

The scan driving circuit includes a timing controller 110 and a level shiftet 150 connected between gate lines of the display panel 100, and a gate shift register 130.

The level shifter 150 converts the transistor-transistor-logic (TTL) logic level voltage of the i-phase gate shift clocks CLK1 to CLKi input from the timing controller 110 into a gate high voltage VGH and a gate low voltage VGL. ) To level shift. Hereinafter, in the embodiment of the present invention, driving using the four-phase gate shift clocks CLK1 to CLK4 will be described as an example.

The gate shift register 130 is composed of stages that sequentially output a carry signal and a gate pulse Gout by shifting the gate start pulse VST in accordance with the gate shift clocks CLK1 to CLK4.

The scan driving circuit may be directly formed on the lower substrate of the display panel 100 in a GIP (Gate In Panel) method. In the GIP method, the level shifter 150 may be mounted on the PCB 140, and the gate shift register 130 may be formed on the lower substrate of the display panel 100.

The timing controller 110 receives digital video data (RGB) from an external host computer through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 110 transmits digital video data (RGB) input from the host computer to the source drive ICs 120.

The timing controller 110 provides timing of a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a main clock (MCLK) from a host computer through an LVDS or TMDS interface receiving circuit. It receives a signal. The timing controller 110 generates timing control signals for controlling the operation timing of the data driving circuit and the scan driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the scan driving circuit, and a data timing control signal for controlling the operation timing of the source drive ICs 120 and the polarity of the data voltage.

The scan timing control signal includes a gate start pulse (VST), a gate shift clock (CLK1 to CLK4), a gate output enable signal (Gate Output Enable; GOE), and the like. The gate start pulse VST is input to the gate shift register 130 to control the shift start timing.

The gate shift clocks CLK1 to CLK4 are level-shifted through the level shifter 150 and then input to the gate shift register 130, and are used as a clock signal for shifting the gate start pulse VST. The gate output enable signal GOE controls the output timing of the gate shift register 130.

Data timing control signals include Source Start Pulse (SSP), Source Sampling Clock (SSC), Polarity Control Signal (Polarity, POL), and Source Output Enable (SOE). Includes. The source start pulse SSP controls shift start timing of the source drive ICs 120. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 120 based on a rising or falling edge.

3 is a diagram showing a gate shift register 130 according to the present invention.

Referring to FIG. 3, the gate shift register 130 according to the present invention includes a plurality of stages (ST1 to STn, n is a natural number greater than or equal to 2) connected in a dependent manner. Each of the stages ST1 to STn outputs first to nth gate pulses Gout1 to Goutn, respectively. The gate pulse is applied to the gate lines of the display device and simultaneously serves as a carry signal transmitted to the front stage and the rear stage. In the following description, the "shearing stage" refers to being positioned above the standard stage. For example, based on the kth (k is a natural number of 1<k<n) stage STk, the front stage is one of the first stage ST1 to the k-1th stage ST(k-1). Instruct. The "rear stage" refers to being located below the standard stage. For example, based on the kth (1<k<n)th stage STk, the subsequent stage indicates any one of the k+1th stage ST(k+1) to the nth stage.

The gate shift register 130 sequentially outputs gate pulses Gout(1) to Gout(n). To this end, one of the sequentially delayed 4-phase gate shift clocks is input to the first stage ST1 to the n-th stage STn.

FIG. 4 is a diagram showing an example of the circuit configuration of the stage i (i is a natural number of 2<i<n) in FIG. 3.

Referring to FIG. 4, the i-th stage STi includes a node control circuit NCON, a reset circuit 131 and a gate pulse output unit 133.

The node control circuit NCON controls the voltages of the Q node and the QB node in response to the start pulse VST or the output of the previous stage. That is, the node control circuit NON charges or discharges the Q node with the start pulse VST or the output voltage of the previous stage in response to the i-1th clock signal CLK(i-1).

The reset circuit 131 controls the gate pulse output unit 133 to output a gate pulse or not to output a gate pulse with a voltage output through the output terminal Qout. For example, the reset circuit 131 discharges the output terminal Qout to a low potential voltage VSS so that the gate pulse output unit 133 does not output the gate pulse, and outputs a high level voltage to output the gate pulse output unit ( 133) is controlled to output a gate pulse.

The reset circuit 131 reduces the output voltage of the output terminal Qout to the low potential voltage VSS regardless of the potential of the Q node Q in response to the reset signal RST1 of the high level voltage provided during the driving preparation period. To discharge. Accordingly, the reset circuit 131 primarily initializes the output terminal Qout to an output voltage during the driving preparation period.

In addition, when the reset signal RST1 is a low-level voltage, the reset circuit 131 discharges the output terminal Qout to a low-potential voltage VSS according to the potential of the Q node, or the voltage level is variable through the output terminal Qout. Output control signal. The output control signal RST2 maintains the first voltage level during the non-display period and maintains the second voltage level during the display period. The first voltage level is a potential that does not operate the gate pulse output unit 133, and the second voltage level is a potential that operates the gate pulse output unit 133. For example, the first voltage level may be a low level voltage, and the second voltage level may be a high level voltage. Therefore, the reset circuit 131 outputs the output control signal RST2 of the first voltage level that does not operate the gate pulse output unit 133 through the output terminal Qout during the non-display period even if the reset signal RST1 is at a low level. do. That is, since the reset circuit 131 does not always operate the gate pulse output unit 133 to the output terminal Qout regardless of the potential of the Q node or the QB node during the non-display period, the Q node or the QB node during the non-display period It is possible to prevent the gate pulse output unit 133 from outputting the gate pulse due to noise of.

As such, the reset circuit 131 uses the output control signal RST2 whose voltage level is variable during the non-display period as a driving power source, so that the potential of the output terminal Qout can be secondarily stabilized without configuring a separate additional circuit. I can.

Conventionally, transistors for independent operations were required in a reset circuit for a primary initialization operation and a control circuit for limiting output during a non-display period. In addition, a combination of each independently driven transistor operated by receiving a reset signal independently.

On the contrary, the reset circuit 131 of the present invention divides the voltage level of the driving power into a display period and a non-display period and swings the output during the non-display period as well as the primary initialization operation in a state where a separate circuit configuration is not required. It is possible to perform a secondary stabilization operation limiting A detailed configuration and operation description of the reset circuit 131 will be described later.

The gate pulse output unit 133 outputs a gate pulse Gouti corresponding to the gate high voltage VGH according to the potential of the output terminal Qout of the reset circuit 131. The gate pulse output unit 133 does not output a gate pulse when the output terminal Qout of the reset circuit 131 is a low potential voltage, and does not output a gate pulse when the output terminal Qout of the reset circuit 131 is a high potential voltage. Output a pulse. Further, the gate pulse output unit 133 discharges the output voltage to a low potential voltage VSS in response to the potential of the QB node QB of the node control circuit NCON. For example, the gate pulse output unit 133 discharges the output voltage to a low potential voltage VSS when the potential of the QB node QB of the node control circuit NCON is a high potential voltage.

The gate pulse output unit 133 includes a pull-up transistor (Tpu) and a pull-down transistor (Tpd), and a combination of a pull-up transistor (Tpu) and a pull-down transistor (Tpd) is various Structure can be used. For example, the gate pulse output unit 133 may be implemented as shown in FIGS. 5A and 5B.

The gate pulse output unit 133 of the exemplary embodiment illustrated in FIG. 5A includes a pull-up transistor Tpu and a pull-down transistor Tpd. The pull-up transistor Tpu outputs the driving voltage Vdd provided through the drain electrode as a gate pulse Gout in response to the low level voltage of the Q node Q. The pull-down transistor Tpd discharges the voltage of the gate pulse output unit 133 to a low potential voltage VSS in response to the high level voltage of the Q node Q.

The gate pulse output unit 133 shown in FIG. 5B includes a pull-up transistor unit Tpu and a pull-down transistor Tpd. The pull-up transistor unit Tpu receives the clock signal CLKi through the drain electrode, and the pass-gate includes a p-type transistor and an n-type transistor. The pull-up transistor Tpu outputs the clock signal CLKi provided through the drain electrode as a gate pulse Gouti in response to the low level voltage of the Q node Q. The pull-down transistor Tpd discharges the voltage of the gate pulse output unit Gouti to a low potential voltage VSS in response to the high level voltage of the Q node Q.

6 is a circuit diagram showing a reset circuit according to the first embodiment, and FIG. 7 shows input and output signals of the stages ST1 to STn. The initialization and output stabilization operation of the reset circuit 131 and a process of outputting a gate pulse by the stages ST1 to STn will be described below with reference to FIGS. 3 to 7.

6, the reset circuit 131-1 according to the first embodiment receives a voltage of a Q node Q and a reset signal RST1, and receives a low potential voltage VSS or an output control signal RST2. Is output to the output terminal (Qout). The Q node Q is connected to the Q node Q of the node control circuit NCON, and the output terminal Qout is connected to the gate pulse output unit 133. The reset circuit 131-1 of the first embodiment outputs an output control signal when the potential of the Q node Q and the reset signal RST1 are both low levels.

To this end, the reset circuit 131-1 of the first embodiment includes first to fourth transistors constituting a NOR gate structure. That is, when the reset signal RST1 input to the gate electrode is at a high level, the first transistor T1 discharges the potential of the output terminal Qout to the low potential voltage VSS. The second transistor T2 is connected in parallel with the first transistor and discharges the potential of the output terminal Qout to the low potential voltage VSS when the Q node Q connected to the gate electrode is at a high level. The third and fourth transistors T4 are connected in series to each other, the third transistor T3 is turned on when the reset signal is at a low level, and the fourth transistor T4 has a Q node Q at a low level. When it is turned on. When the third and fourth transistors T4 are simultaneously turned on, the output control signal RST2 is output to the output terminal Qout through the third transistor T3.

As shown in FIG. 7, the display device has a driving preparation period for a certain period when power is supplied through a system (not shown). When a predetermined time Δt elapses after the driving preparation period, the data input signal DE and the clock signal CLK are input to have a display period for displaying an image. The non-display period includes a period in which an image is not actually displayed among the driving preparation period and the driving period. A section in which an image is not actually displayed during the driving period includes a section in which a touch signal is input or additional information other than image data is received.

The reset circuit 131-1 receives a high-level reset signal RST1 for a predetermined period within a driving preparation period. The first transistor T1 discharges the potential of the output terminal Qout to the low potential voltage VSS in response to the high-level reset signal RST1. At this time, even if the fourth transistor T4 is turned on due to the low potential voltage of the Q node Q, the third transistor T3 is turned off by the high-level reset signal RST1, so output control The current path between the signal RST2 and the output terminal Qout is blocked. That is, while the high-level reset signal RST1 is applied during the driving preparation period, the reset circuit 131 discharges the potential of the output terminal Qout to the low potential voltage VSS regardless of the potential of the Q node Q. do.

After the initialization operation is performed, the reset signal RST1 swings to a low-level voltage. In addition, during the non-display period before the clock signals CLK1 to CLK4 are input, the output control signal RST2 maintains the low level. During the non-display period after the initialization operation, the third transistor T3 is turned on by the low-level reset signal RST1. Since the non-display period is a period in which the gate pulse is not output, the node control circuit NCON controls the potential of the Q node Q to a high level voltage. Accordingly, the second transistor T2 of the reset circuit 131 discharges the potential of the output terminal Qout to the low potential voltage VSS in response to the low potential voltage of the Q node Q. If the Q node Q is charged to a low potential voltage due to abnormal noise, the fourth transistor T4 is turned on. That is, when abnormal noise occurs during the non-display period in which the third transistor T3 is turned on, the output control signal RST2 is output to the output terminal Qout via the third and fourth transistors T4. . However, since the output control signal RST2 has a low-level potential, the gate pulse output unit 133 does not output the gate pulse. Therefore, even if the Q node Q of the node control circuit NCON is a low level voltage due to abnormal operation or noise, the reset circuit 131-1 prevents the gate pulse output unit 133 from outputting the gate pulse. Can be controlled.

In other words, during the driving preparation period, the reset circuit 131-1 discharges the output terminal Qout of the reset circuit 131-1 to a low potential voltage VSS regardless of the potential of the Q node Q. Performs a typical initialization operation. Also, the reset circuit 131-1 prevents the gate pulse from being output regardless of the potential of the Q node Q based on the low-level output control signal RST2 during the non-display period.

In this way, the reset circuit 131-1 of the first embodiment receives the potentials of the reset circuit 131 and the Q node Q into one logic circuit, and converts the potential of the output terminal Qout to the low potential voltage VSS. Discharges or outputs an output control signal RST2 whose voltage level is variable. In particular, the output control signal RST2 separates the display period and the non-display period, and the output control signal RST2 input to the reset circuit 131-1 in the non-display period does not operate the gate pulse output unit 133. Maintain voltage level. Accordingly, the operation of initializing the stages ST1 to STn during the driving preparation period and the operation of limiting the output of the output terminal Qout during the non-display period can be implemented using a single logic circuit. Therefore, compared to the conventional method in which a circuit for the initialization operation and a circuit limiting the output of the output terminal Qout are individually configured and combined, the structure of the reset circuit 131 can be simplified and the number of semiconductor elements required can be reduced. have. The reset circuit 131-1 having a simplified structure as described above can reduce manufacturing cost and reduce the circuit size, thereby reducing the overall size of the shift register 130. That is, the display device of the present invention can reduce the size of the bezel, which is a non-display area on the panel, and is advantageous in using a large screen/high resolution display panel.

After the above non-display period, the gate shift clocks CLK1 to CLK4 are input to the level shifter 150. During the display period, the level shifter 150 level-shifts the logic level voltage of the four-phase gate shift clocks CLK1 to CLK4 input from the timing controller 110 to a gate high voltage VGH and a gate low voltage VGL. , Cyclic clocks sequentially delayed to the first to fourth gate shift clocks CLK1 to CLK4 are generated. During the display period, the reset signal RST1 maintains a low-level voltage level, and the output control signal RST2 swings from a low level to a high level. And during the display period, the node control circuit NCON of the first stage ST1 of the shift register 130 discharges the Q node Q with the output voltage of the gate start pulse VST.

During the display period, since the potentials of the reset signal RST1 and the Q node Q are at the low potential voltage level, the third and fourth transistors T4 of the reset circuit 131 are turned on, and the voltage of the high level is The output control signal RST2 is output to the output terminal Qout. In addition, the gate pulse output unit 133 of the first stage ST1 outputs the first gate pulse Gout1 in response to the high level output control signal RST2 provided from the reset circuit 131.

At the end of the first horizontal period t1, the node control circuit NCON charges the Q node Q in response to the first gate shift clock CLK1. Accordingly, the second transistor T2 of the reset circuit 131 outputs the low potential voltage VSS to the output terminal Qout, and the gate pulse output unit 133 applies the first gate pulse Gout1 to the low potential voltage. Discharge with (VSS).

Similarly, during the second horizontal period t2, the node control circuit NCON of the second stage ST2 receives the first gate pulse Gout1 output from the first stage ST1 as a carry signal, so that the Q node (Q) is discharged, and the gate pulse output unit 133 outputs a second gate pulse Gout2. Similarly, during the third and fourth horizontal periods t3 and t4, the shift register 130 outputs the third and fourth gate pulses Gout3 and Gout4.

8 and 9 show reset circuits according to the second and third embodiments, respectively. The reset circuits according to the second and third embodiments to be described later can perform the same operation according to the driving waveform shown in FIG. 7 as in the first embodiment described above.

Referring to FIG. 8, the reset circuit 131-2 according to the second embodiment receives the voltage of the Q node Q and the reset signal RST1, and outputs the output control signal RST2 to the output terminal Qout. Or discharge the potential of the output terminal Qout to a low potential voltage VSS. The Q node Q is connected to the Q node Q of the node control circuit NCON, and the output terminal Qout is connected to the gate pulse output unit 133. The reset circuit 131-2 of the second embodiment discharges the potential of the output terminal Qout to the low potential voltage VSS when the voltage of the Q node Q and the reset signal RST1 are both high levels.

To this end, the reset circuit 131-2 according to the second embodiment includes first to fourth transistors T21 to T24 forming a NOR gate structure. When the reset signal RST1 input to the gate electrode is at a low level, the first transistor T21 outputs the output control signal RST2 provided to the source electrode to the output terminal Qout through the drain electrode. The second transistor T22 is connected in parallel with the first transistor T21, and when the Q node Q connected to the gate electrode is at a low level, the output control signal RST2 provided to the source electrode is transmitted through the drain electrode. Output to the output terminal (Qout). The third and fourth transistors T23 and T24 are connected in series to each other, the third transistor T23 is turned on when the reset signal is at a high level, and the fourth transistor T24 has a Q node Q Turns on when at high level. When the third and fourth transistors T23 and T24 are simultaneously turned on, they output the output control signal RST2 to the output terminal Qout through the third transistor T23.

9, the reset circuit 131-3 according to the third embodiment receives the voltage of the Q node Q and the reset signal RST1, and outputs the output control signal RST2 to the output terminal Qout. Or discharge the potential of the output terminal Qout to a low potential voltage VSS. The Q node Q is connected to the Q node Q of the node control circuit NCON, and the output terminal Qout is connected to the gate pulse output unit 133.

The reset circuit 131-3 according to the third embodiment includes first to fourth transistors T31 and T34 connected in series with each other. The first transistor T31 is turned on in response to the high-level reset signal RST1, and the second transistor T32 is turned on by the high-level Q node (Q) potential. The first and second transistors T31 and T32 are adjacent and connected in series, so that when the potentials of the reset signal RST1 and the Q node Q are both high levels, the potential of the output terminal Qout is reduced to a low potential voltage ( VSS). The third transistor T33 is turned on in response to the low-level reset signal RST1, and the fourth transistor T34 is turned on by the low-level Q node Q potential. The third and fourth transistors T33 and T34 are adjacent and connected in series, so that when the potentials of the reset signal RST1 and the Q node Q are both low levels, the output control signal RST2 is output to the output terminal Qout. Output as

10 is a view showing the reset circuit 131-4 according to the fourth embodiment, the reset circuit 131-4 according to the fourth embodiment does not use the reset signal RST1, and other driving waveforms are shown in FIG. Same as shown.

Referring to FIG. 10, the reset circuit 131-4 of the fourth embodiment is a first transistor that outputs an output control signal RST2 to an output terminal Qout in response to a low potential voltage VSS of a Q node Q. And a second transistor T42 that discharges the output terminal Qout to a low potential voltage VSS in response to the high potential voltage of the Q node Q and T41. That is, regardless of the potential of the Q node Q, the reset circuit 131-4 of the fourth embodiment maintains the voltage of the output terminal Qout at a low potential during the non-display period. Accordingly, it is possible to prevent the gate pulse output unit 133 from outputting the gate pulse Gout during the non-display period due to an abnormal operation of the Q node Q.

As shown in FIG. 7, during the driving preparation period in which the reset signal RST1 is maintained at the high level, the output control signal RST2 is maintained at the low level. That is, even if the reset signal RST1 is not used, the reset circuit 131-4 uses the output control signal RST2 of which the voltage level is variable, and the gate pulse output unit 133 during the non-display period including the driving preparation period. ) Can be blocked from outputting the gate pulse Gout.

In the above-described embodiments, the non-display period has been described only for a driving preparation period and a certain period consecutive to the driving preparation period. However, the non-display period may include a period in which an image is not displayed for touch sensing within the driving period, and even in the non-display period inserted into the display period, the output control signal RST2 swings to a low level and the gate pulse ( Gout) output can be cut off.

In addition, although the reset circuit of the above-described embodiments is shown separately from the node control circuit, it is obvious that it can be implemented in an embodiment included in the node control circuit.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art. It will be appreciated that it can be implemented. Therefore, the embodiments described above are illustrative in all respects and should be understood as non-limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130: shift register
131: reset circuit 133: gate pulse output unit

Claims (10)

A display panel including a gate line; And
Including a shift register for supplying a gate pulse to the gate line,
The shift register is
A node control circuit for controlling potentials of the Q node and the QB node in response to the gate start pulse or the output of the previous stage;
During the non-display period, the output control signal of the first voltage level is applied and the output control signal of the second voltage level is applied during the display period, and the output control signal is output to the output terminal according to the potential of the Q node or the output terminal is discharged A reset circuit; And
A gate pulse output unit that does not output the gate pulse in response to the output control signal of the first voltage level and outputs the gate pulse in response to the output control signal of the second voltage level,
The reset circuit receives a low potential voltage and the output control signal, outputs the output control signal when the Q node is a low potential voltage, and discharges the output terminal to a low potential voltage when the Q node is a high potential voltage. Thus, the gate pulse is controlled not to be output,
The reset circuit receives a reset signal during a driving preparation period, and discharges the output terminal to a low potential voltage in response to the reset signal.
delete The method of claim 1,
The reset circuit operates as different carriers and includes first and second transistors connected in series with each other,
The output control signal is input to the source electrode of the first transistor, the low potential voltage is input to the source electrode of the second transistor, and the voltage of the Q node is applied to the gate electrodes of the first and second transistors, respectively. Entered,
A display device configured to output the output control signal to the drain electrodes of the first and second transistors or to discharge nodes of the drain electrodes.
delete The method of claim 1,
The reset circuit is
A display device in the form of a NOR gate for outputting the output control signal when both the Q node potential and the reset signal are at low levels.
The method of claim 5,
The reset circuit is
A first transistor configured to output the low potential voltage provided to the source electrode to the drain electrode when the reset signal input to the gate electrode is at a high level;
A second transistor connected in parallel with the first transistor and configured to output the low potential voltage provided as a source electrode to a drain electrode when the Q node connected to the gate electrode is at a high level;
A third transistor turned on when the reset signal input to the gate electrode is at a low level; And
The third transistor is connected in series and turned on when the Q node connected to the gate electrode is at a low level to provide the output control signal input to the source electrode to the source electrode of the third transistor. A display device including a fourth transistor that outputs the output control signal through the third transistor when turned on simultaneously with the three transistors.
The method of claim 1,
The reset circuit is
A display device in the form of a NAND gate that discharges the output terminal to a low potential voltage when both the Q node potential and the reset signal are high levels.
The method of claim 7,
The reset circuit is
A first transistor configured to output the output control signal provided to the source electrode to the drain electrode when the reset signal input to the gate electrode is at a low level;
A second transistor connected in parallel with the first transistor and configured to output the output control signal received from a source electrode to a drain electrode when the Q node connected to the gate electrode is at a low level;
A third transistor turned on when the reset signal input to the gate electrode is at a high level; And
The third transistor is connected in series and is turned on when the Q node connected to the gate electrode is at a high level to provide the low potential voltage input to the source electrode to the source electrode of the third transistor. A display device including a fourth transistor that discharges the output terminal to a low potential voltage when turned on at the same time as the three transistors.
The method of claim 1,
The reset circuit is
When both the Q node potential and the reset signal are high levels, the low potential voltage is output,
The display device outputs the output control signal when both the Q node potential and the reset signal are at low levels.
The method of claim 9,
First and second transistors connected in series with each other, each of which discharges the output terminal to a low potential voltage in response to the reset signal of a high level and the potential of the Q node of a high level; And
A display device comprising third and fourth transistors connected in series with each other and each outputting the output control signal in response to the reset signal of the low level and the potential of the Q node of the Lowry Bell.

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