KR102142477B1 - Array substrate and method of fabricating the same - Google Patents

Abstract

The present invention includes a substrate in which a plurality of pixel regions are defined; A gate electrode formed in each of the plurality of pixel regions on the substrate; A gate insulating film formed on the entire surface of the substrate over the gate electrode; An oxide semiconductor layer formed on the gate insulating layer and corresponding to the gate electrode, respectively; A buffer pattern formed on the oxide semiconductor layer and having a metal silicide region and an amorphous silicon region having conductor characteristics; Provided is an array substrate including a source electrode and a drain electrode formed in contact with the metal silicide region over the buffer pattern and spaced apart from each other, and a method of manufacturing the same.

Description

Array substrate and method of fabricating the same}

The present invention relates to an array substrate, in particular, an array substrate including a thin film transistor capable of minimizing parasitic capacitance and reducing the area by implementing a short channel with an oxide semiconductor layer having excellent device characteristics and stability, and a method for manufacturing the same It is about.

2. Description of the Related Art In recent years, as the society has entered a full-fledged information age, the display field for processing and displaying a large amount of information has rapidly developed, and in response, various various flat panel display devices have been developed and attracting attention.

Specific examples of such a flat panel display device include a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an electroluminescent display device (Electroluminescence Display device: ELD), etc. These flat panel display devices show excellent performance in thinning, lightening, and low power consumption, rapidly replacing the existing cathode ray tube (CRT).

Among them, the liquid crystal display device is used in various fields such as laptops, monitors, and TVs because it has a high contrast ratio, is suitable for moving picture display, and has low power consumption. Its principle of image implementation is the optical anisotropy of liquid crystals. By using hyperpolarizability, the liquid crystal has an optical anisotropy with a long, long molecular structure and directionality in the array, and a polarization property in which the molecular alignment direction changes according to its size when placed in an electric field.

In addition, the organic light emitting device has a high luminance and a low operating voltage characteristic, and since it is a self-emission type that emits light by itself, a contrast ratio is large, an ultra-thin display can be implemented, and a response time is several microseconds ( Iv) It is recently attracting attention as a flat panel display device because it is easy to implement moving images, has no limitation of viewing angle, is stable even at low temperatures, and is driven by a low voltage of 5 to 15 V DC, making it easy to manufacture and design a driving circuit.

In such a liquid crystal display device and an organic light emitting device, an array substrate having a thin film transistor, which is essentially a switching element, is configured to remove on/off each pixel area in common.

Looking at the array substrate having such a configuration, gates and data wirings that define a plurality of pixel areas intersecting each other are provided, and each pixel area has at least one or two or more thin film transistors serving as switching and driving elements. It is provided.

Meanwhile, the thin film transistors provided in each pixel region of the array substrate have various structures according to the constituent materials constituting the semiconductor layer, which is one component thereof.

That is, the semiconductor layer may be formed of any one of amorphous silicon, oxide semiconductor material, and polysilicon, and a thin film transistor having a top gate or bottom gate structure is formed on the array substrate according to the material forming the semiconductor layer.

Of these thin film transistors having semiconductor layers made of various semiconductor materials, interest has recently been focused on array substrates including thin film transistors equipped with oxide semiconductor layers made of oxide semiconductor materials.

In the case of a thin film transistor including an oxide semiconductor layer, compared to a thin film transistor having amorphous silicon as a semiconductor layer, the carrier has excellent conductivity characteristics, and doping of impurities is required as an essential process. This is because the manufacturing process is simple compared to the thin film transistor having a layer.

1 is a cross-sectional view of one pixel region of an array substrate including a thin film transistor having a conventional oxide semiconductor layer.

As illustrated, the array substrate 71 including the thin film transistor Tr1 having the conventional oxide semiconductor layer 77 includes a gate electrode 73, a gate insulating film 75, and a single-layer oxide semiconductor layer ( 77) and the etch stopper 79 and the source and drain electrodes 81 and 83 spaced apart from each other on the etch stopper 79.

At this time, corresponding to the central portion of the oxide semiconductor layer 77 is provided with the etch stopper 79 is the oxide semiconductor layer 77 is made of a metal material for forming the source and drain electrodes 81, 83 When exposed to an etchant for patterning a metal layer (not shown), the metal layer (not shown) has no selectivity and is removed by etching. Alternatively, the internal structure of the oxide semiconductor layer 77 may be damaged by exposure to the etchant, thereby affecting the properties of the thin film transistor Tr1 including the same, and to prevent this.

That is, in order to prevent the central portion of the oxide semiconductor layer 77 from being exposed to an etchant during patterning for forming the source and drain electrodes 81 and 83, an inorganic insulating material is formed on the central portion of the oxide semiconductor layer 77. It is equipped with an etch stopper (79).

However, when manufacturing the array substrate 71 including the oxide semiconductor layer 77 and the thin film transistor Tr1 provided with the etch stopper 79 thereon, once for forming the etch stopper 79 A mask process is being added.

Since the mask process includes a total of 5 unit processes of photoresist application, exposure using an exposure mask, development of exposed photoresist, etching, and strip, the process is complicated and many chemicals are used. As it increases, the production time becomes longer, and the productivity per unit time is charged, the frequency of occurrence of defects increases, and the manufacturing cost increases.

Therefore, in the case of the conventional array substrate 71 having the oxide semiconductor layer 77 and the etch stopper 79, it is required to reduce the manufacturing cost by reducing the mask process.

In addition, when manufacturing the conventional array substrate 71 having the oxide semiconductor layer 77 and the etch stopper 79, the process margin and the etch stopper 79, the oxide semiconductor layer ( 77), the channel length of the thin film transistor Tr1 is increased because exposure misalignment margin must be considered when patterning between the source and drain electrodes 81 and 83.

In addition, the source and drain electrodes 81 and 83 are etched to prevent the oxide semiconductor layer 77 located outside the etch stopper 79 from being exposed to the etching solution for patterning the source and drain electrodes 81 and 83. It should be formed so as to overlap with (79). For this, the source and drain electrodes 81 and 83 must be formed so that the source and drain electrodes 81 and 83 have a relatively large area in consideration of misalignment during exposure. The overlapping area between the gate electrode 73 and the gate electrode 73 increases, and thus the parasitic capacitance Cgs increases, which is a factor that deteriorates the characteristics of the thin film transistor Tr.

The present invention is to solve the above-mentioned problems, while preventing the oxide semiconductor layer from being damaged by an etchant for patterning a metal material, an oxide semiconductor layer capable of reducing manufacturing cost by reducing a single mask process and simplifying the process An object of the present invention is to provide an array substrate having a method and a method for manufacturing the same.

Furthermore, while implementing a short channel, by reducing the area where the source and drain electrodes and the gate electrode overlap, thereby reducing parasitic capacitance, an array substrate with an oxide semiconductor layer capable of improving the characteristics of the thin film transistor and a method of manufacturing the same are provided. The purpose is to do.

An array substrate according to an embodiment of the present invention for achieving the above object, a plurality of pixel areas are defined substrate; A gate electrode formed in each of the plurality of pixel regions on the substrate; A gate insulating film formed on the entire surface of the substrate over the gate electrode;

An oxide semiconductor layer formed on the gate insulating layer and corresponding to the gate electrode, respectively; A buffer pattern formed on the oxide semiconductor layer and having a metal silicide region and an amorphous silicon region having conductor characteristics; It is formed in contact with the metal silicide region over the buffer pattern and includes a source electrode and a drain electrode spaced apart from each other.

At this time, the buffer pattern is characterized in that formed in each element region in the form of an island, and the buffer pattern is characterized in that the portion corresponding to the separation region of the source electrode and the drain electrode forms the amorphous silicon region.

And a gate wiring extending in one direction on the boundary of the pixel region on the substrate; A data wiring defining the pixel area by intersecting the gate wiring through a metal silicide pattern is further provided on the gate insulating layer.

In addition, the buffer pattern is formed on the entire surface of the substrate to form a buffer layer, the gate wiring extending in one direction to the boundary of the pixel region on the substrate; A data line defining the pixel area crossing the gate line is further provided on the buffer layer, and the data line is formed in contact with the metal silicide area.

In addition, the buffer layer is formed in the amorphous silicon region except for regions in which the source and drain electrodes and the data wiring are formed.

On the other hand, the source and drain electrodes are in contact with the metal silicide region is characterized in that it is made of any one of molybdenum (Mo), titanium (Ti), molybdenum (MoTi).

In addition, the source and drain electrodes are formed of a single layer structure made of any one of the molybdenum (Mo), titanium (Ti), and molybdenum (MoTi), or the molybdenum (Mo), titanium (Ti), molybdenum A double layer structure of the first layer made of any one of titanium (MoTi) and the second layer made of any one of low resistance metal materials such as copper (Cu), copper alloy, aluminum (Al), and aluminum alloy (AlNd) Characterized in that, furthermore, the source and drain electrodes are further provided with a third layer made of any one of the molybdenum (Mo), titanium (Ti), and molybdenum (MoTi) on the second layer, a triple layer structure It is characterized by making.

In addition, a protective layer formed on the entire surface of the substrate over the source and drain electrodes and having a drain contact hole exposing the drain electrode; And a pixel electrode provided in the pixel area in contact with the drain electrode through the drain contact hole over the protective layer.

And the buffer pattern is characterized in that 10 to 200 Å.

A method of manufacturing an array substrate according to an embodiment of the present invention includes forming a gate electrode in each of the plurality of pixel regions on a substrate on which a plurality of pixel regions are defined; Forming a gate insulating film on the entire surface of the substrate over the gate electrode; Forming an island-type oxide semiconductor layer corresponding to the gate electrode over the gate insulating layer; Sequentially forming an amorphous silicon layer and a first metal layer on the entire surface of the substrate over the oxide semiconductor layer; Patterning the first metal layer and the amorphous silicon layer to form source and drain electrodes spaced apart from each other in each pixel region, and island-type buffer patterns below the source and drain electrodes; Forming a protective layer on the entire surface of the substrate over the source and drain electrodes; And performing a heat treatment process on the substrate on which the protective layer is formed, such that a portion in contact with the source and drain electrodes of the buffer pattern forms a metal silicide region.

In this case, forming the source and drain electrodes spaced apart from each other in each pixel region by patterning the first metal layer and the amorphous silicon layer, and forming an island-type buffer pattern below the source and drain electrodes may be performed on the first metal layer. Forming a first photoresist pattern of one thickness and a second photoresist pattern of a second thickness thinner than the first thickness; A source drain pattern having the same plane shape as the buffer pattern over the buffer pattern and the buffer pattern by removing the first metal layer exposed outside the first and second photoresist patterns and the amorphous silicon layer positioned under the first metal layer. Forming a; Exposing the central portion of the source drain pattern by removing ashing and removing the second photoresist pattern; Forming the source and drain electrodes spaced apart from each other by removing a central portion of the source drain pattern exposed outside the first photoresist pattern; And removing the first photoresist pattern.

In addition, the forming of the gate electrode includes forming a gate line extending in one direction at the boundary of each pixel area, and forming an island-type buffer pattern under the source and drain electrodes and the source and drain electrodes. The step of forming includes interposing an amorphous silicon pattern over the gate insulating layer to form a data wiring crossing the gate wiring and defining the pixel region.

At this time, the amorphous silicon pattern is characterized in that it is converted to metal silicide by the heat treatment process.

A method of manufacturing an array substrate according to another embodiment of the present invention includes forming a gate electrode in each of the plurality of pixel areas on a substrate on which a plurality of pixel areas are defined; Forming a gate insulating film on the entire surface of the substrate over the gate electrode; Forming an island-type oxide semiconductor layer corresponding to the gate electrode over the gate insulating layer; Forming an amorphous silicon layer on the entire surface of the substrate over the oxide semiconductor layer; Forming source and drain electrodes spaced apart from each other corresponding to the oxide semiconductor layer in each pixel region over the amorphous silicon layer; Forming a protective layer on the entire surface of the substrate over the source and drain electrodes; And performing a heat treatment process on the substrate on which the protective layer is formed, such that a portion of the amorphous silicon layer that contacts the source and drain electrodes forms a metal silicide region.

At this time, the forming of the gate electrode includes forming a gate wiring extending in one direction at the boundary of each pixel region, and forming the source and drain electrodes crosses the gate wiring over the amorphous silicon layer. And forming a data line defining the pixel area.

On the other hand, the amorphous silicon layer is characterized in that it is formed to have a thickness of 10 to 200 ,, wherein the heat treatment process is characterized by proceeding for 5 to 120 minutes in a temperature atmosphere of 400 to 600 ℃.

In addition, the source and drain electrodes are in contact with the metal silicide region is characterized in that any one of molybdenum (Mo), titanium (Ti), molybdenum (MoTi), wherein the source and drain electrodes, the molybdenum (Mo), titanium (Ti), to form a single-layer structure made of any one of the material of the molybdenum (MoTi), or any of the molybdenum (Mo), titanium (Ti), molybdenum (MoTi) material The first layer is made of a low-resistance metal material such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy (AlNd) of the second layer consisting of a double layer structure, or the first layer and the second layer In addition, a third layer made of any one of the molybdenum (Mo), titanium (Ti), and molybdenum (MoTi) is further provided on the second layer to form a triple layer structure.

The present invention, while forming a thin film transistor including an oxide semiconductor layer without a separate etch stopper, so that the oxide semiconductor layer is not affected when patterning the source and drain electrodes, damage to the oxide semiconductor layer does not occur, thereby reducing the characteristics of the thin film transistor. It has an inhibitory effect.

In addition, since the present invention can omit the etch stopper, it is possible to omit one mask process compared to the manufacturing process of the array substrate with a conventional etch stopper, thereby reducing the number of mask processes and simplifying the process.

In addition, by omitting the etch stopper, it is possible to reduce the area of the source and drain electrodes formed overlapping with this, and further, to reduce the channel length, there is an effect of realizing a short channel.

Furthermore, when the thin film transistor forms a short channel, since the on current increases and the voltage for channel formation decreases, it has the effect of reducing power consumption by reducing the driving voltage, and furthermore, the thin film transistor reduces the channel area. As the area is reduced, the area occupied by the thin film transistor in the pixel area decreases, thereby improving the aperture ratio.

In addition, since the area of the source and drain electrodes is reduced by omitting the etch stopper, the overlapping area with the gate electrode can be reduced to reduce parasitic capacitance (Cgs), thereby improving the characteristics of the thin film transistor.

1 is a cross-sectional view of one pixel region of an array substrate having a thin film transistor having a conventional oxide semiconductor layer.
2 is a cross-sectional view of one pixel region of an array substrate provided with an oxide semiconductor layer according to a first embodiment of the present invention.
FIG. 3 is a plan view of a thin film transistor of an array substrate according to a first embodiment of the present invention and a plan view of a thin film transistor of a conventional array substrate, characterized in that an etch stopper is formed as a comparative example.
4A to 4N are cross-sectional views of manufacturing steps for one pixel region including a thin film transistor of an array substrate provided with an oxide semiconductor layer according to a first embodiment of the present invention.
5 is a cross-sectional view of one pixel region of an array substrate provided with an oxide semiconductor layer according to a second embodiment of the present invention.
6A to 6E are cross-sectional views of manufacturing steps for one pixel region including a thin film transistor of an array substrate provided with an oxide semiconductor layer according to a second embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

2 is a cross-sectional view of one pixel region of an array substrate provided with an oxide semiconductor layer according to a first embodiment of the present invention. At this time, for convenience of description, a region in which a thin film transistor is formed in each pixel region is defined as a device region TrA.

As illustrated, in the array substrate 101 according to the first embodiment of the present invention, a thin film transistor Tr2 having an oxide semiconductor layer 120 is provided in the element region TrA in each pixel region P. Is becoming.

At this time, the thin film transistor Tr2 provided with the oxide semiconductor layer 120 is characterized in that the etch stopper is omitted, and is formed by being patterned together with the source and drain electrodes 133 and 136 without a separate additional mask process. Characterized in that it is provided on the upper portion of the oxide semiconductor layer 120, the portion in contact with the source and drain electrodes (133, 136) is made of metal silicide having conductivity characteristics, and the source and drain electrodes (133) , 136) is characterized by being provided with an island-shaped buffer pattern 125, characterized in that it is made of amorphous silicon.

That is, the thin film transistor Tr2 includes a gate electrode 105, a gate insulating layer 110, an oxide semiconductor layer 120, and a buffer pattern 125 partially having conductive properties, and source and drain electrodes 133 spaced apart from each other. 136) is characterized by forming a stacked configuration.

In the thin film transistor Tr2 having such a configuration, the buffer pattern 125 partially has non-conductor or semiconducting properties, and another part has conductive properties in contact with the source and drain electrodes 133 and 136. It is made of matter.

That is, the buffer pattern 125 is made of amorphous silicon having non-conductor or semiconductor characteristics for a portion forming the channel of the oxide semiconductor layer 120, and the portion in contact with the source and drain electrodes 133 and 136 is the Amorphous silicon is changed to be made of metal silicide having conductive properties.

Therefore, the buffer pattern 125 having such a configuration is formed by the same mask process when the source and drain electrodes 133 and 136 are formed, and thus does not require an additional mask process, and furthermore, the source and drain electrodes 133 and 136 When formed, it serves as an etch stopper to prevent the etching solution used during patterning of the metal layer forming it from penetrating into the oxide semiconductor layer 120, thereby suppressing the deterioration of the properties of the thin film transistor Tr2.

A portion of the buffer pattern 125 that contacts the source and drain electrodes 133 and 136 is made of metal silicide having conductive properties, and the metal silicide region 125a made of the metal silicide is the oxide semiconductor layer 120 It has a higher conductivity characteristic and a smaller conductivity characteristic than the source and drain electrodes 133 and 136, thus forming an ohmic region between the source and drain electrodes 133 and 136 and the oxide semiconductor layer 120 to lower contact resistance. By acting as a role, the driving characteristics of the thin film transistor in which the oxide semiconductor layer directly contacts the source and drain electrodes are improved.

In addition, since the thin film transistor Tr2 having such a configuration does not have a separate etch stopper, the source and drain electrodes 133 and 136 are not required because exposure misalignment margin, etc., which are required by the etch stopper are not considered. Since the area of itself becomes small, and the portion overlapping with the gate electrode 105 naturally decreases, the parasitic whose size is proportional to the area where the gate electrode 105 and the source and drain electrodes 133 and 136 overlap. As the capacity Cgs is reduced, the characteristics of the thin film transistor Tr2 itself is improved.

Furthermore, since there is no ES stopper, since the separation region itself between the source and drain electrodes 133 and 136 becomes a region where a channel is formed, an etch stopper is provided, so that the width of the etch stopper becomes a channel region, compared to the conventional thin film transistor Tr2. It has the advantage of forming a short channel.

When the thin film transistor Tr2 forms a short channel, the on current increases, thereby reducing the voltage for channel formation, thereby reducing power consumption by reducing the driving voltage, and further reducing the channel area. As the area of the thin film transistor Tr2 is reduced, the area occupied by the thin film transistor Tr2 in the pixel area P is reduced, thereby improving the aperture ratio.

FIG. 3 is a plan view of a thin film transistor of an array substrate according to a first embodiment of the present invention and a plan view of a thin film transistor of a conventional array substrate, characterized in that an etch stopper is formed as a comparative example.

As shown, in the case of the thin film transistor Tr1 provided on the array substrate 71 according to the comparative example, an etch stopper 79 is provided, in which case the ends facing each other are process errors such as exposure process and etch bias. Even if occurs, the width of the source electrode 81 and the drain electrode 83 is formed to be larger by a, respectively, in order to overlap the etch stopper 79, respectively.

Therefore, in the case of the array substrate 71 according to the comparative example, it can be seen that the final thin film transistor Tr1 increases in area.

However, in the case of the array substrate 101 according to the first embodiment of the present invention, in the thin film transistor Tr2, the etch stopper is omitted, and instead, the buffer pattern 125 patterned simultaneously with the source and drain electrodes 133 and 136 is provided. It is provided.

At this time, the buffer pattern 125 is formed by patterning simultaneously with the source and drain electrodes 133 and 136, and it is not necessary to consider exposure misalignment errors and the like, and the source and drain electrodes 133 are necessarily overlapped by the etch stopper being omitted. Since 136 is not necessary, a width margin for overlapping one end of each of the etch stopper 79 and the source and drain electrodes 81 and 83 as in the array substrate 71 according to the comparative example is omitted. Can.

Therefore, in the array substrate 101 according to the first embodiment of the present invention, the thin film transistors Tr2 have the area of the source and drain electrodes 133 and 136 as much as a width compared to the thin film transistors Tr1 according to the comparative example. Since it can be formed small, it is relatively characteristic that the area of the thin film transistor Tr2 in each pixel area can be reduced.

In addition, since the area of the source and drain electrodes 133 and 136 is reduced by the progress of this process, the overlapping area with the gate electrode 105 is also relatively small, so the source electrode 136, the gate electrode 105, and the drain electrode Since the parasitic capacitance Cgs generated by the overlapping of the 138 and the gate electrode 105 can be reduced, the characteristics of the thin film transistor Tr2 can be improved.

Meanwhile, referring to FIG. 2, a protective layer 140 having a drain contact hole 143 covering the thin film transistor Tr2 having this configuration and exposing the drain electrode 136 of the thin film transistor Tr2 is provided. And the pixel electrode 150 contacting the drain electrode 136 through the drain contact hole 143 over the protective layer 140 is formed for each pixel region P, and thus the first embodiment of the present invention. It forms an array substrate 101 according to.

The array substrate 101 having such a configuration may be an array substrate for a liquid crystal display that performs various driving, or may be an array substrate for an organic light emitting device.

At this time, when the array substrate 101 forms an array substrate for a liquid crystal display device, the shape of the pixel electrode 150 may be variously modified.

For example, a common electrode (not shown) may be formed on the protective layer 140 to be further spaced apart from the pixel electrode 150, or the pixel electrode 150 and the insulating layer (not shown) may be formed. A common electrode (not shown) is provided through, and among the pixel electrode 150 and the common electrode (not shown), components provided on the insulating layer (not shown) are provided in a plurality of bar shapes. An opening (not shown) may also be provided.

In addition, when the array substrate 101 forms an array substrate for an organic light emitting device, an organic emission layer (not shown) and a counter electrode (not shown) may be further provided on the pixel electrode 150, and each pixel region A bank (not shown) may be further provided at the boundary of (P).

Hereinafter, a method of manufacturing an array substrate according to a first embodiment of the present invention having the above-described configuration will be described.

4A to 4K are process cross-sectional views of manufacturing steps for one pixel area including a thin film transistor of an array substrate provided with an oxide semiconductor layer according to a first embodiment of the present invention. In this case, for convenience of description, a portion in which the thin film transistor Tr2 in each pixel area P is to be formed is defined as a device area TrA.

First, as shown in FIG. 4A, a transparent insulating substrate 101, for example, a metal material having low resistance properties on a substrate made of glass or plastic, for example, copper (Cu), copper alloy, aluminum (Al) , By depositing one or more materials selected from aluminum alloy (AlNd), molybdenum (Mo) and molybdenum alloy (MoTi), a first metal layer (not shown) having a single-layer or multi-layer structure is formed.

Subsequently, photoresist is applied to the first metal layer (not shown), exposure using an exposure mask, development of the exposed photoresist, etching of the first metal layer (not shown), and a series of strips of photoresist. By forming and patterning a mask process including a unit process of, a gate line (not shown) extending in one direction is formed at a boundary of the pixel area P, and at the same time, the gate line ( (Not shown) to form a gate electrode 105.

In the drawing, although the gate wiring (not shown) and the gate electrode 105 are both made of a single layer structure as an example, these components may form a multi-layer structure.

Next, as shown in FIG. 4B, a gate insulating film is formed on the front surface by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) over the gate wiring (not shown) and the gate electrode 105. (110) is formed.

Next, as illustrated in FIG. 4C, an oxide semiconductor material, for example, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), zinc oxide (ZnO) over the gate insulating layer 110 Either one of them is deposited or applied to form an oxide semiconductor material layer (not shown).

Thereafter, a mask process is performed on the oxide semiconductor material layer (not shown) to pattern the island-shaped oxide semiconductor layer 120 corresponding to the gate electrode 105 in each device region TrA.

Next, as illustrated in FIG. 4D, an amorphous silicon layer 123 is formed on the entire surface of the substrate 101 by depositing amorphous silicon over the oxide semiconductor layer 120. At this time, the amorphous silicon layer 123 is characterized in that the thickness is 10 to 200 Å.

The amorphous silicon layer 123 is the most characteristic component of the array substrate 101 according to the first embodiment of the present invention, and a portion in contact with the source and drain electrodes (133, 136 of FIG. 4N) is a metal silicide region. If it is thicker than 200Å, it is not easy to convert the entire surface of the amorphous silicon layer 123 into a metal silicide region, and when it is thinner than 10Å, a portion in which the channel in the oxide semiconductor layer 120 is formed, that is, Inhibition of penetration of the etchant may be reduced in the region between the source and drain electrodes 133 and 136.

Therefore, the amorphous silicon layer 123 preferably has a thickness of 10 to 200 mm 2.

Next, a metal capable of forming a metal silicide having conductivity characteristics by reacting with the amorphous silicon layer 123 when heat treatment is performed at a predetermined temperature over the amorphous silicon layer 123 having a thickness of 10 to 200 MPa, for example, molybdenum (Mo ), titanium (Ti), or any one of molybdenum (MoTi) to be deposited alone to form a second metal layer 128 having a single-layer structure, or the molybdenum (Mo), titanium (Ti), and molybdenum (MoTi) ) By depositing any one of the metal material having a low-resistance properties, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy (alNd) by depositing any one of the second metal layer of the double layer structure ( 128).

At this time, when the second metal layer 128 forms a double-layer structure, it is possible to form a triple layer structure by depositing any one of the molybdenum (Mo), titanium (Ti), and molybdenum titanium (MoTi) on the top again. .

In the second metal layer 128 having the single-layer, double-layer, and triple-layer structures, any one of molybdenum (Mo), titanium (Ti), and molybdenum titanium (MoTi) is used as the metal directly contacting the amorphous silicon layer 123. It is characterized by being.

In the drawing, it is shown that the second metal layer 128 is formed of any one of molybdenum (Mo), titanium (Ti), and molybdenum titanium (MoTi), for example.

Next, as shown in FIG. 4F, a photoresist is formed over the second metal layer 128 to form a photoresist layer 190, and the light transmissive area TA is blocked over the photoresist layer 190. After placing the exposure mask 195 having the area BA and the semi-transmissive area HTA, diffraction exposure or halftone exposure using the exposure mask 195 is performed.

In this case, the semi-transmissive area HTA of the exposure mask 195 is a central portion of the gate electrode 105 in each device region TrA, that is, a portion in which the channel is formed in the oxide semiconductor layer 120 later. The transmission area BA is positioned to correspond to the portion where the data wiring (130 of FIG. 4N) and the source and drain electrodes (133, 136 of FIG. 4N) are to be formed. The area allows the blocking area BA to correspond.

In this case, the positions of the transmissive area TA and the blocking area BA of the exposure mask 195 may be changed depending on the properties of the photoresist layer 190.

In the first embodiment of the present invention, as an example, the photoresist layer 190 is shown to have a negative type property in which the lighted portion remains after development, and the photoresist layer is removed after the lighted portion is developed. It is also possible to use a material having a potential type property.

Next, as shown in FIG. 4G, the development of the exposed photoresist layer (190 in FIG. 4F) further progresses data wiring (130 in FIG. 4N) and source and drain electrodes (133 and 136 in FIG. 4N). For the portion to be formed, a first photoresist pattern 191a having a first thickness is formed, and a spaced area between the source and drain electrodes (133 and 136 of FIG. 4N), that is, each oxide semiconductor layer 120 ), a second photoresist pattern 191b having a second thickness thinner than the first thickness is formed in the region where the channel is formed, and the photoresist layer (190 in FIG. 4F) is removed for other regions. To expose the second metal layer 128.

Next, as shown in FIG. 4H, the second metal layer (128 of FIG. 4G) exposed outside the first and second photoresist patterns 191a and 191b and the amorphous silicon layer positioned below it (FIG. By continuously etching and patterning 123 of 4g, a data line 130 defining a pixel area P crossing the gate line (not shown) corresponding to the boundary of each pixel area P is formed, and at the same time In each element region TrA, a source drain pattern 129 connected to each other is formed at this stage.

In this case, a first amorphous silicon pattern 124a having the same planar shape as the source drain pattern 129 is formed under the source drain pattern 129, and the data wiring 130 is also formed under the data wiring 130. A second amorphous silicon pattern 124b having the same planar shape as is formed.

Next, as shown in FIG. 4I, the ashing is performed to remove the second photoresist pattern (191b in FIG. 4H) of the second thickness to remove the source drain pattern 129 in each device region TrA. ).

At this time, the thickness of the first photoresist pattern 191a is also reduced by the ashing, but still remains on the first and second amorphous silicon patterns 124a and 124b.

Next, as shown in FIG. 4J, on the first amorphous silicon pattern 124a by etching the exposed source drain pattern (129 in FIG. 4I) by removing the second photoresist pattern (191b in FIG. 4H). Source electrodes 133 and drain electrodes 136 spaced from each other are formed.

At this time, the oxide semiconductor layer 120 is provided with the first amorphous silicon pattern 124a on top of it to serve as an etch stopper, so that the source drain pattern (129 in FIG. 4I) is exposed to the etchant used for etching. Things are prevented.

Therefore, the oxide semiconductor layer 120 is not affected by the etching solution for etching the source drain pattern (129 in FIG. 4I).

Next, as shown in FIG. 4K, the data wiring 130 and the source and drain electrodes 133 and 136 are exposed by stripping to remove the first photoresist pattern (191b in FIG. 4J ). Order.

Subsequently, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the source and drain electrodes 133 and 136 and the data wiring 130 to protect the entire surface of the substrate 101 ( 140).

Next, as shown in FIG. 4L, the substrate in the state where the protective layer 140 is formed on the front surface is placed in a heat treatment device 198, for example, in an oven or furnace, or heated. After being placed on a means (not shown), a heat treatment process of heating the substrate to a temperature of 400 to 600°C is performed.

At this time, the heat treatment process is preferably performed for 5 to 120 minutes.

Part of the first amorphous silicon pattern (124a in FIG. 4K) contacting the source and drain electrodes 133 and 136 by the heat treatment process is molybdenum (among the metal materials forming the source and drain electrodes 133 and 136) Mo), titanium (Ti), or a material of any of titanium (MoTi) is diffused into the first amorphous silicon pattern (124a in FIG. 4K), thereby changing to a metal silicide region 125a having conductor characteristics.

Therefore, the island-shaped first amorphous silicon pattern (124 in FIG. 4K) provided in each device region TrA has a metal silicide region in contact with the source and drain electrodes 133 and 136 after the heat treatment process is performed. A buffer pattern 125 forming 125a and forming an amorphous silicon region 125b is formed in a space between the source and drain electrodes 133 and 136.

In the heat treatment process, since the portion of the first amorphous silicon pattern (124a of FIG. 4K) contacting the source and drain electrodes 133 and 136 must be provided with conductor characteristics, that is, the source and drain electrodes 133 and 136 ), the portion in contact with the metal silicide should be converted, so the heat treatment process time is appropriately adjusted according to the thickness of the first amorphous silicon pattern (124a in FIG. 4K).

On the other hand, the second amorphous silicon pattern (124b in FIG. 4K) provided under the data wiring 130 is also converted to metal silicide by the heat treatment process, thereby forming the metal silicide pattern 126, and finally, the metal silicide Since the site pattern 126 is configured to be in contact with the data wiring 130, it is substantially a component of the data wiring 130, thereby helping the data wiring 130 to form a multi-layer structure.

Therefore, in this case, the data wiring 130 has a metal silicide pattern 126 at its lowermost layer, and a layer composed of any one of minimum molybdenum (Mo), titanium (Ti), and molybdenum titanium (MoTi) is provided as a double layer. A low-resistance metal material such as copper (Cu), copper alloy, or aluminum (Al), in addition to the upper part of the layer consisting of molybdenum (Mo), titanium (Ti), or molybdenum (MoTi) in addition to the structure or the double-layer structure ), a layer made of any one of aluminum alloys (AlNd) is further provided to form a triple layer structure, or the layer made of any one of molybdenum (Mo), titanium (Ti), or molititanium (MoTi) in the triple layer structure It is also provided again to form a quadruple structure.

Meanwhile, through the heat treatment process, the source electrode 133, the oxide semiconductor layer 120, and the drain electrode 136 and the oxide semiconductor layer 120 are provided with electricity characteristics through the buffer pattern 125. The source and drain electrodes 133, 136 spaced apart from the gate electrode 105, the gate insulating layer 110, the oxide semiconductor layer 120, and the buffer pattern 125, which are sequentially stacked in each of the device regions TrA. Will form a thin film transistor (Tr2).

Next, as shown in FIG. 4M, the mask layer is patterned by performing a mask process on the protective layer 140 of the substrate 101 subjected to the heat treatment process to expose the drain electrode 136 of the thin film transistor Tr2. The drain contact hole 143 is formed.

Next, as shown in Figure 4n, a transparent conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) over the protective layer 140 provided with the drain contact hole 143 To form a transparent conductive material layer (not shown), and by performing a mask process to pattern the pixel electrode 150 in each pixel region P by patterning the array substrate according to the first embodiment of the present invention (101) is completed.

In this case, the pixel electrode 150 may be made of an opaque metal material other than the transparent conductive material.

The array substrate 101 according to the first embodiment of the present invention manufactured as described above omits a mask process for forming a separate etch stopper, thereby manufacturing an array substrate (71 of FIG. 1) equipped with a conventional etch stopper. It has the effect of reducing the mask process once compared to the method.

5 is a cross-sectional view of one pixel region of an array substrate provided with an oxide semiconductor layer according to a second embodiment of the present invention, and the same components as the array substrate according to the first embodiment are denoted by adding 100 to reference numerals. Granted..

The array substrate 201 according to the second embodiment of the present invention differs only in the buffer pattern (125 in FIG. 2) in comparison with the array substrate (101 in FIG. 2) according to the first embodiment. The elements are all the same, so only the parts with differences are explained.

As illustrated, in the array substrate 201 according to the second embodiment of the present invention, the thin film transistor Tr2 having the oxide semiconductor layer 220 is provided in the element region TrA in each pixel region P. Is becoming.

In this case, the island buffer pattern is not provided between the oxide semiconductor layer 220 and the source and drain electrodes 233 and 236 as the most characteristic configuration in the array substrate 201 according to the second embodiment of the present invention. 201) A buffer layer 227 is provided on the entire surface.

That is, in the case of the array substrate (101 in FIG. 2) according to the first embodiment of the present invention, an island-type buffer is formed between the oxide semiconductor layer (120 in FIG. 2) and the source and drain electrodes (133, 136 in FIG. 2). Although a pattern (125 in FIG. 2) is provided, in the case of the array substrate 201 according to the second embodiment of the present invention, instead of an island-type buffer pattern (125 in FIG. 2), the front surface of the substrate 201 is provided. The buffer layer 227 is formed.

At this time, the buffer layer 227 is characterized by being made of the same material as the buffer pattern (125 in FIG. 2), that is, amorphous silicon and metal silicide.

That is, the buffer layer 227 is a portion of the data wiring 230 and the source and drain electrodes 233 and 236, respectively, and is made of metal silicide having conductor characteristics to form a metal silicide region 227a. The portion that does not contact the 230 and the source and drain electrodes 233 and 236 is made of amorphous silicon and is formed of an amorphous silicon region 227b.

The array substrate 201 according to the second embodiment of the present invention provided with the buffer layer 227 having such a configuration has an array substrate according to the first embodiment of the present invention described above except for the buffer layer 227 Since it is the same as 101) in FIG. 2, detailed description thereof will be omitted.

The array substrate 201 according to the second embodiment of the present invention having the above-described configuration also has the same effect as the array substrate (101 of FIG. 2) according to the first embodiment of the present invention, that is, the gate electrode 205 and the source and Improved characteristics of thin film transistor (Tr2) by reducing parasitic capacity by reducing overlapping area between drain electrodes (233, 236), reducing area of source and drain electrodes (233, 236) itself by omitting etch stopper and reducing the number of mask processes And, it has the effect of realizing the short channel of the thin film transistor (Tr2).

6A to 6E are process cross-sectional views of one pixel region including a thin film transistor of an array substrate provided with an oxide semiconductor layer according to a second embodiment of the present invention. In this case, for convenience of description, a portion in which the thin film transistor Tr2 in each pixel area P is to be formed is defined as a device area TrA.

In the case of the manufacturing method of the array substrate 201 according to the second embodiment of the present invention, the buffer layer 227 and the source thereon are compared with the manufacturing method of the array substrate (101 in FIG. 2) according to the first embodiment of the present invention. And the steps of forming the drain electrodes 233 and 236 and the data wiring 230, and all other steps are the same, and thus the manufacturing method of the array substrate (101 in FIG. 2) according to the first embodiment The steps with differentiation will be explained mainly.

First, as illustrated in FIG. 6A, a gate electrode 205 and a gate wiring (not shown) are formed on a transparent insulating substrate 201, and a gate insulating film 210 is formed on the entire surface of the substrate 201 on top of the gate electrode 205. Form.

Thereafter, after forming the amorphous silicon layer 223 having a thickness of 10 to 200 위로 over the gate insulating film 210, mentioned in the method of manufacturing the array substrate according to the first embodiment described above on the amorphous silicon layer 223 The second metal layer 228 having a single layer, double layer, or triple layer structure made of the same material is sequentially formed.

Next, as shown in FIG. 6B, a photoresist is formed on the second metal layer 228 to form a photoresist layer 290, and the light transmission region TA is blocked from the photoresist layer 290. After the exposure mask 295 having the area BA is positioned, the photoresist layer 290 is exposed through the exposure mask 295.

In the case where the photoresist layer 290 is a negative type, the transmission area of the exposure mask 290 for the portions corresponding to the data wiring (230 in FIG. 6E) and the source and drain electrodes (233, 236 in FIG. 6E) TA) is matched, and for other areas, the blocking area BA is positioned so that the exposure is performed.

Next, as illustrated in FIG. 6C, a photoresist pattern 291 having the same height is formed over the second metal layer 228 by developing the exposed photoresist layer (290 in FIG. 6B ).

Next, as shown in FIG. 6D, by etching only the second metal layer (228 of FIG. 6C) exposed outside the photoresist pattern 291, the gate wiring (not shown) and the amorphous silicon layer 223 are etched. Data wirings 230 intersecting the pixel region P and source and drain electrodes 233 and 236 spaced apart from each other in the element region TrA are formed.

At this time, in the process of etching by exposing the second metal layer (228 of FIG. 6C) to the etching solution, the oxide semiconductor layer 220 is covered by the amorphous silicon layer 223, and thus is not affected by the etching solution at all.

Next, as shown in FIG. 6E, the strip is processed to remove the photoresist pattern (291 in FIG. 6D) formed on the data wiring 230 and the source and drain electrodes 233 and 236. The data wiring 230 and the source and drain electrodes 233 and 236 are exposed.

Subsequently, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited on the data wiring 230 and the source and drain electrodes 233 and 236 to protect the entire surface of the substrate 201 ( 240).

Next, the substrate 201 on which the protective layer 240 is formed is placed inside the heat treatment apparatus and heat treatment is performed for 5 to 120 minutes in a temperature atmosphere of 400°C to 600°C.

Through this heat treatment process, the buffer layer 227 is in contact with the data wiring 230 and the source and drain electrodes 233 and 236 as a metal silicide region 227a, and other regions are amorphous silicon regions. (227b).

Since the process is the same as the manufacturing process of the array substrate according to the first embodiment of the present invention described above is omitted.

The mask process for forming the etch stopper is also omitted by the method of manufacturing the array substrate 201 according to the second embodiment of the present invention as described above, so that the manufacturing of the array substrate (71 in FIG. 1) with the conventional etch stopper is omitted. It has the effect of reducing the mask process once compared to the method.

The present invention is not limited to the above-described embodiments, and various changes and modifications are possible without departing from the spirit of the present invention.

101: substrate
105: gate electrode
110: gate insulating film
120: oxide semiconductor layer
125: buffer pattern
125a: Metal silicide region
125b: amorphous silicon region
126: metal silicide pattern
130: data wiring
133: source electrode
136: drain electrode
140: protective layer
143: drain contact hole
150: pixel electrode
P: Pixel area
Tr2: Thin film transistor
TrA: Device area

Claims (23)

A substrate in which a plurality of pixel regions are defined;
A gate electrode formed in each of a plurality of pixel regions on the substrate;
A gate insulating film formed on the entire surface of the substrate over the gate electrode;
Oxide semiconductor layers respectively formed on the gate insulating layer and corresponding to the gate electrode;
A buffer pattern formed on the oxide semiconductor layer and having a metal silicide region and an amorphous silicon region having conductor characteristics;
A source electrode and a drain electrode formed in contact with the metal silicide region over the buffer pattern and spaced apart from each other
Including,
The amorphous silicon region is made of silicon,
The metal silicide region is an array substrate made of the silicon constituting the amorphous silicon region and a metal material constituting the source electrode and the drain electrode.
According to claim 1,
The buffer pattern is an island-shaped array substrate characterized by being formed for each pixel area.
According to claim 2,
The portion of the buffer pattern corresponding to the spaced apart region of the source electrode and the drain electrode forms the amorphous silicon region.
According to claim 2,
A gate wiring extending in one direction on a boundary of the pixel region on the substrate;
An array substrate further provided with a data wiring defining the pixel region by intersecting the gate wiring through a metal silicide pattern over the gate insulating layer.
According to claim 1,
The buffer pattern is formed on the entire surface of the substrate on the oxide semiconductor layer and the gate insulating layer in the plurality of pixel regions to form a buffer layer.
The method of claim 5,
A gate wiring extending in one direction on a boundary of the pixel region on the substrate;
An array substrate characterized in that a data wiring is formed on the buffer layer to cross the gate wiring to define the pixel region, and the data wiring is formed in contact with the metal silicide region.
The method of claim 6,
An area of the buffer layer, except for the region where the source electrode and the drain electrode and the data wiring are formed, constitutes the amorphous silicon region.
According to claim 1,
A portion of the source electrode and the drain electrode in contact with the metal silicide region is an array substrate, characterized in that any one of molybdenum (Mo), titanium (Ti), molybdenum (MoTi).
The method of claim 8,
The source electrode and the drain electrode form a single-layer structure made of any one of the molybdenum (Mo), titanium (Ti), and molybdenum (MoTi), or the molybdenum (Mo), titanium (Ti), The double layer structure of the first layer made of any one of molybdenum (MoTi) and the second layer made of any one of low resistance metal materials such as copper (Cu), copper alloy, aluminum (Al), and aluminum alloy (AlNd) Array substrate characterized by being achieved.
The method of claim 9,
The source electrode and the drain electrode are further provided with a third layer made of any one of the molybdenum (Mo), titanium (Ti), and molybdenum titanium (MoTi) on the second layer to form a triple layer structure. Characteristic array substrate.
According to claim 1,
A protective layer formed on the entire surface of the substrate over the source electrode and the drain electrode and having a drain contact hole exposing the drain electrode;
A pixel electrode provided in the pixel area in contact with the drain electrode through the drain contact hole over the protective layer
Array substrate comprising a.
According to claim 1,
The thickness of the buffer pattern is 10 to 200

It is characterized in that the array substrate.
Forming a gate electrode in each of the plurality of pixel regions on a substrate on which a plurality of pixel regions are defined;
Forming a gate insulating film on the entire surface of the substrate over the gate electrode;
Forming an island-type oxide semiconductor layer corresponding to the gate electrode over the gate insulating layer;
Sequentially forming an amorphous silicon layer and a first metal layer on the entire surface of the substrate over the oxide semiconductor layer;
Patterning the first metal layer and the amorphous silicon layer to form a source electrode and a drain electrode spaced apart from each other in each pixel region, and an island-type buffer pattern under the source electrode and the drain electrode;
Forming a protective layer on the entire surface of the substrate over the source electrode and the drain electrode;
By performing a heat treatment process on the substrate on which the protective layer is formed, a portion exposed between the source electrode and the drain electrode in the buffer pattern forms an amorphous silicon region made of silicon, and a portion in contact with the source electrode and the drain electrode And forming a metal silicide region formed of the silicon constituting the amorphous silicon region and a metal material constituting the source electrode and the drain electrode.
The method of claim 13,
The step of patterning the first metal layer and the amorphous silicon layer to form a source electrode and a drain electrode spaced apart from each other in each pixel region, and an island-type buffer pattern below the source electrode and the drain electrode,
Forming a first photoresist pattern of a first thickness and a second photoresist pattern of a second thickness thinner than the first thickness over the first metal layer;
A source drain having the same planar shape as the buffer pattern over the buffer pattern and the buffer pattern by removing the first metal layer exposed outside the first and second photoresist patterns and the amorphous silicon layer positioned under the first metal layer. Forming a pattern;
Removing the second photoresist pattern by performing ashing, thereby exposing a central portion of the source drain pattern;
Forming the source electrode and the drain electrode spaced apart from each other by removing a central portion of the source drain pattern exposed outside the first photoresist pattern;
Removing the first photoresist pattern
Method of manufacturing an array substrate comprising a.
The method of claim 13,
The forming of the gate electrode includes forming a gate wiring extending in one direction at a boundary of each pixel region,
Forming an island-type buffer pattern under the source electrode, the drain electrode, and the source electrode and the drain electrode may include data defining the pixel area by intersecting the gate wiring through an amorphous silicon pattern over the gate insulating layer. A method of manufacturing an array substrate comprising forming wiring.
The method of claim 15,
The amorphous silicon pattern is a method of manufacturing an array substrate characterized in that it is converted to metal silicide by the heat treatment process.
Forming a gate electrode in each of the plurality of pixel regions on a substrate on which a plurality of pixel regions are defined;
Forming a gate insulating film on the entire surface of the substrate over the gate electrode;
Forming an island-type oxide semiconductor layer corresponding to the gate electrode over the gate insulating layer;
Forming an amorphous silicon layer on the entire surface of the substrate over the oxide semiconductor layer;
Forming a source electrode and a drain electrode spaced apart from each other corresponding to the oxide semiconductor layer in each pixel region on the amorphous silicon layer;
Forming a protective layer on the entire surface of the substrate over the source electrode and the drain electrode;
By performing a heat treatment process on the substrate on which the protective layer is formed, a portion of the amorphous silicon layer exposed between the source electrode and the drain electrode forms an amorphous silicon region made of silicon, and contacts the source electrode and the drain electrode. A method of manufacturing an array substrate comprising forming a metal silicide region comprising a portion of the silicon constituting the amorphous silicon region and a metal material constituting the source electrode and the drain electrode.
The method of claim 17,
The forming of the gate electrode includes forming a gate wiring extending in one direction at a boundary of each pixel region,
The forming of the source electrode and the drain electrode includes forming a data line defining the pixel region by intersecting the gate line over the amorphous silicon layer.
The method of claim 13 or 17,
The method of manufacturing an array substrate, characterized in that the amorphous silicon layer is formed to have a thickness of 10 to 200 mm 2.
The method of claim 19,
The heat treatment process is a method of manufacturing an array substrate characterized in that it proceeds for 5 minutes to 120 minutes in a temperature atmosphere of 400 to 600 ℃.
The method of claim 13 or 17,
A method of manufacturing an array substrate, characterized in that a portion in contact with the metal silicide region of the source electrode and the drain electrode is made of any one of molybdenum (Mo), titanium (Ti), and molybdenum titanium (MoTi).
The method of claim 21,
The source electrode and the drain electrode,
The molybdenum (Mo), titanium (Ti), or formed of a single layer structure made of any one of the material of titanium (MoTi), or
The first layer made of any one of the molybdenum (Mo), titanium (Ti), and molybdenum (MoTi) and low-resistance metal materials such as copper (Cu), copper alloy, aluminum (Al), and aluminum alloy (AlNd) A double layer structure of the second layer made of any one of the
In addition to the first layer and the second layer, a third layer made of any one of molybdenum (Mo), titanium (Ti), and molybdenum (MoTi) is further provided on the second layer to form a triple layer structure. A method of manufacturing an array substrate characterized by being achieved.
The method of claim 17,
The amorphous silicon layer is formed on the front surface of the substrate on the oxide semiconductor layer and the gate insulating layer in the plurality of pixel regions.

Images