KR101816891B1

KR101816891B1 - Organic Light Emitting Diode Display And Driving Method Thereof

Info

Publication number: KR101816891B1
Application number: KR1020100041909A
Authority: KR
Inventors: 이영학; 윤중선
Original assignee: 엘지디스플레이 주식회사
Priority date: 2010-05-04
Filing date: 2010-05-04
Publication date: 2018-01-09
Also published as: KR20110122410A

Abstract

The organic light emitting diode display device according to the present invention includes: an organic light emitting diode (OLED) emitting light by a driving current flowing between a high potential driving voltage source for generating a high potential driving voltage and a low potential driving voltage source; A driving TFT having a gate electrode connected to a first node and a source electrode connected to the high potential driving voltage source, the driving TFT controlling the driving current according to a source-gate voltage; A first storage capacitor connected between the first node and the second node; A first switch TFT for initializing the first node to a reference voltage; A second switch TFT sampling the high potential driving voltage and the threshold voltage of the driving TFT and reflecting the sampled voltage to the first node; A third switch TFT for switching a current path between the data line and the second node; A fourth switch TFT for switching a current path between the driving TFT and the organic light emitting diode; And a fifth switch TFT for initializing the second node to the reference voltage.

Description

[0001] The present invention relates to an organic light emitting diode (OLED) display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display device, and more particularly, to an organic light emitting diode display device capable of improving image quality and a driving method thereof.

2. Description of the Related Art In recent years, development of various flat panel displays (FPD) has been accelerated. Particularly, the organic light emitting diode display device has advantages of high response speed, high luminous efficiency, high luminance and wide viewing angle by using a self-luminous element which emits light by itself.

The organic light emitting diode display device has an organic light emitting diode as shown in FIG. The organic light emitting diode has organic compound layers (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting diode display device arranges the pixels including the organic light emitting diode in a matrix form and controls the brightness of the pixels according to the gray level of the video data. Such an organic light emitting diode display device is divided into a passive matrix type and an active matrix type using a TFT (Thin Film Transistor) as a switching element. Among them, the active matrix method selectively turns on the TFT as the active element to select the pixel and maintains the light emission of the pixel with the voltage held in the storage capacitor.

2 is a circuit diagram showing one pixel equivalently in an active matrix type organic light emitting diode display.

2, a pixel of an active matrix type organic light emitting diode display device includes an organic light emitting diode OLED, a switch TFT ST, a driver TFT DT, and a storage capacitor Cst.

The switch TFT (ST) turns on in response to a scan signal from the gate line (GL), thereby conducting a current between its source electrode and drain electrode. The switch TFT (ST) applies a data voltage from the data line (DL) to the gate electrode of the driver TFT (DT) and the storage capacitor (Cst) during the turn-on period. The driving TFT DT controls the current flowing in the organic light emitting diode OLED according to the voltage Vsg between the source and the gate of the driving TFT DT. The storage capacitor Cst keeps the gate potential of the driving TFT DT constant for a predetermined period. The organic light emitting diode OLED has a structure as shown in FIG. 1 and is connected between the drain electrode of the driving TFT DT and the ground voltage source GND.

2 is proportional to the driving current Ioled flowing in the organic light emitting diode OLED and the driving current Ioled is proportional to the gate-source voltage of the driving TFT DT Vsg of the driving TFT DT and the threshold voltage Vth of the driving TFT DT.

Here, 'μ' denotes the mobility of the driving TFT DT, 'Cox' denotes the parasitic capacitance of the driving TFT DT, 'W' denotes the channel width of the driving TFT DT, 'Vdd' denotes a high potential driving voltage, and 'Vdata' denotes a data voltage.

Such image quality deterioration due to the luminance deviation between pixels in an organic light emitting diode display device is caused by various causes.

First, there is an electrical characteristic deviation of the driving TFT DT such as a threshold voltage Vth for the above reasons.

In a panel using a Low Temperature Poly Silicon (LTPS) back plane, a characteristic deviation of the driving TFT (DT) between pixels occurs due to an ELA (Excimer Laser Annealing) process. On the other hand, in a panel using an amorphous silicon (a-Si) back plane, there is almost no characteristic deviation of the driving TFT (DT) due to the process. However, due to the gate-bias stress accumulated in the gate electrode of the driving TFT DT in accordance with the panel driving, the deterioration degree of the driving TFT DT varies from pixel to pixel, Resulting in characteristic deviations. When the characteristic deviation of the driving TFT DT, that is, the difference of the threshold voltage Vth of the driving TFT DT between the pixels is generated, the organic light emitting diode (OLED) corresponding to the same data voltage Vdata The driving current Ioled flowing through the OLED varies depending on the pixels.

Second, a deviation of the high potential driving voltage (Vdd) due to the IR drop can be mentioned.

The IR drop is a phenomenon in which the level of the high potential driving voltage (Vdd) gradually decreases as the distance from the voltage input terminal is decreased due to the wiring resistance of the power supply wiring. Therefore, the level of the high potential driving voltage Vdd applied to the pixels differs depending on the positions of the pixels. If the level of the high-potential driving voltage Vdd between the pixels changes according to the position, the driving current Iolde flowing through the organic light-emitting diode OLED corresponding to the same data voltage Vdata Are different for each pixel.

In order to eliminate the cause of image quality degradation as described above, various compensation type pixels have recently been proposed, but it is difficult to reduce the luminance deviation between the pixels to a satisfactory level with such a pixel structure. Particularly, in this conventional pixel structure, since the gate potential of the driving TFT can not be directly controlled, it is difficult to implement a sequential BDI (Black Data Insertion) technique. Here, BDI is a technique for alleviating motion blurring, which is blurred and blurry on the screen due to the retention characteristics of the organic light emitting diode display, .

Of course, even with the conventional pixel structure, it is possible to implement a shot-based BDI through control of the driving power source. As shown in FIG. 3, the shot-type BDI does not emit light simultaneously to all the pixels at the same specific time regardless of the data addressing order. For this, the addressing speed of the data must be increased by a time period occupied by the BDI interval within one frame. In addition, according to the shot-type BDI, the light emission time is reduced at the lower part of the panel in which the data addressing order is late compared to the upper part of the panel in which the data addressing order is fast. As a result, there is a limitation in improving the performance of moving picture response time (hereinafter referred to as "MPRT") for eliminating motion blur in the conventional pixel structure.

Accordingly, it is an object of the present invention to provide an organic light emitting diode display device and a method of driving the same, which can improve image quality by preventing luminance deviation between pixels.

It is another object of the present invention to provide an organic light emitting diode (OLED) display device and a method of driving the same, which can improve the MPRT performance by facilitating the BDI technology implementation without causing a luminance deviation according to the panel position.

According to an aspect of the present invention, there is provided an organic light emitting diode (OLED) display device including: an organic light emitting diode (OLED) emitting light by a driving current flowing between a high potential driving voltage source for generating a high potential driving voltage and a low potential driving voltage source; A driving TFT having a gate electrode connected to a first node and a source electrode connected to the high potential driving voltage source, the driving TFT controlling the driving current according to a source-gate voltage; A first storage capacitor connected between the first node and the second node; A first switch TFT having a gate electrode connected to an n-th initialization line to which a n-th initialization signal is applied, and initializing the first node to a reference voltage; A second switch TFT having a gate electrode connected to an nth control line to which an nth control signal is applied and sampling the threshold voltage of the driving TFT and reflecting the sampled voltage to the first node; A third switch TFT having a gate electrode connected to an nth scan line to which an nth scan signal is applied, and switching a current path between the data line and the second node; A fourth switch TFT having a gate electrode connected to the nth emission line to which the nth emission signal is applied, for switching a current path between the driving TFT and the organic light emitting diode; And a fifth switch TFT having a gate electrode connected to the nth control line to which the nth control signal is applied and for initializing the second node to the reference voltage, The n th initialization signal and the n th control signal are maintained at the turn-on level during the 5 th -1st period (the second initialization period), and the n th scan signal and the n- The nth emission signal is maintained at a turn-off level, and the n-th control signal is maintained at the turn-on level during the 5-2th period (the second sampling period), and the n-th initialization signal, n emission signal is maintained at a turn-off level, and the n-th emission signal is maintained at a turn-on level during the fifth 5-3 period (light emission cutoff period), and the n-th initialization signal, The scan signal is maintained at the turn-off level.

According to the organic light emitting diode display device and the driving method of the present invention, the driving current flowing through the organic light emitting diode is not affected by the threshold voltage deviation and the high potential driving voltage deviation of the driving TFT. As a result, even if the deviations are generated, luminance unevenness phenomenon between the pixels is not caused, so that a dramatic improvement in image quality can be expected compared with the conventional method.

Furthermore, according to the organic light emitting diode display device and the driving method of the present invention, it is possible to freely control the driving of the sequential BDI by directly controlling the gate potential of the driving TFT. Accordingly, the present invention greatly improves the MPRT performance without causing a luminance deviation according to the position of the panel without increasing the data addressing speed, thereby effectively eliminating the motion blurring recognized in the moving image. In addition, the present invention can eliminate 3D (3 Dimension) crosstalk through free BDI driving, and can easily apply 3D driving, thereby greatly enhancing the product competitiveness of the display.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining the principle of light emission of a general organic light emitting diode display device. FIG.
2 is an equivalent circuit diagram of a pixel in a conventional organic light emitting diode display.
3 is a diagram showing BDI driving in the conventional shot method.
4 is a block diagram illustrating an organic light emitting diode display device according to an embodiment of the present invention.
5 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
FIG. 6 is a voltage waveform diagram of the control signals applied to FIG. 5 and the first and second nodes; FIG.
FIG. 7A is an equivalent circuit diagram of a pixel for the first period of FIG. 6; FIG.
FIG. 7B is an equivalent circuit diagram of a pixel for the second period of FIG. 6; FIG.
FIG. 7C is an equivalent circuit diagram of a pixel for the third period of FIG. 6; FIG.
FIG. 7D is an equivalent circuit diagram of a pixel for the fourth period of FIG. 6; FIG.
8A is an equivalent circuit diagram of a pixel for the 5 < th >
8B is an equivalent circuit diagram of a pixel for the 5-2 period of FIG. 6. FIG.
FIG. 8C is an equivalent circuit diagram of a pixel for the period 5 - 3 in FIG. 6; FIG.
9 is a diagram illustrating BDI operation in a sequential manner according to the present invention;
10 is an equivalent circuit diagram of a pixel according to another embodiment of the present invention.
FIG. 11 is a voltage waveform diagram of control signals applied to FIG. 10 and the first and second nodes. FIG.
12A to 12C are diagrams showing a variable example of a sampling period.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 4 to 12C.

4 illustrates an organic light emitting diode display device according to an embodiment of the present invention.

4, the organic light emitting diode display includes a display panel 10 in which pixels P are arranged in a matrix, a data driver 12 for driving the data lines 14, A GIP driver 13 for driving the drivers 12 and 13 and a timing controller 11 for controlling the operation of the drivers 12 and 13.

In the display panel 10, a plurality of data lines 14 and gate lines 15, 16, 17, and 18 are intersected with each other, and pixels P are arranged in each of the intersection areas. The gate lines 15, 16, 17, and 18 may include a plurality of scan lines 15, a plurality of emission lines 16, a plurality of control lines 17, And a plurality of initialization lines 18. In the pixel structure shown in FIG. 10, the gate lines may further include sensing lines 19 in addition to the lines 15, 16, 17, and 18. Each of the pixels P is supplied with a high potential driving voltage Vdd, a low potential driving voltage Vss and a reference voltage Vref. The high-potential driving voltage (Vdd) is generated at a constant DC level by the high-potential driving voltage source. The low potential driving voltage Vss is generated by the low potential driving voltage source at a constant DC level lower than the high potential driving voltage Vdd. The reference voltage Vref is generated at a constant DC level determined between the high potential drive voltage Vdd and the low potential drive voltage Vss. The reference voltage Vref may be generated in the timing controller 11 or the GIP driver 13.

The timing controller 11 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 10 and supplies the digital video data RGB to the data driver 12. [ The timing controller 11 also controls the timing of the data driver 12 based on the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK and the data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the GIP driver 13. [

The data driver 12 converts the digital video data RGB into an analog data voltage (hereinafter, referred to as a data voltage) according to the data control signal DDC and supplies it to the data lines 14.

The GIP driver 13 includes a scan driver 13A for driving the scan lines 15 and an emission driver 13B for driving the emission lines 16. [ The scan driver 13A generates a scan signal according to the gate control signal GDC and supplies the scan signal to the scan lines 15. [ The scan driver 13A includes a shift register for shifting the scan signal. The shift register is formed directly on the non-display area of the display panel 10 according to the GIP (Gate In Panel) method. The emission driver 13B generates an emission signal according to the gate control signal GDC and supplies it to the emission lines 16. [ The emission driver 13B includes a shift register for shifting the emission signal. The shift register is formed directly on the non-display area of the display panel 10 according to the GIP (Gate In Panel) method.

The GIP driver 13 may further include a control driver (not shown) for driving the control lines 17. The control driver includes a shift register for shifting the control signal. The shift register is formed directly on the non-display area of the display panel 10 according to the GIP (Gate In Panel) method.

The GIP driver 13 may further include a separate driver (not shown) for driving the initialization lines 18 and / or the sensing lines 19. In some cases, this separate driver function may be performed in the scan driver 13A.

Fig. 5 shows an example of a pixel P arranged on the nth horizontal line (n is a positive integer).

Referring to FIG. 5, a pixel P according to an embodiment of the present invention includes an organic light emitting diode (OLED), a driver TFT DT, and a switch circuit SWC.

The gate electrode of the driving TFT DT is connected to the switch circuit SWC through the first node N1 and the source electrode of the driving TFT DT is connected to the high potential driving voltage source VDD, Is connected to the switch circuit SWC through the third node N3. The driving TFT DT controls the amount of current flowing in the organic light emitting diode OLED according to its source-gate voltage. Here, the driving TFT DT may be implemented as a P-type MOSFET (Metal-Oxide Semiconductor Field Effect Transistor).

The anode electrode of the organic light emitting diode OLED is connected to the switch circuit SWC and the cathode electrode of the organic light emitting diode OLED is connected to the low potential driving voltage source VSS. The organic light emitting diode OLED has the structure shown in FIG. 1, and emits light by a driving current applied through the driving TFT DT.

The switch circuit SWC includes the first to fifth switch TFTs ST1 to ST5 and the first and second storage capacitors Cst1 and Cst2.

The first switch TFT (ST1) functions to initialize the first node (N1) to the reference voltage (Vref). The gate electrode of the first switch TFT ST1 is connected to the nth initialization line 18n to which the nth initialization signal INITn is supplied and the source electrode of the first switch TFT ST1 is connected to the input terminal of the reference voltage Vref And the drain electrode of the first switch TFT (ST1) is connected to the first node (N1). The first switch TFT (ST1) switches the current path between the first node (N1) and the input terminal of the reference voltage (Vref) in response to the n-th initialization signal (INITn). Here, the n-th initialization signal INITn may be replaced with a scan signal SCANn-k of nk (where k is a positive integer smaller than n) according to the set value of the sampling period, May be replaced by nth scan lines 15n-k. This will be described later with reference to FIGS. 12A to 12C.

The second switch TFT (ST2) samples the high potential driving voltage (Vdd) and the threshold voltage of the driving TFT (DT). The gate electrode of the second switch TFT ST2 is connected to the nth control line 17n to which the nth control signal CTRNn is supplied and the source electrode of the second switch TFT ST2 is connected to the third node N3 And the drain electrode of the second switch TFT (ST2) is connected to the first node (N1). The second switch TFT ST2 switches the current path between the first node N1 and the third node N3 in response to the nth scan signal SCANn to make the diode connection of the drive TFT DT.

The third switch TFT (ST3) functions to address data. The gate electrode of the third switch TFT ST3 is connected to the nth scan line 15n to which the nth scan signal SCANn is supplied and the source electrode of the third switch TFT ST3 is connected to the data voltage Vdata , And the drain electrode of the third switch TFT (ST3) is connected to the second node (N2). The third switch TFT ST3 supplies the data voltage Vdata from the data line 14 to the second node N2 by being turned on in response to the n-th scan signal SCANn.

The fourth switch TFT (ST4) has a function of controlling whether or not to emit light. The gate electrode of the fourth switch TFT ST4 is connected to the emission line 16n to which the nth emission signal EMn is supplied and the source electrode of the fourth switch TFT ST4 is connected to the third node N3 And the drain electrode of the fourth switch TFT (ST4) is connected to the anode electrode of the organic light emitting diode (OLED). The fourth switch TFT (ST4) switches the current path between the drive TFT (DT) and the organic light emitting diode (OLED) in response to the nth emission signal (EMn).

The fifth switch TFT (ST5) has a function of initializing the second node N2 to the reference voltage Vref. The gate electrode of the fifth switch TFT ST5 is connected to the nth control line 17n to which the nth control signal CTRNn is supplied and the source electrode of the fifth switch TFT ST5 is connected to the input terminal of the reference voltage Vref And the drain electrode of the fifth switch TFT (ST5) is connected to the second node N2. The fifth switch TFT (ST5) turns on in response to the n-th control signal CTRNn, thereby supplying the reference voltage Vref to the second node N2.

The first storage capacitor Cst1 is connected between the first node N1 and the second node N2. The storage capacitor Cst stores a voltage applied to the first node N1 and the second node N2. The second storage capacitor Cst2 is connected between the high potential driving voltage source VDD and the second node N2 to stabilize the potential of the second node N2.

The operation of the pixel P according to the embodiment of the present invention will be described with reference to Figs. 6, 7A to 7D, and 8A to 8C.

Referring to FIG. 6, the operation of the pixel P according to the embodiment of the present invention includes first to fourth periods (T1 to T4) indicating normal driving, and fifth to seventeenth to And the fifth to third periods (T51 to T53).

First, normal driving will be described. In the normal driving, the first period T1 is a first setup period, the second period T2 is a first sampling period, the third period T3 is a data addressing period, the fourth period T4 is a light emission Respectively.

7A, during the first period T1, the n-th initialization signal INITn and the n-th control signal CTRn are maintained at the turn-on level, that is, the low logic level L, ) And the second and fifth switch TFTs ST5. During the first period T1, the nth scan signal SCANn and the nth emission signal EMn are maintained at the turn-off level, that is, the high logic level H, to turn on the third switch TFT ST3, The switch TFT (ST4) is turned off.

As a result, the first node N1 and the second node N2 are firstly initialized to the reference voltage Vref.

Referring to FIG. 7B, the n-th control signal CTRn is maintained at the low logic level L during the second period T2 to turn on the second and fifth switch TFTs ST5 continuously. During the second period T2, the n-th initialization signal INITn is inverted to the high logic level H to turn off the first switch TFT ST1, and the n-th scan signal SCANn and the n-th emission signal The third switch TFT ST3 and the fourth switch TFT ST4 are continuously turned off, respectively.

As a result, the potential VN1 of the first node N1 is lower than the high-potential driving voltage Vdd by the diode connection of the driving TFT DT (the gate electrode and the drain electrode of the driving TFT DT are short-circuited) (Vdd-Vth) obtained by subtracting the threshold voltage (Vth) of the reference signal (DT). The sampled first calculation value Vdd-Vth is stored in the first storage capacitor Cst1. The potential of the second node N2 maintains the reference voltage Vref.

Referring to FIG. 7C, during the third period T3, the n-th scan signal SCANn is inverted to the low logic level L to turn on the third switch TFT ST3. During the third period T3, the n-th control signal CTRn is inverted to the high logic level H to turn off the second and fifth switch TFTs ST2 and ST5, and the n-th initialization signal INITn And the nth emission signal EMn are maintained at the high logic level H to turn off the first switch TFT ST1 and the fourth switch TFT ST4, respectively.

As a result, the potential of the second node N2 is programmed to the data voltage Vdata, and this data voltage Vdata is stored in the first storage capacitor Cst1. At this time, due to the coupling effect of the first storage capacitor Cst1, the second calculated value Vref-Vdata corresponding to the potential variation of the second node N2, that is, the data voltage Vdata from the reference voltage Vref, Is reflected on the potential VN1 of the first node N1. Accordingly, the potential VN1 of the first node N1 becomes equal to the compensation value {(Vdd-Vth) - (Vref-Vdata) obtained by subtracting the second calculated value Vref-Vdata from the first calculated value Vdd- }.

Referring to FIG. 7D, during the fourth period T4, the nth emission signal EMn is inverted to the low logic level L to turn on the fourth switch TFT ST4. During the fourth period T4, the nth scan signal SCANn is inverted to the high logic level H to turn off the third switch TFT ST3, and the nth initialization signal INITn and the n- The signal CTRn is maintained at the high logic level H to turn off the first switch TFT ST1 and the second and fifth switch TFTs ST2 and ST5.

As a result, the potential VN1 of the first node N1 is maintained at the compensation value {(Vdd-Vth) - (Vref-Vdata)} and the fourth switch TFT ST4 is turned on, The driving current Ioled flows as shown in the following equation (2).

Here, 'μ' denotes the mobility of the driving TFT DT, 'Cox' denotes the parasitic capacitance of the driving TFT DT, 'W' denotes the channel width of the driving TFT DT, Vth is the threshold voltage of the driving TFT DT, Vdd is the high-level driving voltage, and Vdd is the gate-to-source voltage of the driving TFT DT. 'Vdata' denotes a data voltage, and 'Vref' denotes a reference voltage.

Unlike Equation (1), Equation 2 (C) does not include 'Vth' and 'Vdd' in the equation. This means that the driving current Ioled flowing through the organic light emitting diode OLED does not depend on the threshold voltage Vth deviation of the driving TFT DT between pixels and / or the high potential driving voltage Vdd deviation. As a result, even if the threshold voltage (Vth) and / or the high potential driving voltage (Vdd) of the driver TFT (DT) between the pixels is changed, the resulting luminance deviation between the pixels is not generated.

Next, BDI driving will be described. BDI driving is performed following normal driving within each frame to improve MPRT performance. In the BDI driving, the fifth-time period T51 indicates the second initialization period, the fifth-time period T52 indicates the second sampling period, and the fifth-third period T53 indicates the light-off time period .

Referring to FIG. 8A, the n-th initialization signal INITn and the n-th control signal CTRn are inverted to a low logic level L during the 5-1th period T51, , And turns on the second and fifth switch TFT (ST5). During the fifth time period T51, the nth scan signal SCANn is maintained at the high logic level H to turn off the third switch TFT ST3, and the nth emission signal EMn is turned on, Is held at the high logic level (H) to turn off the fourth switch TFT (ST4).

As a result, the first node N1 and the second node N2 are secondarily initialized to the reference voltage Vref.

Referring to FIG. 8B, the n-th control signal CTRn is maintained at the low logic level L during the 5-2th period T52 to turn on the second and fifth switch TFTs ST5 continuously. During the 5-2 second period T52, the n-th initialization signal INITn is inverted to the high logic level H to turn off the first switch TFT ST1, and the n-th scan signal SCANn and the n- The switching signal EMn remains at the high logic level H to turn off the third switch TFT ST3 and the fourth switch TFT ST4, respectively.

As a result, the potential VN1 of the first node N1 is lower than the high-potential driving voltage Vdd by the diode connection of the driving TFT DT (the gate electrode and the drain electrode of the driving TFT DT are short-circuited) (Vdd-Vth) obtained by subtracting the threshold voltage (Vth) of the reference signal (DT). The second sampled first calculated value (Vdd-Vth) is large enough to turn off the driving TFT (DT). The first calculated value Vdd-Vth is stored in the first storage capacitor Cst1. The potential of the second node N2 maintains the reference voltage Vref.
Referring to FIG. 8C, during the fifth to third period T53, the nth scan signal SCANn is inverted to the low logic level L to turn on the third switch TFT ST3. During the third period T3, the n-th control signal CTRn is inverted to the high logic level H to turn off the second and fifth switch TFTs ST2 and ST5, and the n-th initialization signal INITn And the nth emission signal EMn are maintained at the high logic level H to turn off the first switch TFT ST1 and the fourth switch TFT ST4, respectively.

delete

Even if the third switch TFT ST3 is turned on, the drive TFT DT continues to be driven by the first calculated value Vdd-Vth applied to the gate electrode of the drive TFT DT through the first node N1 Off state. As a result, the driving current applied to the organic light emitting diode (OLED) is cut off, and BDI driving can be easily implemented.

FIG. 9 shows BDI driving in a sequential manner according to the present invention.

Referring to FIG. 9, since the gate potentials of the driving TFTs disposed on the corresponding horizontal line can be directly controlled through the initialization signal and the control signal sequentially generated in units of horizontal lines, a sequential BDI implementation becomes possible. The BDI of the conventional shot mode shown in FIG. 3 requires data addressing as fast as the BDI interval occupied by the emission time of the pixels in the one frame (the emission time decreases as the panel goes down) On the other hand, according to the sequential BDI according to the present invention, the light emission time of all the pixels can be made the same regardless of the panel position in one frame, and all of one frame period is allocated to the data addressing It is not necessary to increase the speed of data addressing. Sequential BDI can effectively improve the MPRT performance without causing a luminance deviation according to the panel position. 9, "Add " corresponds to the above-described operation of T1 to T3," Emission "corresponds to operation of T4, and" BDI "corresponds to operation of T51 to T53.

The ratio of the BDI period in one frame depends on how the initialization signal and the control signal are designed. That is, the BDI period can be shortened or lengthened by adjusting the initialization signal and the control signal. In order to increase the MPRT performance, it is advantageous to increase the BDI period.

Figs. 10 and 11 show another example of the pixel P arranged on the nth horizontal line (n is a positive integer).

In the driving of the pixel P according to the embodiment of the present invention, the current path in the direction of the arrow is formed due to the turn-on of the second switch TFT (ST2) during the first period T1 as shown in Fig. This leakage current Ilk increases power consumption. This side effect may also occur in the 5 < th > -1 time period T51 as shown in Fig. 8A though not shown. The second switch TFT ST2 must be turned off during the first and fifth time periods T1 and T51 in order to eliminate the leakage current Ilk. In the pixel P according to another embodiment of the present invention, a separate signal line, that is, a sensing line 19n is further provided. By the sensing signal SENn applied through the sensing line 19n, So that switching of the TFT ST2 is controlled. In other words, the gate electrode of the second switch TFT (ST2) is connected to the sensing line 19n. The sensing signal SENn is maintained at the turn-on level only during the second and fifth time periods T2 and T52, and remains at the turn-off level during the remaining periods. That is, the sensing signal SENn is maintained at a level capable of turning off the second switch TFT (ST2) during the first and fifth-time periods (T1, T51). As a result, in the pixel P structure according to another embodiment of the present invention, since the leakage current path passing through the second switch TFT (ST2) during the first and fifth-time periods (T1, T51) Power increase can be suppressed. The operational effects of the other embodiments of the present invention are substantially the same as those of the embodiment of the present invention. 11, the sensing signal SENn may be maintained at the turn-on level and the emission signal EMn may be maintained at the turn-off level in the fifth to third period T53.

12A to 12C show variable examples of the sampling period.

In order to improve the MPRT performance, high-speed driving is indispensable. As the frame frequency increases, the length of one horizontal period (1H) becomes shorter at the same resolution. For example, when a display panel having Full HD resolution (1920 x 1080) is driven at a frame frequency of 240 Hz, one horizontal period (1 / (240 * 1080)) is approximately 3.9 ㎲. The shorter the length of one horizontal period (1H), the shorter the period devoted to sampling the threshold voltage of the driving TFT, and it is difficult to accurately sample the threshold voltage of the driving TFT.

In the pixel according to the embodiments of the present invention, the sampling period can be easily extended by varying the control signal (the first embodiment) or the control signal and the sensing signal (the second embodiment). For example, in the pixel structure according to the first embodiment, the n-th initialization signal INITn shown in FIG. 12B corresponds to FIG. 12A in which the length of the sampling period T2 is set to be one horizontal period (1H) The n-th control signal CTRNn is turned on in a two horizontal period (2H), or the n-th control signal (CTRNn) The sampling period T2 can be extended any number of times by changing the turn-on level of the signal CTRNn to three horizontal periods 3H. Of course, in this case, it is also necessary to adjust the timing of the n-th initialization signal INITn, the n-th scan signal SCANn and the n-th emission signal EMn. For example, in response to FIG. 12A in which the n-th initialization signal INITn is synchronized with the n-2th scan signal SCANn-2, the n-th initialization signal INITn in the case of FIG. 3). In the case of FIG. 12C, the n-th initialization signal INITn may be adjusted to be synchronized with the (n-4) th scan signal SCANn-4.

As described above, according to the organic light emitting diode display device and the driving method of the present invention, the driving current flowing through the organic light emitting diode is not affected by the threshold voltage deviation and the high potential driving voltage deviation of the driving TFT. As a result, even if the deviations are generated, luminance unevenness phenomenon between the pixels is not caused, so that a dramatic improvement in image quality can be expected compared with the conventional method.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, in the embodiment of the present invention, only the case where the TFT is implemented as a P-type MOSFET has been described. However, the technical idea of the present invention is not limited to this and can be applied to an N-type MOSFET and a C-type MOSFET (CMOS) Of course. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Data driver 13: GIP driver
13A: Scan driver 13B: Emission driver
14: Data line 15: Scan line
16: Emission line 17: Control line
18: initialization line 19: sensing line

Claims

An organic light emitting diode (OLED) emitting light by a driving current flowing between a high potential driving voltage source and a low potential driving voltage source for generating a high potential driving voltage;
A driving TFT having a gate electrode connected to a first node and a source electrode connected to the high potential driving voltage source, the driving TFT controlling the driving current according to a source-gate voltage;
A first storage capacitor connected between the first node and the second node;
A first switch TFT having a gate electrode connected to an n-th initialization line to which a n-th initialization signal is applied, and initializing the first node to a reference voltage;
A second switch TFT having a gate electrode connected to an nth control line to which an nth control signal is applied and sampling the threshold voltage of the driving TFT and reflecting the sampled voltage to the first node;
A third switch TFT having a gate electrode connected to an nth scan line to which an nth scan signal is applied, and switching a current path between the data line and the second node;
A fourth switch TFT having a gate electrode connected to the nth emission line to which the nth emission signal is applied, for switching a current path between the driving TFT and the organic light emitting diode; And
And a fifth switch TFT having a gate electrode connected to the n-th control line to which the n-th control signal is applied and for initializing the second node to the reference voltage,
5-1, 5-2 and 5-3 periods for BDI driving,
During the 5-1th period (the second initialization period), the n-th initialization signal and the n-th control signal are maintained at the turn-on level, the n-th scan signal and the n-th emission signal are maintained at the turn-
During the 5-2th period (the second sampling period), the n-th control signal is maintained at the turn-on level, the n-th initialization signal, the n-th scan signal and the n-th emission signal are maintained at the turn-
Wherein the n th emission signal is maintained at a turn-on level during the 5 < th > third period (light emission cutoff period), and the n < th > Display device.

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The method according to claim 1,
A first, a second, a third and a fourth period for normal driving,
During the first period (the first initialization period), the n-th initialization signal and the n-th control signal are maintained at the turn-on level and the n-th scan signal and the n-th emission signal are maintained at the turn-off level;
During the second period (the first sampling period), the n-th control signal is maintained at the turn-on level and the n-th initialization signal, the n-th scan signal and the n-th emission signal are maintained at the turn-off level;
During the third period (data addressing period), the n-th scan signal is maintained at the turn-on level and the n-th initialization signal, the n-th control signal and the n-th emission signal are maintained at the turn-off level;
Wherein the n th emission signal is maintained at a turn-on level during the fourth period (light emission period), and the n th initialization signal, the n th control signal and the n th scan signal are maintained at a turn- Diode display.

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An organic light emitting diode (OLED) emitting light by a driving current flowing between a high potential driving voltage source and a low potential driving voltage source for generating a high potential driving voltage;
A driving TFT having a gate electrode connected to a first node and a source electrode connected to the high potential driving voltage source, the driving TFT controlling the driving current according to a source-gate voltage;
A first storage capacitor connected between the first node and the second node;
A first switch TFT having a gate electrode connected to an n-th initialization line to which a n-th initialization signal is applied, and initializing the first node to a reference voltage;
A second switch TFT having a gate electrode connected to an nth sensing line to which a nth sensing signal is applied and sampling the threshold voltage of the driving TFT and reflecting the sampled voltage to the first node;
A third switch TFT having a gate electrode connected to an nth scan line to which an nth scan signal is applied, and switching a current path between the data line and the second node;
A fourth switch TFT having a gate electrode connected to the nth emission line to which the nth emission signal is applied, for switching a current path between the driving TFT and the organic light emitting diode; And
And a fifth switch TFT having a gate electrode connected to the n-th control line to which the n-th control signal is applied, and for initializing the second node to the reference voltage.

6. The method of claim 5,
During the first period (the first initialization period), the n-th initialization signal and the n-th control signal are maintained at the turn-on level and the n-th sensing signal, the n-th scan signal and the n-th emission signal are maintained at the turn- ;
During the second period (first sampling period), the n-th control signal and the n-th sensing signal are maintained at the turn-on level and the n-th initialization signal, the n-th scan signal and the n-th emission signal are maintained at the turn- ;
During the third period (data addressing period), the n-th scan signal is maintained at the turn-on level and the n-th initialization signal, the n-th control signal, the n-th sensing signal and the n-th emission signal are maintained at the turn-off level;
During the fourth period (light emission period), the nth emission signal is maintained at the turn-on level, and the nth initialization signal, the nth control signal, the nth sensing signal, and the nth scan signal are maintained at the turn- Diode display.

The method according to claim 6,
Further comprising a fifth to a fifth time period for driving the BDI;
During the 5-1th period (the second initialization period), the n-th initialization signal and the n-th control signal are maintained at the turn-on level, and the n-th sensing signal, the n-th scan signal, Lt; / RTI >
During the 5-2th period (second sampling period), the n-th control signal and the n-th sensing signal are maintained at the turn-on level, and the n-th initialization signal, the n-th scan signal, Lt; / RTI >
During the fifth to third periods (light emission cutoff period), the nth emission signal is maintained at the turn-on level, and the n-th initialization signal, the n-th control signal, the n-th sensing signal, The organic light emitting diode display device being maintained.

The method according to claim 6,
Wherein the width of the turn-on level of the n-th control signal and the n-th sensing signal overlapping the turn-off level of the n-th initialization signal increases in proportion to the first sampling period.

6. The method according to claim 1 or 5,
Wherein the n-th initialization signal is replaced with an nk (k is a positive integer smaller than n) scan signal according to a set value of a sampling period, and the n-th initialization line is replaced with an nk-th scan line.

8. The method of claim 1 or 7,
And the light emission cutoff timing of the pixels within one frame is sequentially delayed from the top to the bottom of the display panel.

An organic light emitting diode which emits light by a driving current flowing between a high potential driving voltage source and a low potential driving voltage source for generating a high potential driving voltage, a gate electrode connected to the first node, and a source electrode connected to the high potential driving voltage source And a first storage capacitor connected between the first node and the second node, the driving method comprising: driving the organic light emitting diode (OLED)
Firstly initializing the potential of the first node and the second node to a reference voltage;
Sampling the potential of the first node with a first calculation value obtained by subtracting the threshold voltage of the driving TFT from the high potential driving voltage;
Applying a data voltage to the second node and reflecting a second operation value corresponding to a potential variation of the second node to the first node to change the potential of the first node from the first operation value to the second operation Setting a compensation value obtained by subtracting a value from the compensation value;
Applying a driving current to the organic light emitting diode by turning on the driving TFT with the compensation value;
Secondarily initializing the potential of the first node and the second node to the reference voltage;
Second sampling the potential of the first node with the first calculated value; And
And turning off the driving TFT by the second sampled first calculation value to cut off a driving current applied to the organic light emitting diode,
And the second calculated value corresponding to the potential variation of the second node is a value obtained by subtracting the data voltage from the reference voltage.

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12. The method of claim 11,
Wherein the light emission blocking time point of the pixels within one frame is sequentially delayed from the top to the bottom of the display panel.

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The method of claim 3,
And the width of the turn-on level of the n-th control signal overlapping with the turn-off level of the n-th initialization signal increases in proportion to the first sampling period.