KR101338994B1 - Thin Film Transistor and Method for fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor and a method of manufacturing the same, the method of manufacturing a thin film transistor according to the present invention comprises the steps of forming an active layer on a substrate; Forming a gate insulating film on the substrate including the active layer; Forming a gate electrode on the gate insulating film; Forming a first conductive impurity region by injecting a first conductive impurity into an active layer under one side of the gate electrode; Forming a second conductive impurity region by implanting a second conductive impurity into the active layer under the other side of the gate electrode; Forming first and second contact holes on the gate insulating layer including the gate electrode to expose the first conductive impurity region and the second conductive impurity region; And forming a drain electrode and a source electrode connected to the first conductive impurity region and the second conductive impurity region, respectively, on the interlayer insulating layer including the first and second contact holes. do.

Impurity region, leakage current, active layer, lightly doped drain (LDD)

Description

Thin film transistor and its manufacturing method {Thin Film Transistor and Method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a manufacturing method, and more particularly, to a thin film transistor capable of suppressing leakage current and kink, even when a lightly doped drain region is not formed separately. It is about a method.

In general, a liquid crystal display device is divided into a passive matrix liquid crystal display device and an active matrix liquid crystal display device according to a method of driving pixels. Among them, an active matrix liquid crystal display device is driven by a thin film transistor in which one pixel is formed for each pixel.

The thin film transistor is composed of an active layer, a gate electrode, a source electrode, and a drain electrode, and the double active layer is where the channel is formed and determines the characteristics of the thin film transistor.

The active layer generally uses amorphous silicon or polysilicon. Recently, the active layer of the thin film transistor has been replaced by amorphous silicon to polysilicon. This is because polysilicon has an advantage of making SOG (silicon on glass) products that can produce circuits on glass substrates with high electric field mobility and almost no light leakage current compared to amorphous silicon.

A thin film transistor using polysilicon generally adopts a top gate structure, which has a structure similar to that of a typical metal-oxide semiconductor field effect transistor (MOSFET) device due to the presence of a gate electrode on the top of the active layer. In addition, it has the great advantage of using the existing semiconductor integrated process.

In addition, a self-aligned structure of the thin film transistor channel is possible by using a mask on the gate electrode when doping.

While polysilicon thin film transistors have excellent field mobility and on-current characteristics, as shown in FIG. 1, off-current characteristics, which are one of the main requirements of thin film transistors, are not good.

Here, in theory, the off current means that when the thin film transistor is in the off state, electrons do not move to the active layer and current cannot flow, but in reality, electrons passing through the active layer exist and current flows. That is, at a low drain voltage, the off current means that electrons are tunneled by the electric field applied to the drain electrode and the active layer region and move to the conduction band to flow the current.

In order to reduce the off current, an additional doping process called a lightly doped drain (LDD) may be performed to increase the horizontal distance between energy bands, thereby preventing electrons from easily tunneling, thereby reducing the off current.

In this regard, the thin film transistor structure according to the prior art to which the LDD doping process is applied will be described with reference to FIGS. 2 and 3 as follows.

2 is a plan view of a thin film transistor having an LDD structure according to the prior art.

3A is a cross-sectional view of a thin film transistor taken along line IIIa-IIIa 'of FIG. 2, and FIG. 3B is a cross-sectional view of a thin film transistor taken along line IIIb-IIIb' of FIG. 2, and FIG. 3C is taken along line IIIc-IIIc 'of FIG. FIG. 3D is a cross-sectional view of the thin film transistor taken along line IIId-IIId 'of FIG. 2.

Here, the thin film transistor structure according to the prior art will be described with reference to FIGS. 2 and 3C.

The thin film transistor according to the prior art may be formed of a single MOS such as NMOS or PMOS, and may be formed of CMOS, but only the case of NMOS is described below.

2 and 3C, a thin film transistor according to the related art supplies a data signal of a data line (not shown) to a pixel electrode (not shown) in response to a gate signal of a gate line (not shown). The thin film transistor has a channel between the gate electrode 19a connected to the gate line, the source electrode 33b connected to the data line, the drain electrode 33a connected to the pixel electrode, the source electrode 33b and the drain electrode 33a. It includes an active layer (15a) to form a.

Here, the gate electrode 19a protrudes perpendicularly to the gate line (not shown) to operate the thin film transistor according to a gate signal applied from the gate line (not shown).

The source electrode 33b is connected to the data line, and applies a data signal applied from the data line to the drain electrode 33a via the active layer 15a.

The drain electrode 33a is formed to face the source electrode 33b with the gate electrode 420 interposed therebetween, and applies the applied data signal to the pixel electrode.

Furthermore, the active layer 15a is formed on the insulating substrate 11 with the buffer insulating film 13 interposed therebetween. In this case, the active layer 15a includes a channel region overlapping the gate electrode 19a with the gate insulating layer 17 interposed therebetween, and a source region 27b and a drain region 27a facing each other with the channel region interposed therebetween. And a lightly doped drain (LDD) region 21 interposed between the source region 27b and the drain region 27b.

Even though n + impurities are doped in the drain region 27a and the source region 27b, the LDD region 21 may be undoped but typically doped with low concentration impurities in order to reduce the off current of the thin film transistor.

In addition, the source region 27b and the drain region 27a are respectively connected to the drain electrode 33a and the first and second contact holes 31a and 31b through the interlayer insulating layer 29 and the gate insulating layer 17. It is connected to the source electrode 33b, respectively.

A method of manufacturing a thin film transistor according to the prior art having the above configuration will be described with reference to FIGS. 4A to 4H.

4A to 4H are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the related art.

As shown in FIG. 4A, after the buffer insulating film 13 is formed on the insulating substrate 11, an amorphous silicon layer is deposited thereon and then crystallized to form the polysilicon layer 15.

Subsequently, as illustrated in FIG. 4B, the polysilicon layer 15 is selectively etched through a photolithography process and an etching process to form an active layer 15a.

Next, the gate insulating layer 17 is formed on the buffer insulating layer 13 including the active layer 15a by using an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ).

Subsequently, a metal such as Al alloy is deposited on the gate insulating film 17 by sputtering or the like to form the gate metal layer 19.

Subsequently, as shown in FIG. 4C, the gate metal layer 19 is selectively etched through a photolithography process and an etching process to form a gate electrode 19a.

Next, as shown in FIG. 4D, the LDD region 21 is formed by ion-implanting n-low concentration impurities into portions of the active layer 15a below both sides of the gate electrode 19a using the gate electrode 19a as a blocking film. do.

Subsequently, as shown in FIGS. 4E and 4F, the first photoresist layer 23 is coated on the entire surface of the substrate, and then the first photoresist layer 23 is selectively patterned through a photolithography process and an etching process using a mask. A first photosensitive film pattern 23a having first and second openings 25a and 25b exposing regions corresponding to the drain region and the source region of the active layer 15a to be formed in the process is formed.

Subsequently, n + high concentration impurity ions are implanted into the drain region and the source region of the active layer 15a exposed through the first and second openings 25a and 25b using the first photoresist pattern 23a as a blocking film to n + drain / Source regions 27a and 27b are formed.

Next, as shown in FIG. 4G, the interlayer insulating layer 29 is formed by removing the first photoresist layer pattern 23a and depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the entire surface of the substrate. Form.

Subsequently, the interlayer insulating layer 29 is selectively removed through a photolithography process and an etching process using a mask to form first and second contact holes 31a and 31b exposing the drain / source regions 27a and 27b. do.

Next, as shown in FIG. 4H, a metal such as Al or Al alloy is deposited on the interlayer insulating layer 29 by sputtering to form a source / drain forming metal layer (not shown).

Subsequently, the metal layer (not shown) is selectively removed by a photolithography process and an etching process using a mask to form a drain electrode 33a and a source electrode 33b to complete the thin film transistor manufacturing process.

 The thin film transistor according to the related art manufactured as described above and a method of manufacturing the same, although not shown in the drawing, form a lightly doped drain (LDD) region, thereby providing a leakage current in an off state. Can be suppressed.

However, according to the above-described thin film transistor and its manufacturing method, there are the following problems.

The thin film transistor and its manufacturing method according to the prior art further require an LDD photo process and a doping process to form an LDD structure for suppressing leakage current in an off state, thereby increasing the overall device fabrication process. This affects productivity and production yield.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, an object of the present invention is to suppress the leakage current (knock current) and kink (phenomena) even if the LDD (lightly doped drain) region is not formed separately The present invention provides a thin film transistor and a method of manufacturing the same.

A thin film transistor according to the present invention for achieving the above object, the gate electrode formed on a substrate; Source / drain electrodes formed on the substrate and positioned at both sides of the gate electrode; And an active layer formed between the gate electrode and the substrate and including a channel region overlapping the gate electrode so as to be insulated from the gate electrode, and a source / drain region connected to each of the source / drain electrodes and having different conductivity. It is characterized by.

According to an aspect of the present invention, a thin film transistor includes: forming an active layer on a substrate; Forming a gate insulating film on the substrate including the active layer; Forming a gate electrode on the gate insulating film; Forming a first conductive impurity region by injecting a first conductive impurity into an active layer under one side of the gate electrode; Forming a second conductive impurity region by implanting a second conductive impurity into the active layer under the other side of the gate electrode; Forming first and second contact holes on the gate insulating layer including the gate electrode to expose the first conductive impurity region and the second conductive impurity region; And forming a drain electrode and a source electrode connected to the first conductive impurity region and the second conductive impurity region, respectively, on the interlayer insulating layer including the first and second contact holes. do.

According to the thin film transistor and the manufacturing method according to the present invention has the following effects.

The present invention is a structure for forming a p + region in the source region in the thin film transistor structure of the prior art without the LDD structure other than the conventional LDD structure, there is no additional step in the process, and omitted the LDD doping process required in the LDD structure This simplifies the process.

Therefore, the present invention enables a more compact device design by reducing the area of the driving circuit part in a structure capable of suppressing short channel effects of the device.

In addition, the present invention can obtain a characteristic suitable for the characteristics of each driving circuit by adjusting the p + region, it is possible to improve the driving circuit characteristics and design.

In the present invention, when the p + region is applied to the n + region when applied to the P-TFT, the same effect as described above can be obtained.

Hereinafter, a thin film transistor structure according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a plan view of a thin film transistor structure according to the present invention.

6A is a cross-sectional view of the thin film transistor taken along the line VIa-VIa 'of FIG. 5, and FIG. 6B is a cross-sectional view of the thin film transistor taken along the line VIb-VIb' of FIG. 5, and FIG. 6C is taken along the line VIc-VIc 'of FIG. FIG. 6D is a cross-sectional view of the thin film transistor taken along the line VId-VId ′ of FIG. 1.

Here, the thin film transistor manufacturing method according to the present invention will be described with reference to FIGS. 5 and 6c.

The thin film transistor according to the present invention may be formed of a single MOS, such as NMOS or PMOS, and may be formed of CMOS, but only the case of NMOS is described below.

5 and 6C, the thin film transistor according to the present invention supplies a data signal of a data line (not shown) to a pixel electrode (not shown) in response to a gate signal of a gate line (not shown). The thin film transistor has a channel between the gate electrode 109a connected to the gate line, the source electrode 127b connected to the data line, the drain electrode 127a connected to the pixel electrode, the source electrode 127b and the drain electrode 127a. It includes an active layer 105a to form a.

Here, the gate electrode 109a protrudes perpendicularly to the gate line (not shown) to operate the thin film transistor according to a gate signal applied from the gate line (not shown).

The source electrode 127b is connected to the data line, and applies a data signal applied from the data line to the drain electrode 127a via the active layer 105a.

The drain electrode 127a is formed to face the source electrode 127b with the gate electrode 109a interposed therebetween, and applies the applied data signal to the pixel electrode.

Furthermore, the active layer 105a is formed on the insulating substrate 101 with the buffer insulating film 103 interposed therebetween. In this case, the active layer 105a includes a channel region overlapping the gate electrode 109a with the gate insulating layer 107 interposed therebetween, and the second conductive source region 121 and the first conductive layer facing each other with the channel region interposed therebetween. And a drain region 115. The second conductive source region 121 refers to a p + region. Although the case of the N-type TFT has been described in the present invention, the case of the P-type TFT is also possible, and in this case, the second conductive source region 121 refers to the n + region.

In addition, the source and drain regions 121 and 115 may pass through the drain electrode 127a and 127 through the first and second contact holes 125a and 125b respectively penetrating the interlayer insulating film 123 and the gate insulating film 107. It is connected to the source electrode 127b, respectively.

On the other hand, the thin film transistor manufacturing method according to the present invention having the above configuration will be described with reference to FIGS. 7A to 7H.

7A to 7H are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the present invention.

As shown in FIG. 7A, after forming the buffer insulating film 103 on the insulating substrate 101, an amorphous silicon layer is deposited thereon and then crystallized to form the polysilicon layer 105.

In this case, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is used as the buffer insulating film 103. The buffer insulating film 103 prevents impurities from the insulating substrate 101 from being diffused. give.

In addition, the amorphous silicon layer is deposited by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or the like, and is then formed as a polysilicon layer 105 through a crystallization process using laser or heat. .

Subsequently, as illustrated in FIG. 7B, the polysilicon layer 105 is selectively etched through a photolithography process and an etching process to form an active layer 105a.

Next, the gate insulating film 107 is formed on the buffer insulating film 103 including the active layer 105a by using an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ).

Subsequently, a gate metal layer 109 is formed by depositing a metal such as Al alloy, Mo or Mo alloy, W or W alloy, Cr or Cr alloy, Ti or Ti alloy on the gate insulating film 107 by sputtering or the like. do. In this case, the gate metal layer 109 may be formed as a single layer or a double layer.

Subsequently, as illustrated in FIG. 7C, the gate metal layer 109 is selectively etched through a photolithography process and an etching process to form a gate electrode 109a.

Next, the first photoresist layer 111 is coated on the gate insulating layer 107 including the gate electrode 109a, and then the first photoresist layer 111 is selectively patterned through a photolithography process and an etching process using a mask. A first photosensitive film pattern 111a having a first opening 113 to expose a region corresponding to the source region of the active layer 105a to be formed in the process is formed.

Subsequently, as shown in FIG. 7D, n + high concentration impurities are implanted into the source region forming region of the active layer 105a exposed through the first opening 113 using the first photoresist pattern 111a as a blocking film. An n + drain region 115 is formed.

Next, as shown in FIG. 7E, after removing the first photoresist pattern 111a, a second photoresist 117 is coated on the entire surface of the substrate.

Subsequently, as illustrated in FIG. 7F, the second photoresist layer 117 may be selectively removed through a photolithography process and an etching process to expose a region corresponding to the source region, thereby exposing a second photoresist layer 119. Pattern 117 is formed.

Next, the p + region 121 is formed by ion implanting a high concentration of p + impurities into the source region forming region of the exposed active layer 105a through the second opening 119 using the second photoresist pattern 117 as a blocking layer. do.

Subsequently, as shown in FIG. 7G, the second photoresist layer pattern 117 is removed, and an interlayer is deposited on the entire surface of the substrate by depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) by PECVD or APCVD. The insulating film 123 is formed.

Subsequently, the interlayer insulating layer 123 and a portion of the gate insulating layer 107 below are sequentially etched through a photolithography process and an etching process using a mask to form the drain region 115 and the source region, that is, the p + region 121. The first and second contact holes 125a and 125b are respectively formed to be exposed.

Subsequently, as shown in FIG. 7H, a metal such as Al or Al alloy, Mo or Mo alloy, W or W alloy, Cr or Cr alloy, Ti, or Ti alloy is sputtered on the interlayer insulating film 123. Deposition to form a source / drain forming metal layer (not shown).

Next, the metal layer (not shown) is selectively removed by a photolithography process and an etching process using a mask to form a drain electrode 127a and a source electrode 127b, thereby completing a thin film transistor manufacturing process.

 Referring to FIGS. 8A and 8B, the off current and the kink phenomenon according to the thin film transistor according to the present invention manufactured as described above are as follows.

8A is a graph illustrating a comparison of the drain current according to the gate voltage of the thin film transistor structure according to the present invention and the prior art.

8B is a graph illustrating a comparison of the drain current according to the drain voltage of the thin film transistor structure according to the present invention and the prior art.

As shown in FIG. 8A, the present invention can significantly reduce the leakage current in the off state, compared to the conventional thin film transistor structure in which the LDD region is not formed. This is because carriers in the off state exit the p + region 121 and leaks because carriers generated in the p + region 121 as the source region exhibit a screen effect in the channel region 105a. Reduce current.

In addition, as shown in FIG. 8B, the present invention can reduce the kink of the output characteristics, as compared with the conventional thin film transistor structure in which the LDD region is not formed. This allows the hole of the electron-hole pair due to the impact ionization to exit and can suppress the kink phenomenon.

As described above, the present invention is a structure for forming a p + region in the source region in the thin film transistor structure of the prior art that does not have an LDD structure other than the conventional LDD structure, and there is no additional step in the process and is required in the LDD structure. Since the LDD doping process is omitted, the process can be simplified.

Therefore, the present invention enables a more compact device design by reducing the area of the driving circuit part in a structure capable of suppressing short channel effects of the device.

In addition, the present invention can obtain a characteristic suitable for the characteristics of each driving circuit by adjusting the p + region, it is possible to improve the driving circuit characteristics and design.

In the present invention, when the p + region is applied to the n + region, the same effect as described above can be obtained.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Therefore, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also within the scope of the present invention.

1 is a graph showing a change in off current according to a gate voltage of a thin film transistor structure according to the prior art.

2 is a plan view of a thin film transistor having an LDD structure according to the prior art.

3A is a cross-sectional view of a thin film transistor taken along line IIIa-IIIa 'of FIG. 2, and FIG. 3B is a cross-sectional view of a thin film transistor taken along line IIIb-IIIb' of FIG. 2, and FIG. 3C is taken along line IIIc-IIIc 'of FIG. FIG. 3D is a cross-sectional view of the thin film transistor taken along line IIId-IIId 'of FIG. 2.

4A to 4H are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the related art.

5 is a plan view of a thin film transistor structure according to the present invention.

6A is a cross-sectional view of the thin film transistor taken along the line VIa-VIa 'of FIG. 5, and FIG. 6B is a cross-sectional view of the thin film transistor taken along the line VIb-VIb' of FIG. 5, and FIG. 6C is taken along the line VIc-VIc 'of FIG. FIG. 6D is a cross-sectional view of the thin film transistor taken along the line VId-VId ′ of FIG. 1.

7A to 7H are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the present invention.

8A is a graph illustrating a comparison of the drain current according to the gate voltage of the thin film transistor structure according to the present invention and the prior art.

8B is a graph illustrating a comparison of the change of the drain current according to the drain voltage of the thin film transistor structure according to the present invention and the prior art.

Claims (8)

A gate electrode formed on the substrate; Source / drain electrodes formed on the substrate and positioned at both sides of the gate electrode; And An active layer formed between the gate electrode and the substrate and including a channel region overlapping the gate electrode to be insulated from the gate electrode, and a source / drain region connected to each of the source / drain electrodes and having a different conductivity; Thin film transistor, characterized in that. The thin film transistor according to claim 1, wherein the drain region is n + high concentration region and the source region is p + high concentration region. The thin film transistor according to claim 1, wherein the gate electrode and the source / drain electrode are selected from metals such as Al alloy, Mo or Mo alloy, W or W alloy, Cr or Cr alloy, Ti or Ti alloy. . Forming an active layer on the substrate; Forming a gate insulating film on the substrate including the active layer; Forming a gate electrode on the gate insulating film; Forming a first conductive impurity region by injecting a first conductive impurity into an active layer under one side of the gate electrode; Forming a second conductive impurity region by implanting a second conductive impurity into the active layer under the other side of the gate electrode; Forming first and second contact holes on the gate insulating layer including the gate electrode to expose the first conductive impurity region and the second conductive impurity region; And And forming a drain electrode and a source electrode connected to the first conductive impurity region and the second conductive impurity region, respectively, on the interlayer insulating layer including the first and second contact holes. Thin film transistor manufacturing method. The method of claim 4, wherein the first conductive impurity is n + high concentration impurity and the second conductive impurity is p + high concentration impurity. The method of claim 4, wherein the gate electrode and the source / drain electrode are formed by selecting any one of metals such as Al, Al alloy, Mo or Mo alloy, W or W alloy, Cr or Cr alloy, Ti or Ti alloy, and the like. Thin film transistor manufacturing method characterized in that. The method of claim 4, wherein the first conductive impurity is p + high concentration impurity and the second conductive impurity is n + high concentration impurity. 5. The method of claim 4, further comprising forming a buffer insulating film on the substrate.

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