KR101298402B1 - Liquid Crystal Panel and Liquid Crystal Display Device having the same - Google Patents

Abstract

A liquid crystal panel suitable for minimizing driving power consumption is disclosed.

In the liquid crystal panel, pixel areas are divided by a plurality of gate lines and a plurality of data lines. Pixels disposed in each of these pixel regions respond to signals from adjacent preceding pixels along corresponding gate lines, corresponding data lines, and corresponding data lines. Accordingly, the swing width of the pixel voltage signal supplied to each of the data lines is reduced, thereby reducing driving power consumption of the liquid crystal panel and suppressing generation of noise of an impulse component.

Liquid crystal panel, series, liquid crystal cell, pixel electrode, reference voltage, previous pixel voltage.

Description

Liquid crystal panel and liquid crystal display device including the same {Liquid Crystal Panel and Liquid Crystal Display Device having the same}

BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the drawings used in the detailed description of the present invention, a brief description of each drawing is provided.

1 is a view schematically showing a conventional liquid crystal display device.

2A and 2B illustrate an inversion driving method of a liquid crystal display device.

3 is a waveform diagram showing a change in voltage charged in any one pixel on a liquid crystal panel driven in an inversion manner.

4 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a view illustrating polar patterns of pixel voltages charged in pixels of a liquid crystal panel according to an exemplary embodiment of the present invention when driven in a dot inversion scheme.

FIG. 6 is a waveform diagram of signals appearing in each part of a liquid crystal display according to an exemplary embodiment of the present invention when driven in a dot inversion scheme.

FIG. 7 is a layout illustrating a structure of a liquid crystal panel according to an exemplary embodiment of the present invention included in FIG. 4.

DESCRIPTION OF THE REFERENCE NUMERALS to the main parts of the drawings "

2, 12: liquid crystal panel 4, 14: gate driver

6, 16: data driver 8, 18: timing control unit

9: common voltage generator 20: reference voltage generator

PLX: Pixel CLC: Liquid Crystal Cell

FPEP: first pixel electrode pattern SPEP: second pixel electrode pattern

TFT: Thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel for displaying an image, and more particularly, to a liquid crystal panel including a liquid crystal. The present invention also relates to a liquid crystal display device including a liquid crystal panel and a driving method thereof.

Flat panel panels, such as liquid crystal panels, plasma display panels, and light emitting display panels, are easily replaced by conventional cathode ray tubes due to their light weight and slimness. The liquid crystal panel applies an electric field that changes according to the pixel data included in the video signal to each pixel to adjust the light transmittance of the liquid crystal cell so that the image is displayed.

The liquid crystal cells included in the liquid crystal panel are formed to be commonly connected to the common voltage line. Accordingly, each of the liquid crystal cells charges a pixel voltage signal that changes based on the common voltage. In other words, the pixel voltage signal supplied to each of the liquid crystal cells has a common voltage and a difference voltage. As a result, a conventional liquid crystal panel causes a lot of driving power to be consumed.

In addition, in order to improve the response characteristic of the liquid crystal to the pixel voltage signal, the conventional liquid crystal panel is driven in an inversion manner. The inversion driving method is a frame inversion system for inverting the polarity of the pixel voltage signal as the frame is changed, and is a line (or column) for inverting the polarity of the pixel voltage signal as the line is changed. A version method (Line (or Column) Inversion System), and a dot inversion system that inverts the polarity of the pixel voltage signal every time the pixel is changed. In the inversion driving method, the positive pixel voltage signal changing in the positive (+) region and the negative pixel voltage signal changing in the negative (−) region are simultaneously applied to the liquid crystal panel based on the common voltage. As a result, the swing width of the pixel voltage signal applied to the liquid crystal panel increases. As a result, the liquid crystal panel driven by the inversion driving method increases the power consumption of the driving power and generates an impulse noise.

These problems will become more apparent through the conventional liquid crystal display as shown in FIG. The conventional liquid crystal display of FIG. 1 includes a liquid crystal panel 2 connected to a gate driver 4 and a data driver 6. The liquid crystal panel 2 includes pixels PXL provided in regions divided by a plurality of data lines DL1 through DLm and a plurality of gate lines GL1 through GLn, respectively. Each of the pixels includes a liquid crystal cell CLC commonly connected to a common voltage line Vcom extending from the common voltage generator 9, and a corresponding data line in response to a scan signal on a corresponding gate line GL. And a thin film transistor TFT for switching the pixel voltage signal to be supplied from the DL to the liquid crystal cell CLC. Since the liquid crystal cell CLC constituting the pixel PXL is connected to the common voltage line Vcom, the pixel voltage signal supplied to the liquid crystal cell CLC has a difference voltage from the common voltage Vcom. As a result, the swing width of the pixel voltage charged in each of the liquid crystal cells and the pixel voltage signal output to each of the data lines DL is increased. As a result, consumption of driving power for driving the conventional liquid crystal panel is inevitably high.

In addition, the pixels PXL on the liquid crystal panel 2 may be driven in an inversion manner. For example, as illustrated in FIGS. 2A and 2B, each pixel may be driven by a pixel voltage signal that is polarity-inverted for each frame and also polarly-inverted with the pixel voltage signal supplied to adjacent pixels. For reference, if FIG. 2A illustrates the polar pattern of the pixel voltage signal supplied to each pixel of the liquid crystal panel 2 when the image of the odd (or even) frame is displayed, FIG. 2B is a view of the even (or even) frame. When an image is displayed, the polarity pattern of the pixel voltage signal supplied to each pixel of the liquid crystal panel 2 is shown. In order to supply the polarity-inverted pixel voltage signal from frame to frame and between adjacent pixels, the data driver 6 converts the pixel data from the timing controller 8 into a pixel voltage signal which is an analog signal and the converted pixel voltage. The polarity of the signal is inverted every frame and horizontal synchronizing period and according to the data lines DL1 to DLm. Accordingly, if the pixel voltage signal supplied to each of the data lines DL1 to DLn has a positive voltage in one frame or one horizontal synchronous period as shown in FIG. 3, the pixel voltage signal is supplied in the next frame or the next horizontal synchronous period. It has a negative voltage.

When the liquid crystal panel is driven in the inversion manner, the pixel voltage signal alternately has positive and negative voltages based on the common voltage and increases the change width (ie, the swing width). As a result, in the conventional liquid crystal panel and the liquid crystal display including the same, driving power consumption is increased and noise in the form of an impulse is generated.

Accordingly, an object of the present invention is to provide a liquid crystal panel suitable for minimizing driving power consumption.

Another object of the present invention is to provide a liquid crystal panel suitable for minimizing the generation of noise.

Another object of the present invention is to provide a liquid crystal display and a driving method thereof suitable for minimizing driving power consumption.

Another object of the present invention is to provide a liquid crystal display and a driving method thereof suitable for suppressing generation of noise.

In order to achieve the above object, a liquid crystal panel according to an exemplary embodiment of the present invention includes: a plurality of gate lines; A plurality of data lines separating pixel regions together with the gate lines; And pixels disposed in each of the pixel regions, the pixels responding to signals from a preceding pixel adjacent along a corresponding gate line, a corresponding data line, and a corresponding data line.

Each of the pixels arranged along the data line preferably includes a liquid crystal cell electrically connected to adjacent pixels along the data line.

The liquid crystal cells included in the pixels arranged along the data line may be connected to a reference voltage line in series.

It is preferable that the liquid crystal cells of the series circuit charge the pixel voltage such that the positive and negative voltages are alternated based on the voltage charged in the preceding liquid crystal cell.

Each of the liquid crystal cells of the series circuit includes: a first pixel electrode pattern connected to a preceding liquid crystal cell; And a second pixel electrode pattern connected to the subsequent liquid crystal cell.

It is preferable that the first and second pixel electrode patterns are formed in a shape having combs.

Preferably, the comb teeth of the first pixel electrode pattern are alternately arranged with the comb teeth of the second pixel electrode pattern.

According to another exemplary embodiment, a liquid crystal panel includes: a plurality of gate lines; A plurality of data lines separating pixel regions together with the gate lines; Liquid crystal cells disposed in each of the pixel regions and connected to each other in series along the data line; And control switch elements disposed corresponding to each of the pixel areas, and connected between corresponding gate lines, data lines, and corresponding liquid crystal cells.

In another embodiment, a liquid crystal display device includes: a gate driver for sequentially driving gate lines on a liquid crystal panel; And supplying a second pixel voltage signal having the first pixel voltage signal when the preceding gate line is driven among the adjacent gate lines as a reference voltage to each of the data lines on the liquid crystal panel when the subsequent gate line is driven. It has a data driver.

The second pixel voltage signal preferably has a voltage having a difference corresponding to a logic value of the pixel data compared to the first pixel voltage signal.

Preferably, the second pixel voltage signal is alternately higher and lower than the first pixel voltage signal.

In another aspect, a driving method of a liquid crystal display device includes: sequentially driving gate lines on a liquid crystal panel; Supplying a first pixel voltage signal when a preceding gate line among adjacent gate lines is driven to each of the data lines on the liquid crystal panel; And supplying a second pixel voltage signal based on the first pixel voltage to each of the data lines on the liquid crystal panel when a later gate line among adjacent gate lines is driven.

According to the above configuration, the liquid crystal panel according to the present invention and the liquid crystal display including the same reduce the swing width of the pixel voltage in each of the liquid crystal cells and the swing width of the pixel voltage signal supplied to each of the data lines. Accordingly, the driving power consumption of both the liquid crystal panel and the liquid crystal display including the same is reduced, and generation of noise of the impulse component is suppressed.

In addition to the objects of the present invention as described above, other objects, other advantages and other features of the present invention will become apparent from the detailed description of the preferred embodiment with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention including a liquid crystal panel according to an exemplary embodiment of the present invention. 5 is a diagram illustrating a polar pattern of a pixel voltage signal charged in liquid crystal cells on a liquid crystal panel when the liquid crystal display according to the exemplary embodiment of the present invention is driven in a dot inversion manner.

Referring to FIG. 4, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 12 according to an exemplary embodiment of the present invention driven by the gate driver 14 and the data driver 16. In the liquid crystal panel 12 according to the exemplary embodiment, the pixels PXL11 to PXLnm formed in each of the regions divided by the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. It includes. Each of the pixels PXL11 to PXLnm switches the pixel voltage signal to be supplied to the liquid crystal cells CLC11 to CLCnm from the corresponding data lines DL1 to DLm in response to a scan signal on the corresponding gate lines GL1 to GLn. Thin film transistors (TFT11 to TFTnm). The liquid crystal cells CLC11 to CLC1m included in each of the pixels PXL11 to PXL1m for one line driven by the scan signal on the first gate line GL1 are electrically connected to the reference voltage line VLref. The reference voltage line VLref is supplied with a reference voltage Vref that maintains a constant voltage level generated by the reference voltage generator 20. The reference voltage generator 20 may supply a reference voltage Vref having a different voltage level for each frame to the reference voltage line VLref under the control of the timing controller 18. Alternatively, the reference voltage generator 10 may be replaced by the common voltage generator 9 included in the conventional liquid crystal display. In this case, the common voltage Vcom generated by the common voltage generator 9 is supplied to the reference voltage line VLref. Alternatively, the reference voltage line VLref may be supplied with the reference voltage Vref from the data driver 16. Even in this case, the data driver 16 can generate the reference voltage Vref whose voltage level varies from frame to frame under the control of the timing controller 18.

The liquid crystal cells CLC21 to CLCnm included in the pixels PXL21 to PXLnm in response to the scan signals on the remaining gate lines GL2 to GLn may correspond to the corresponding pixels on the preceding gate lines GL1 to GLn-1. It is connected between the liquid crystal cells CLC11 to CLC (n-1) m of PXL11 to PXL (n-1) m and drain terminals of the thin film transistors TFT21 to TFTnm of the current pixels PXL21 to PXLnm. In other words, the liquid crystal cells CLC21 to CLCnm included in the pixels PXL21 to PXLnm in response to the scan signals on the second to nth gate lines GL2 to GLn are the preceding gate lines GL1 to GLn−. It is connected between the preceding thin film transistors TFT11 to TFT (n-1) m included in the corresponding pixel on 1) and the drain terminals of the current thin film transistors TFT21 to TFTnm included in the current pixel. Accordingly, the liquid crystal cells CLC arranged along the data line DL are connected to the reference voltage line VLref dependently to form a series circuit.

Accordingly, each of the liquid crystal cells CLC11 to CLC1m included in each of the pixels PXL11 to PXL1m corresponding to the scan signal on the first gate line GL1 is disposed on the corresponding data lines DL1 to DLm. The voltage difference between the pixel voltage signal and the reference voltage Vref on the reference voltage line VLref is charged. Each of the liquid crystal cells CLC21 to CLCnm included in each of the pixels PXL21 to PXLnm in response to the scan signals on the second to nth gate lines GL2 to GLn is a pixel on the corresponding data line DL1 to DLm. By the voltage signal, the liquid crystal cells CLC11 to CLC (n-1) m included in the corresponding pixels PXL11 to PXL (n-1) m on the preceding gate lines GL1 to GLn-1 are charged. The pixel voltage having either one of the voltage levels of the positive (+) region or the voltage level of the negative (-) region is charged based on the pixel voltage signal. In other words, each of the liquid crystal cells CLC21 to CLCnm included in each of the pixels PXL21 to PXLnm in response to the scan signals on the second to nth gate lines GL2 to GLn may have the preceding gate lines GL1 to GLn. The pixel voltage signal charged in the liquid crystal cells CLC11 to CLC (n-1) m included in the corresponding pixels PXL11 to PXL (n-1) m on the pixel -1 is more corresponding to the data lines DL1 to 1. The pixel voltage as high or low as the voltage level of the pixel voltage signal on DLm) is charged.

Thus, each of the liquid crystal cells CLC21 to CLCnm on the liquid crystal panel 12 according to the embodiment of the present invention has positive polarity (+) based on the voltage charged in the liquid crystal cells CLC11 to CLC (n-1) m on the previous line. ) Or the pixel voltage transmitted through each of the data lines DL1 to DLm, since the pixel voltage having the negative polarity voltage is charged, the pixel voltage is charged in each of the liquid crystal cells CLC21 to CLCnm. The swing width of the signal becomes small. As a result, the liquid crystal panel 12 according to the exemplary embodiment of the present invention minimizes driving power consumption and also reduces impulse noise.

The gate driver 14 sequentially enables the plurality of gate lines GL1 to GLn on the liquid crystal panel 12 in response to the gate timing control signal from the timing controller 18. The data driver 16 supplies a pixel voltage signal to each of the data lines DL1 to DLm whenever one of the gate lines GL1 to GLn is driven. For this purpose, the data driver 16 responds to the data timing control signal from the timing controller 18. Further, the data driver 16 inputs one line of pixel data from the timing controller 18 every horizontal synchronous period, and one line of pixels having a voltage level corresponding to each logic value of the pixel data of one line. The pixel voltage signals are supplied to corresponding first through m th data lines DL1 through DLm. The timing controller 18 receives the video data VD and the synchronization signals SYNC from an external video source (not shown) such as a graphics board of the computer system. The sync signals SYNC include a vertical sync signal, a horizontal sync signal, a data clock, and the like. The video data VD includes red, green, and blue pixel data for one frame (or one picture). The timing controller 18 generates the gate control signal and the data control signal based on the synchronization signals SYNC. The timing controller 18 also supplies the red, green, and blue pixel data of the video data VD to the data driver 16 line by line.

The pixel voltage signal supplied to each of the first to m th data lines DL1 to DLm is a previous frame or a previous horizontal synchronous period every frame period and / or horizontal synchronous period when the liquid crystal panel 12 is driven in an inversion manner. The pixel voltage signal may have a voltage that changes in a positive (+) direction or a negative (−) direction. In addition, the pixel voltage signal may be polarized-reversed as the data lines DL1 to DLm change.

For example, when the liquid crystal panel 12 is driven in a dot inversion method, a pixel voltage signal output to each of the data lines DL1 to DLm has a voltage level having a polarity opposite to that of the pixel voltage signals on adjacent data lines. In addition, the first horizontal synchronous period of the frame period has a positive or negative voltage level based on the reference voltage Vref on the reference voltage line VLref. In addition, the pixel voltage signal output to each of the data lines DL1 to DLm has a positive or negative voltage based on the voltage level of the previous pixel voltage signal for each horizontal synchronization period. Accordingly, the liquid crystal cells CLC11 to CLCnm included in each of the pixels PXL11 to PXLnm on the liquid crystal panel 12 have pixel voltages of opposite polarities to those of adjacent pixels as shown in FIG. 5. The signal is charged.

Referring to FIG. 5, the pixel voltage signal DVk on the k-th data line DLk is included in the liquid crystal cell CLCjk of the pixel PXLjk connected to the j-th gate line GLj and the k-th data line DLk. Is filled in the liquid crystal cell CLC (j-1) k of the pixel PXL (j-1) k connected to the j-1 th gate line GLj-1 and the k th data line DLk. The pixel voltage (that is, the positive pixel voltage) CLCVjk that is as high as the voltage level of the pixel voltage signal DVk on the k-th data line DLk is charged based on the pixel voltage CLCV (j-1) k. . Similarly, the pixel voltage signal on the k + 1th data line DLk + 1 also applies to the liquid crystal cell of the pixel connected to the j + 1th gate line GLj + 1 and the k + 1th data line DLk + 1. The k + 1th data line DLk + based on the pixel voltage charged in the liquid crystal cell of the pixel connected to the jth gate line GLj and the k + 1st data line DLk + 1 by DVk + 1. The pixel voltage (that is, the positive pixel voltage) CLCV (j + 1) (k + 1) as high as the voltage level of the pixel voltage signal DVk + 1 on 1) is charged. On the other hand, in the liquid crystal cell of the pixel connected to the j-th gate line GLj and the k + 1-th data line DLk + 1, the pixel voltage signal DVk + 1 on the k + 1-th data line DLk + 1 The pixel on the k + 1th data line DLk + 1 based on the pixel voltage charged in the liquid crystal cell of the pixel connected to the jth gate line GLj and the k + 1th data line DLk + 1 by The pixel voltage (that is, the negative pixel voltage) CLCVj (k + 1) as low as the voltage level of the voltage signal DVk + 1 is charged. In addition, the k-th also applies to the liquid crystal cell CLC (j + 1) k of the pixel PXL (j + 1) k connected to the j + 1th gate line GLj + 1 and the kth data line DLk. The pixel voltage CLCjk charged in the liquid crystal cell CLCjk of the pixel PXLjk connected to the j-th gate line GLj and the k-th data line DLk by the pixel voltage signal DVk on the data line DLk. ) Is charged as low as the voltage level of the pixel voltage signal DVk on the k-th data line DLk (that is, negative pixel voltage) CLC (j + 1) k.

In order to drive the liquid crystal panel 12 in the polar pattern as shown in FIG. 5, the data driver 16 is equipped with the k-th and k + 1-th pixel voltage signals DVk, DVk + 1 as shown in FIG. ) Is supplied to the kth and k + 1th data lines DLk and DLk + 1, respectively. Referring to FIG. 6, the k th pixel voltage signal DVk corresponds to a logic value (ie, a gray scale value) of pixel data on the basis of a pixel voltage level between the j−1 th horizontal sync periods in a j th horizontal sync period. After the voltage level increased by the voltage (that is, the voltage level changed by the voltage corresponding to the logic value of the pixel data in the positive polarity direction), the pixel voltage level between the jth horizontal synchronization periods in the j + 1th horizontal synchronization period The voltage level is lowered by the voltage corresponding to the logic value of the pixel data, that is, the voltage level changed by the voltage corresponding to the logic value of the pixel data in the negative (−) direction. Similarly, the k + 1 th pixel voltage signal VDk + 1 also has a negative polarity (− In the j + 1th horizontal synchronization period, the voltage level changed in the positive (-) direction by the voltage corresponding to the logic value of the pixel data based on the pixel voltage level between the jth horizontal synchronization periods in the j + 1th horizontal synchronization period. Has

Each of the thin film transistors included in the k-th pixel on the j-th gate line GLj is turned on by the high potential scan signal GLSj on the j-th gate line GLj to k-th data. The pixel voltage signal DVk on the line DLk is supplied to the corresponding liquid crystal cell CLCjk. Then, the k-th liquid crystal cell CLCjk on the j-th gate line GLj charges the pixel voltage signal DVk from the k-th data line DLk. Accordingly, the k-th liquid crystal cell CLCjk on the j-th gate line GLj includes the pixel voltage CLCV (charged in the corresponding liquid crystal cell CLC (j-1) k on the previous gate line GLj-1. Based on j-1) k), the pixel voltage (that is, the pixel voltage of positive polarity (+)) CLCVjk as high as the voltage level of the pixel voltage signal DVk on the k-th data line DLk is charged. Similarly, the thin film transistor TFTj (k + 1) included in the k + 1th pixel on the jth gate line GLj is also turned on by the high potential scan signal GLSj on the jth gate line GLj. On, the pixel voltage signal DLVk + 1 on the k + 1th data line DLk + 1 is supplied to the corresponding liquid crystal cell CLCj (k + 1). Then, the k + 1 th liquid crystal cell CLCj (k + 1) on the j th gate line GLj charges the pixel voltage signal DLVk + 1 from the k + 1 th data line DLk + 1, K + 1 based on the pixel voltage CLCV (j-1) (k + 1) charged in the corresponding liquid crystal cell CLC (j-1) k + 1 on the previous gate line GLj-1 The pixel voltage (that is, the pixel voltage of negative polarity (-)) CLCVj (k + 1) which is as low as the voltage level of the pixel voltage signal DVk + 1 on the first data line DLk + 1 is charged.

Also, the thin film transistors included in the k-th pixel on the j + 1th gate line GLj + 1 are also turned on by the high potential scan signal GLSj + 1 on the j + 1th gate line GLj + 1. On, the pixel voltage signal DLVk on the k-th data line DLk is supplied to the corresponding liquid crystal cell CLC (j + 1) k. Then, the k-th liquid crystal cell CLC (j + 1) k on the j + 1-th gate line GLj + 1 charges the pixel voltage signal DLVk from the k-th data line DLk. Accordingly, the k-th liquid crystal cell CLC (j + 1) k on the j + 1th gate line GLj + 1 includes the pixel voltage (charged in the corresponding liquid crystal cell CLCjk on the previous gate line GLj). Based on the CLCVjk, the pixel voltage (that is, the pixel voltage of negative polarity (−)) CLCV (j + 1) k lowered by the voltage level of the pixel voltage signal DVk on the k-th data line DLk is charged. . Similarly, the thin film transistors TFT (j + 1) (k + 1) included in the k + 1th pixels on the j + 1th gate line GLj + 1, respectively, also have the j + 1th gate line GLj + 1. The liquid crystal cell CLC (j + 1) (turned on by the high-potential scan signal GLSj + 1 of the phase corresponding to the pixel voltage signal DVk + 1 on the k + 1th data line DLk + 1) k + 1)). Then, the k + 1 th liquid crystal cell CLC (j + 1) (k + 1) on the j + 1 th gate line GLj + 1 is the pixel voltage signal from the k + 1 th data line DLk + 1. Charges (DVk + 1) to the k + 1th data line based on the pixel voltage CLCVj (k + 1) charged in the corresponding liquid crystal cell CLCj (k + 1) on the previous gate line GLj. The pixel voltage (that is, the pixel voltage of positive polarity (-)) as low as the voltage level of the pixel voltage signal DVk + 1 on (DLk + 1) (CLCV (j + 1) (k + 1)) is charged. .

In this form, each of the liquid crystal cells included in the pixels on the liquid crystal panel 12 is as high or low as the voltage level of the pixel voltage signal on the corresponding data line based on the pixel voltage charged in the corresponding liquid crystal cell on the previous line. The pixel voltage (ie, the positive and negative pixel voltages) is charged. Accordingly, the swing width of the pixel voltage in each of the liquid crystal cells on the liquid crystal panel and the swing width of the pixel voltage signal supplied to each of the data lines DL are reduced. As a result, both the liquid crystal panel and the liquid crystal display including the liquid crystal panel according to the embodiment of the present invention reduce driving power consumption and suppress generation of noise of an impulse component.

FIG. 7 is a layout illustrating a structure of the liquid crystal panel 12 according to the exemplary embodiment of the present invention included in FIG. 4. In FIG. 7, only pixels connected to three data lines DLk-1 to DLk + 1 are illustrated, but n * m pixels connected to m data lines DL1 to DLm as shown in FIG. 4. Those skilled in the art will understand that the PXL11 to PXLnm are included in the liquid crystal panel 12 according to the exemplary embodiment of the present invention. Therefore, FIG. 7 will be described as including n * m pixels PXL11 to PXLnm.

  Referring to FIG. 7, the liquid crystal panel 12 according to the exemplary embodiment of the present invention may be formed in each of the regions divided by the crossing of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. The formed pixels PXL11 to PXLnm are included. Each of these pixels PXL11 to PXLnm includes thin film transistors TFT11 to TFTnm connected to corresponding gate lines GL1 to GLn and corresponding data lines DL1 to DLm. Each of the pixels PXL21 to PXLnm connected to the second to nth gate lines GL2 to GLn is a thin film transistor TFT11 connected to the thin film transistors TFT21 to TFTnm and the previous gate lines GL1 to GLn-1. To liquid crystal cells CLC11 to CLC (n-1) m connected between the drain terminals of the to TFT (n-1) m. Each of the pixels PXL11 to PXLnm connected to the first gate line GL1 may have a drain terminal (that is, a thin film transistor TFT11 to TFT1m) connected to the reference voltage line VLref and the first gate line GL1. And liquid crystal cells CLC11 to CLC1m connected between the corresponding liquid crystal cells CLC21 to CLC2m on the second line.

Each of the liquid crystal cells CLC11 to CLCnm includes a first pixel electrode pattern FPEP11 to FPEPnm formed to be electrically connected to a drain terminal of a corresponding thin film transistor and a corresponding liquid crystal cell on a next line, and a reference voltage line VLref or A second pixel electrode pattern SPEP11 to SPEPnm electrically connected to the drain terminal of the corresponding thin film transistor on the previous line and the corresponding liquid crystal cell. Each of the first and second pixel electrode patterns FPEP and SPEP is formed in a comb shape. In addition, the comb teeth of the first pixel electrode pattern FPEP are arranged in the pixel area so as to alternate with the comb teeth of the second pixel electrode pattern SPEP.

For example, the liquid crystal cell CLCjk of the pixel PXLjk driven by the j-th gate line GLj and the k-th data line DLk may have a k-th pixel on the j-1 th gate line GLj-1. Liquid crystal cell CLC (j-1) k included in PXLk and liquid crystal cell CLC (j included in k-th pixel PXL (j + 1) k on j + 1th gate line GLj + 1. +1) k). In other words, the liquid crystal cell CLCjk of the pixel PXLjk driven by the j-th gate line GLj and the k-th data line DLk has a k-th thin film connected to the j-1 th gate line GLj-1. The drain terminal of the transistor TFT (j-1) k is connected between the drain terminal of the thin film transistor TFTjk connected to the j-th gate line GLj.

Meanwhile, the first pixel electrode pattern FPEP included in each of the liquid crystal cells on the first line is a drain terminal of the corresponding thin film transistors TFT11 to TFT1m connected to the first gate line GL1 and the corresponding liquid crystal on the other line. It is electrically connected to the second pixel electrode patterns SPEP21 to SPEP2m of the cells CLC21 to CLC2m. On the other hand, the second pixel electrode patterns SPEP11 to SPEP2m included in each of the liquid crystal cells on the first line are connected to the reference voltage line VLref. In addition, the combs of the first pixel electrode pattern FPEP and the combs of the second pixel electrode pattern SPEP included in each of the liquid crystal cells CLC11 to CLC1m on the first line are alternately arranged in the pixel area. do.

As a result, corresponding drain lines of the thin film transistors TFT11 to TFT (n-1) m connected to the second to n-1th gate lines GL1 to GLn-1 are corresponding gate lines GL1 to GLn-1. First pixel electrode patterns FPEP11 to FPEP (n-1) m formed in the corresponding pixel regions to be driven by the second pixel, and second pixels formed in the corresponding pixel regions to be driven by the next gate lines GL2 to GLn. All of the electrode patterns SPEP21 to SPEPnm are electrically connected. All of the second pixel electrode patterns SPEP11 to SPEP1m included in the liquid crystal cells CLC11 to CLC1m to be driven by the first gate line GL1 are electrically connected to the reference voltage line VLref. Only the first pixel electrode patterns FPEPn1 to FPEPnm formed in the corresponding pixel region are electrically connected to the drain terminals of the thin film transistors TFTn1 to TFTnm to be driven by the nth gate line GLn.

Thus, the liquid crystal panel 12 according to the exemplary embodiment of the present invention has a pixel electrode pattern of a liquid crystal cell of a previous line in which two pixel electrode patterns included in each of the liquid crystal cells are adjacently disposed along a corresponding data line DL. Electrically connected with the pixel electrode pattern of the liquid crystal cell of the line, the liquid crystal cells arranged along the data line are connected in series to the reference voltage line VLref. When each of the liquid crystal cells connected in series is charged with a positive or negative pixel voltage based on the pixel voltage charged in the liquid crystal cell of the previous line, the swing width of the pixel voltage charged in each of the liquid crystal cells becomes small. Accordingly, the liquid crystal panel 12 according to the exemplary embodiment of the present invention can reduce driving power consumption and suppress generation of impulse noise.

As described above, in the liquid crystal panel and the liquid crystal display including the liquid crystal display according to the exemplary embodiment of the present invention, each of the liquid crystal cells included in the pixels corresponds to data corresponding to the pixel voltage charged in the corresponding liquid crystal cell on the previous line. Charges the pixel voltage (ie, positive and negative pixel voltages) as high or low as the voltage level of the pixel voltage signal on the line. Accordingly, the swing width of the pixel voltage in each of the liquid crystal cells on the liquid crystal panel, the swing width of the pixel voltage supplied to each of the data lines DL, and the swing width of the pixel voltage signal supplied to each of the data lines are reduced. . As a result, both the liquid crystal panel and the liquid crystal display including the liquid crystal panel according to the embodiment of the present invention can reduce the driving power consumption and can suppress the generation of the noise of the impulse component.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be apparent that various modifications, alterations, and other equivalent embodiments are possible.

Claims (18)

delete delete delete delete delete delete delete delete delete delete delete delete A gate driver for sequentially driving gate lines on the liquid crystal panel including the liquid crystal cell; The second pixel voltage signal, which is a voltage having a difference corresponding to a logic value of the pixel data, compared to the first pixel voltage signal when the preceding gate line is driven among the adjacent gate lines, the liquid crystal when the subsequent gate line is driven. A data driver for supplying each of the data lines on the panel, The liquid crystal cell of the pixel corresponding to the subsequent gate line is connected between the liquid crystal cell of the pixel corresponding to the preceding gate line and the drain terminals of the thin film transistor of the pixel corresponding to the subsequent gate line. Liquid crystal display. delete 14. The method of claim 13, And the second pixel voltage signal is alternately higher and lower than the first pixel voltage signal. Sequentially driving gate lines on the liquid crystal panel; Supplying a first pixel voltage signal when a preceding gate line among adjacent gate lines is driven to each of the data lines on the liquid crystal panel; And A second pixel voltage signal, which is a voltage of a difference corresponding to a logic value of pixel data, is supplied to each of the data lines on the liquid crystal panel when a subsequent gate line of adjacent gate lines is driven, compared to the first pixel voltage signal. Including the steps of: The liquid crystal cell of the pixel corresponding to the subsequent gate line is connected between the liquid crystal cell of the pixel corresponding to the preceding gate line and the drain terminals of the thin film transistor of the pixel corresponding to the subsequent gate line. Driving method of liquid crystal display device. delete 17. The method of claim 16, And the second pixel voltage signal is alternately higher and lower than the first pixel voltage signal.

Images