KR101225221B1 - Driving liquid crystal display and apparatus for driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof to improve the display quality of a liquid crystal display device driven by a 2-dot inversion method.

The liquid crystal display includes a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; A control signal generator for generating a source output enable signal having a different pulse width in horizontal period units; And a data driving circuit for inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line in response to the source output enable signal.

Description

Liquid crystal display and its driving method {DRIVING LIQUID CRYSTAL DISPLAY AND APPARATUS FOR DRIVING THE SAME}

1 is a view schematically showing the data polarity of a liquid crystal panel driven in a one dot inversion scheme.

FIG. 2 is a diagram schematically illustrating data polarity of a liquid crystal panel driven in a two dot inversion scheme. FIG.

3 is a block diagram schematically illustrating a liquid crystal display device driven in a two dot inversion method.

FIG. 4 is an enlarged view of a 4x4 liquid crystal cell matrix vertically arranged side by side in the liquid crystal panel of FIG.

FIG. 5 is a waveform diagram illustrating data of a 2-dot inversion method filled in a liquid crystal cell matrix as shown in FIG. 4.

6 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

7 is a circuit diagram showing in detail the SOE generation circuit shown in FIG.

FIG. 8 is a waveform diagram showing input and output waveforms of the SOE generation circuit shown in FIG. 6; FIG.

FIG. 9 is a block diagram showing in detail the data driving circuit shown in FIG. 6; FIG.

FIG. 10 is a waveform diagram illustrating charging characteristics of data supplied to a liquid crystal cell matrix as shown in FIG. 4 in accordance with a source output enable signal according to the present invention. FIG.

11 is a block diagram illustrating a virtually partitioned liquid crystal panel in the liquid crystal display according to the second embodiment of the present invention.

FIG. 12 is a waveform diagram illustrating an example of a source output enable supplied to each block of a liquid crystal panel partitioned into a plurality of blocks as shown in FIG.

Description of the Related Art

31, 61: timing controller 32, 62: data drive circuit

33, 63: gate driving circuit 34, 64: liquid crystal panel

65: SOE generation circuit 71: multiplexer

91: first latch 92: shift register

93: second latch 94: digital-to-analog converter

95: buffer 96: charge share circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for improving display quality of a liquid crystal display device driven by a 2-dot inversion method.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. In an active matrix type liquid crystal display, switching elements are formed in each liquid crystal cell, which is advantageous for displaying a moving image. As the switching device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

The LCD is driven in an inversion manner to reduce flicker and afterimage by periodically inverting the polarity of data charged in the liquid crystal cell. The inversion method includes a line inversion method of inverting the polarity of data between adjacent liquid crystal cells in the vertical line direction, a version method of inverting the polarity of data between adjacent liquid crystal cells in the horizontal line direction, a vertical line direction and a horizontal line direction There is a dot inversion method in which the polarity of data between adjacent liquid crystal cells is reversed. Of these inversion methods, the dot inversion method is mainly selected because flicker hardly appears in the vertical and horizontal directions.

In the dot inversion scheme, as illustrated in FIG. 1, polarities of data supplied to adjacent liquid crystal cells in the vertical direction are opposite to each other, and polarities of data supplied to adjacent liquid crystal cells in the horizontal direction are opposite to each other. The polarity of the data is inverted every frame (Fn-1, Fn). The dot inversion method is most widely used in liquid crystal display devices because flicker is minimized in both the vertical and horizontal directions.

In the dot inversion scheme of FIG. 2, the polarity of data is inverted in units of two dots in the horizontal and vertical directions. The two-dot inversion method as shown in FIG. 2 has the advantage of lower power consumption than the one-dot inversion method as shown in FIG.

3 schematically shows a conventional liquid crystal display device driven in a two dot inversion method.

Referring to FIG. 3, a conventional liquid crystal display device includes a liquid crystal panel 34 in which data lines D1 to Dm and gate lines G1 to Gn cross each other, and TFTs for driving the liquid crystal cell Clc are formed at the intersections thereof. ), A data driving circuit 32 for supplying data to the data lines D1 to Dm of the liquid crystal panel 34, and a scan pulse for supplying scan pulses to the gate lines G1 to Gn of the liquid crystal panel 34. And a timing controller 31 for controlling the gate driving circuit 33 and the data driving circuit 32 and the gate driving circuit 33.

The data driving circuit 32 stores a shift register for sampling a clock, a register for temporarily storing data, a line for storing data in response to a clock signal from the shift register, and simultaneously outputs the stored one line of data. Latch, a digital / analog converter for selecting a positive / negative gamma voltage corresponding to the digital data value from the latch, and a data line to which analog data converted by the positive / negative gamma voltage is supplied (D1 to Dm) ), And a multiplexer for selecting) and an output buffer connected between the multiplexer and the data line. The data driving circuit 32 inverts the polarity of the data voltages supplied to the data lines D1 to Dm in units of two horizontal periods according to a two dot inversion scheme, and converts the data voltages into a source output enable signal. Enable: Supply the data lines D1 to Dm of the liquid crystal panel 34 according to SOE.

The gate driving circuit 33 includes a shift register for sequentially generating scan pulses, and a level shifter for shifting the voltage of the scan pulses to a level suitable for driving the liquid crystal cell Clc. The gate driving circuit 33 sequentially supplies scan pulses to the gate lines G1 to Gn under the control of the timing controller 31.

The timing controller 31 controls the gate control signal GDC and the data driving circuit 32 for controlling the gate driving circuit 33 by using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, a polarity signal POL, and the like. Here, the source output signal SOE is a signal indicating the output time of the data. The gate control signal GDC includes a gate shift clock GSC, a gate output enable GOE, a gate start pulse GSP, and the like.

FIG. 5 illustrates a two-dot inversion data voltage supplied to four liquid crystal cells vertically arranged as shown in FIG. 4.

4 and 5, the liquid crystal display of the two dot inversion method inverts the polarity of the data voltage every two horizontal line periods. Therefore, the positive polarity voltage higher than the common voltage Vcom is applied to the liquid crystal cell A of the first horizontal line HL1 and the liquid crystal cell B of the second horizontal line HL2 connected to the first data line DL1. On the other hand, the liquid crystal cell C of the third horizontal line HL3 connected to the first data line DL1 and the liquid crystal cell D of the fourth horizontal line HL4 are connected to the common voltage Vcom. Low negative voltage is applied.

However, in such a two-dot inversion system, a liquid crystal cell to which a positive voltage (or negative voltage) rising from the negative voltage (or positive voltage) is applied, and a positive voltage changing from the positive voltage (or negative voltage) The amount of charge of data charged in the liquid crystal cell is different between the liquid crystal cells to which the negative voltage is applied. This is because the rising time (or falling time) of the positive voltage (or negative voltage) rising from the negative voltage (or positive voltage) is long, while the positive voltage varies from the positive voltage. This is because the rising time (or polling time) is relatively short. Due to such a difference in charging characteristics, the second and fourth horizontal lines HL2 and HL4 may have the same gray level data voltage as compared to the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3. The liquid crystal cells B and D of FIG. 2 appear brighter, and a luminance difference is generated between neighboring horizontal lines.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof to improve the display quality of a liquid crystal display device driven by a 2-dot inversion method.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; A control signal generator for generating a source output enable signal having a different pulse width in horizontal period units; And a data driving circuit for inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line in response to the source output enable signal.

The control signal generator further generates a polarity control signal indicating the polarity of the data voltage.

The data driving circuit inverts the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal and in response to the source output enable signal, first data and second data having the same polarity as the first data. The third and fourth data having different polarities from the first and second data are sequentially output.

The source output enable signal includes an odd pulse indicating the output of the first and third data voltages; And an even pulse indicating the output of the second and fourth data voltages with a larger pulse width than the odd pulse.

The data driving circuit further includes a charge share circuit for supplying an intermediate voltage between the positive data voltage and the negative data voltage to the data line during the high logic period of the odd and even pulses.

The control signal generator includes a first source output enable signal in which pulses appear in units of two horizontal periods, and a second source in which a pulse occurs in units of two horizontal periods and is delayed by about one horizontal period compared to the first source output enable signal. A timing controller for generating an output enable signal and a selection control signal for selecting the source output enable signals; And a multiplexer for alternately outputting the first and second source output enable signals in units of one horizontal period in response to the selection control signal.

According to another exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; A control signal generator for generating a source output enable signal having a different pulse width according to the position of the liquid crystal panel; And a data driving circuit for inverting the polarity of the data voltage in units of N (N is a positive integer of 2 or more) horizontal period and supplying the data voltage to the data line in response to the source output enable signal.

The liquid crystal panel includes a first block closer to the data driving circuit, a second block located farther from the data driving circuit than the first block, and a third block farther from the data driving circuit than the second block. Include.

The control signal generator may include a source output enable signal of a first block including a first odd pulse and a first even pulse having substantially the same pulse width, and a second even pulse having a wider pulse width than the first even pulse. A source output enable signal of a third block is generated including a source output enable signal of two blocks and a third even pulse having a wider pulse width than the second even pulse.

The data driving circuit outputs data to be displayed in the first block in response to the source output enable signal of the first block, and then displays the data in the second block in response to the source output enable signal of the second block. After outputting data to be output, the data to be displayed in the third block is output in response to the source output enable signal of the third block.

The control signal generator includes a first source output enable signal in which pulses appear in units of two horizontal periods, and a pulse having a delay of about one horizontal period compared to the first source output enable signal and having a different pulse width according to the block. A timing controller for generating a second source output enable signal in horizontal period units and a selection control signal for selecting the source output enable signals; And a multiplexer for alternately outputting the first and second source output enable signals in units of one horizontal period in response to the selection control signal.

A method of driving a liquid crystal display according to an embodiment of the present invention includes the steps of: generating a source output enable signal having a different pulse width in units of horizontal periods; N (N is a positive integer of 2 or more) and inverting the polarity of the data voltage in the horizontal period unit and supplying the data voltage to the data line of the liquid crystal panel in response to the source output enable signal.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, including generating a source output enable signal having a different pulse width according to a position of the liquid crystal panel; N (N is a positive integer of 2 or more) and inverting the polarity of the data voltage in the horizontal period unit and supplying the data voltage to the data line of the liquid crystal panel in response to the source output enable signal.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 12.

Referring to FIG. 6, the liquid crystal display according to the exemplary embodiment of the present invention includes an SOE generation circuit 65 for generating a source output enable signal in which an odd pulse having a short pulse width and an even pulse having a wide pulse width alternate. The scan pulse is supplied to the data driving circuit 62 outputting a data voltage whose polarity is inverted in a 2-dot inversion scheme in response to the output signal SOE, and the gate lines G1 to Gn of the liquid crystal panel 64. And a timing controller 61 for controlling the data driving circuit 62, the gate driving circuit 63, and the SOE generation circuit 65.

Liquid crystal is injected between the two glass substrates, and the liquid crystal panel 64 is formed such that the data lines D1 to Dm and the gate lines G1 to Gn cross each other on the lower glass substrate. The TFTs formed at the intersections of the data lines D1 to Dm and the gate lines G1 to Gn liquid crystal the data on the data lines D1 to Dm in response to a scan pulse from the gate lines G1 to Gn. It is supplied to the cell Clc. For this purpose, the gate electrodes of the TFTs are connected to the gate lines G1 to Gn, and the source electrodes are connected to the data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. A common voltage (Vcom) is supplied to the common electrode facing the pixel electrode. Reference numeral 'Cst' denotes a storage capacitor. The storage capacitor Cst may be formed between the liquid crystal cell Clc connected to the k th gate line (where k is a positive integer between 1 and n) and the k-1 th front gate line, and the k th It may be formed between the liquid crystal cell Clc connected to the gate line and a separate common line.

The SOE generation circuit 65 is composed of a multiplexer 71 as shown in FIG. The multiplexer 71 receives the first source output signal SOE1 having a short pulse width and the second source output signal SOE2 having a wide pulse width from the timing controller 61 to the first and second input terminals. The multiplexer 71 horizontally adjusts the first source output signal SOE1 having a short pulse width and the second source output signal SOE2 having a wide pulse width by approximately 1 in response to the control signal S1 from the timing controller 61. They are alternately selected on a periodic basis and the selected source output signals SOE1 and SOE2 are supplied to the data driving circuit 62. This SOE generation circuit 65 can be built in the timing controller 61.

The data driving circuit 62 responds to the digital data RGB input from the timing controller 61 in response to the control signals DDC and SOE input from the timing controller 61 and the SOE generation circuit 65. The data of which polarity is inverted is supplied to the data lines D1 to Dm of FIG. 2 as shown in FIG. That is, the data driving circuit 62 generates data having the same polarity for two horizontal periods according to the polarity control signal POL included in the control signal DDC from the timing controller 61, and then reverses the polarity of the data. Inverts the polarities of horizontally neighboring data to each other. A detailed description of the data driving circuit 62 will be described in detail with reference to FIG. 9.

The gate driving circuit 63 sequentially supplies scan pulses to the gate lines G1 to Gn in response to the control signal GDC from the timing controller 61.

The timing controller 61 controls the gate control signal GDC and the data driving circuit 62 for controlling the gate driving circuit 63 using the vertical / horizontal synchronization signals V and H and the clock CLK. To generate a data control signal DDC. The data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a first source output signal SOE1, a first source output signal SOE1, a polarity signal POL, and the like. The gate control signal GDC includes a gate shift clock GSC, a gate output signal GOE, a gate start pulse GSP, and the like.

In addition, the timing controller 61 varies the number of coefficients of the clock CLK so that the pulse width of the first source output signal SOE1 having a short pulse width and a period of two horizontal periods 2H as shown in FIG. Generate a second source output signal SOE2 that is wide and has two horizontal periods 2H. The second source output signal SOE2 is generated approximately one horizontal period later than the first source output signal SOE1. The first source output signal SOE1 indicates the output of the preceding radix data among the two data of the same polarity, and the second source output signal SOE2 has the same polarity as the radix data and the output of the even data generated after the radix data. To indicate. In addition, the second source output signal SOE2 is set to be wider than the pulse width of the first source output signal SOE1 so as to reduce the time for the good data to be charged in the liquid crystal cell and thus to be filled with the liquid crystal cell and the good data charged with the odd data. Make the filling amount of the liquid crystal cell uniform. This will be described in detail with reference to FIG. 10.

9 schematically shows the data driving circuit 62.

Referring to FIG. 9, the data driving circuit 62 includes a plurality of integrated circuits (ICs), each integrated circuit including a shift register 92 and a first latch, which are cascaded between an input line and a data line. 91, a second latch 93, a digital-to-analog converter (hereinafter referred to as "DAC") 94, a charge share circuit 96 and a buffer 95.

The shift register 92 shifts the source start pulse SSP from the timing controller 61 in accordance with the source shift clock signal SSC to generate a sampling signal. In addition, the shift register 92 shifts the source start pulse SSP to transfer a carry signal CAR to the next stage shift register 92.

The first latch 91 samples and stores the digital data RGB according to the sampling signal input from the shift register 92, and supplies the stored digital data to the second latch 93.

The second latch 93 latches the data RGB input from the first latch 91 and then, in response to the source output signal SOE from the timing controller 60, the second latch 93 in another integrated circuit. ) And digital data of one horizontal line latched together. The second latch 93 outputs data at the falling edge of the source output enable signal SOE from the SOE generation circuit 65 as shown in FIG. 8, and at the rising edge of the source output enable signal SOE. Stop output of data. Accordingly, the second latch 93 makes the output time of the even data longer than the odd data by the even source output enable signal SOE having a wide pulse width.

The DAC 94 transmits the digital data RGB from the second latch 93 to the positive analog gamma voltage VPG or the negative analog gamma voltage VNG according to the polarity control signal POL from the timing controller 61. Converts the polarity of the data voltage in two horizontal periods so that the polarity of the data voltage is inverted in two horizontal periods, and outputs an analog data voltage having a different polarity in a two-dot inversion manner.

The charge share circuit 96 supplies the charge share voltage to the data line through the buffer 95 during the high logic section of the source output enable signal SOE from the SOE generation circuit 65 as shown in FIG. 8. Here, the charge share voltage is an intermediate voltage between the positive data voltage and the negative data voltage and is equal to or similar to the common voltage Vcom supplied to the common electrode of the liquid crystal cell. This charge share voltage may be generated by a switch circuit that supplies a voltage supplied from a power supply circuit disposed outside the data integrated circuit to the data line during the high logic section of the source output enable SOE. It may be generated by a switch circuit for shorting neighboring data lines to which data of different polarities are supplied during the high logic period of the enable signal SOE.

The buffer 95 supplies a large current of the analog data to the data line so that the analog data voltage generated from the charge share circuit 94 does not drop down by the liquid crystal panel 64.

In Fig. 9, reference numeral R denotes an equivalent line resistance between the output terminal of the data driving circuit 62 and the data lines D1 to Dm.

10 shows a source output enable signal SOE and a charging voltage of a liquid crystal cell according to the present invention. The charging characteristics of the liquid crystal cells according to the present invention will be described by combining the waveform diagram of FIG. 10 and the 4 × 4 liquid crystal cell matrix of FIG. 9.

4 and 10, a liquid crystal display according to an exemplary embodiment of the present invention includes analog data voltages having alternating polarities for approximately two horizontal periods in response to the source output enable signal SOE shown in FIG. 8. It supplies to the liquid crystal cells Clc through D1 to Dm and TFTs.

The odd pulse of the source output enable signal SOE has a small pulse width, and is approximately one horizontal period (1H) between the rising time of the odd pulse of the source output enable signal SOE and the rising pulse of the even pulse. In comparison, the even pulse of the source output enable signal SOE has a relatively longer pulse width, and the rising time of the even pulse of the source output enable signal SOE and the rising time of the odd pulse generated thereafter are approximately. 1 horizontal period (1H). Accordingly, the liquid crystal cells B and D of the second and fourth horizontal lines HL2 and HL4 may be charged in comparison with the liquid crystal cells A and C of the first and third horizontal lines HL1 and HL3. The output time of data is shorter. As a result, the present invention can make the charging characteristic nonuniformity between the liquid crystal cell of the odd line and the liquid crystal cell of the even line in the two dot inversion method uniform by modulation of the source output enable (SOE).

During the high logic period in which the odd and even pulses of the source output enable signal SOE are generated, the charge share voltage between the positive data voltage and the negative data voltage is supplied to the data line.

Meanwhile, since the liquid crystal cells close to the data driving circuit 62 do not have RC delay due to the line resistance of the data line and the capacitance of the liquid crystal cell, the data output time having the same polarity as the source output enable SOE shown in FIG. 8. If different, rather filling unevenness may result.

11 and 12 are diagrams for describing a method of driving a liquid crystal display according to a second embodiment of the present invention.

11 and 12, the liquid crystal display according to the present invention virtually divides the liquid crystal panel 64 into a plurality of blocks, for example, three blocks BL1, BL2, and BL3, and each block. The output of data to be supplied to the fields BL1, BL2, and BL3 is controlled by different source output enable signals SOE (BL1), SOE (BL2), and SOE (BL2).

The first block BL1 of the liquid crystal panel 64 includes a plurality of horizontal lines and is close to the data driving circuit 64. The source output enable signal SOE (BL1) indicating the output of the analog data voltage to be supplied to the liquid crystal cells Clc of the first block BL1 is a radix pulse indicating the output of the data voltages of the same polarity. The pulse width of the even pulse is substantially the same. Accordingly, in the present invention, the charging unevenness of the liquid crystal cells of the first block BL1, which may occur when the pulse width of the source output enable varies periodically in the first block BL1 having almost no delay when the polarity of the data changes. Can be prevented.

The second block BL2 of the liquid crystal panel 64 includes a plurality of horizontal lines and is located farther from the data driving circuit 64 than the first block BL1 to change the line resistance of the data line when the polarity of the data changes. And a delay due to capacitance of the liquid crystal panel is longer than that of the first block BL1. The source output enable signal SOE (BL2) indicating the output of the analog data voltage to be supplied to the liquid crystal cells Clc of the second block BL2 is a radix pulse indicating the output of the data voltages of the same polarity. Change the pulse width of the even pulse, but make the pulse width of the even pulse approximately 1 to 1.2 times wider than that of the odd pulse. Therefore, in the second block BL2 where a delay occurs when the polarity of the data changes, the charging time of the excellent data is increased by the shortage of the odd data whose charging time is shortened due to the delay of the odd data and the even data of the same polarity. In the second block BL2, the liquid crystal cell charging characteristic of odd data and the liquid crystal cell charging characteristic of even data can be made uniform.

The third block BL3 of the liquid crystal panel 64 includes a plurality of horizontal lines and is located farther from the data driving circuit 64 than the second block BL2 so that the line resistance of the data line changes when the polarity of the data changes. And a delay due to the capacitance of the liquid crystal panel is longer than that of the second block BL2. The source output enable signal SOE (BL3) indicating the output of the analog data voltage to be supplied to the liquid crystal cells Clc of the third block BL2 is a radix pulse indicating the output of the data voltages of the same polarity. Change the pulse width of the even pulse, but make the pulse width of the even pulse approximately 1.2 to 1.5 times wider than that of the odd pulse. Therefore, in the third block BL3 where a delay occurs when the polarity of the data changes, the charging time of the excellent data is increased by the shortage of the odd data whose charging time is shortened due to the delay between the odd data and the even data of the same polarity. It is possible to shorten the liquid crystal cell charging characteristic of odd data and the liquid crystal cell charging characteristic of even data in the third block BL3.

The liquid crystal display according to the second embodiment of the present invention is substantially the same as the above-described embodiment except for the second source output enable signal SOE2 generated from the timing controller 61. In this second embodiment, the timing controller 61 uses the second source output enable signal SOE2 as shown in FIG. 8 to vary the even pulse width of the source output enable signal SOE according to the position of the liquid crystal panel. The pulse width of is varied depending on the position of the liquid crystal panel 64. That is, the timing controller 61 substantially sets the pulse width of the second source output enable signal SOE2 corresponding to the first block BL1 of the liquid crystal panel 64 to the first source output enable signal SOE1. In the same manner, the timing controller 61 sets the pulse width of the second source output enable signal SOE2 corresponding to the second block BL2 of the liquid crystal panel 64 to the first source output enable signal SOE1. 1 to 1.2 times wider than the. The timing controller 61 has a pulse width of the second source output enable signal SOE2 corresponding to the third block BL3 of the liquid crystal panel 64 from 1.2 to the first source output enable signal SOE1. Make it 1.5 times wider.

As described above, the liquid crystal display device and the driving method thereof according to the present invention invert the polarity of the data voltage to be supplied to the liquid crystal cell in units of two horizontal periods, and instruct the output of the source output enable signal to instruct the data output to the data line. Among the odd and even pulses, the pulse width of the even pulses is controlled longer than the odd pulses so that the liquid crystal cell supplied with the odd horizontal line data and the even horizontal line data are supplied in the 2-dot inversion driven liquid crystal display device. The charging characteristics of the liquid crystal cell can be made uniform. As a result, the liquid crystal display device and the driving method thereof according to the present invention can improve the display quality in the 2-dot inversion method. Furthermore, the liquid crystal display and the driving method thereof according to the present invention vary the pulse width of the source output enable signal according to the position of the panel so that the charging characteristics of all liquid crystal cells in the panel to which data is supplied in a 2-dot inversion method are uniform. can do.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, although the embodiment of the present invention has been described based on the dot inversion method, N (where N is a positive integer of 2 or more) may also be applied to the dot inversion method. In addition, embodiments disclosed in the detailed description of the invention may be used in combination. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (26)

A liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; A control signal generator for generating a source output enable signal having a different pulse width in horizontal period units; N (N is a positive integer of 2 or more) inverts the polarity of the data voltage in units of horizontal periods to generate a positive data voltage and a negative data voltage, A data driving circuit configured to supply the data voltage to the data line in response to the source output enable signal; And the data driving circuit includes a charge share circuit which generates an intermediate voltage between the positive data voltage and the negative data voltage. The method of claim 1, And the control signal generator further generates a polarity control signal indicating the polarity of the data voltage. The method of claim 2, The data driving circuit, Inverting the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal, and in response to the source output enable signal, first data, second data having the same polarity as the first data, the first and And third and fourth data having different polarities from the second data are sequentially output. The method of claim 3, wherein The source output enable signal is, An odd pulse indicating the output of the first and third data voltages; And an even pulse indicating the output of the second and fourth data voltages with a larger pulse width than the odd pulse. 5. The method of claim 4, The intermediate voltage is, And generated during the high logic period of the odd and even pulses and supplied to the data line. 5. The method of claim 4, The control signal generator, A first source output enable signal in which pulses appear in units of two horizontal periods, a second source output enable signal in which a pulse appears in units of two horizontal periods and delayed by about one horizontal period compared to the first source output enable signal, A timing controller for generating a selection control signal for selecting the source output enable signals; And a multiplexer for alternately outputting the first and second source output enable signals in units of one horizontal period in response to the selection control signal. A liquid crystal panel in which a plurality of data lines and a plurality of gate lines intersect and a plurality of liquid crystal cells are disposed; A control signal generator for generating a source output enable signal having a different pulse width according to the position of the liquid crystal panel; N (N is a positive integer of 2 or more) Inverts the polarity of the data voltage in horizontal period units to generate a positive data voltage and a negative data voltage, and converts the data voltage in response to the source output enable signal. A data driving circuit for supplying the And the data driving circuit includes a charge share circuit which generates an intermediate voltage between the positive data voltage and the negative data voltage. The method of claim 7, wherein And the control signal generator further generates a polarity control signal indicating the polarity of the data voltage. The method of claim 7, wherein The data driving circuit, Inverting the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal, and in response to the source output enable signal, first data, second data having the same polarity as the first data, the first and And third and fourth data having different polarities from the second data are sequentially output. The method of claim 9, The source output enable signal is, An odd pulse indicating the output of the first and third data voltages; And an even pulse indicating the output of the second and fourth data voltages with a larger pulse width than the odd pulse. 11. The method of claim 10, The liquid crystal panel includes a first block closer to the data driving circuit, a second block located farther from the data driving circuit than the first block, and a third block farther from the data driving circuit than the second block. Including; The control signal generator may include a source output enable signal of a first block including a first odd pulse and a first even pulse having substantially the same pulse width, and a second even pulse having a wider pulse width than the first even pulse. Generate a source output enable signal of a third block comprising a source output enable signal of two blocks and a third even pulse having a wider pulse width than the second even pulse; The data driving circuit outputs data to be displayed in the first block in response to the source output enable signal of the first block, and then displays the data in the second block in response to the source output enable signal of the second block. And outputting data to be displayed on the third block in response to a source output enable signal of the third block. The method of claim 11, The intermediate voltage is, And generated during the high logic period of the odd and even pulses and supplied to the data line. The method of claim 11, The control signal generator, A first source output enable signal in which pulses appear in units of two horizontal periods, and a pulse having a delay of about one horizontal period compared to the first source output enable signal and having a different pulse width according to the block appear in the unit of two horizontal periods. A timing controller for generating a second source output enable signal and a selection control signal for selecting the source output enable signals; And a multiplexer for alternately outputting the first and second source output enable signals in units of one horizontal period in response to the selection control signal. Generating a source output enable signal having a different pulse width in horizontal period units; N (N is a positive integer of 2 or more) Inverts the polarity of the data voltage in horizontal period units to generate a positive data voltage and a negative data voltage, and in response to the source output enable signal, the data voltage is applied to the liquid crystal panel. Supplying to a data line; And And generating an intermediate voltage between the positive data voltage and the negative data voltage. 15. The method of claim 14, And generating a polarity control signal indicative of the polarity of the data voltage. 16. The method of claim 15, Inverting the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal, and in response to the source output enable signal, first data, second data having the same polarity as the first data, the first and And sequentially outputting third and fourth data having different polarities from the second data. 17. The method of claim 16, The source output enable signal is, An odd pulse indicating the output of the first and third data voltages; And an even pulse that indicates an output of the second and fourth data voltages with a larger pulse width than the odd pulse. The method of claim 17, And the intermediate voltage is supplied to the data line during the high logic period of the odd and even pulses. The method of claim 17, A first source output enable signal in which pulses appear in units of two horizontal periods, a second source output enable signal in which a pulse appears in units of two horizontal periods and delayed by about one horizontal period compared to the first source output enable signal, Generating a selection control signal for selecting the source output enable signals; And alternately outputting the first and second source output enable signals in units of one horizontal period by using a multiplexer controlled according to the selection control signal. Generating a source output enable signal having a different pulse width according to a position of the liquid crystal panel; N (N is a positive integer of 2 or more) Inverts the polarity of the data voltage in horizontal period units to generate a positive data voltage and a negative data voltage, and in response to the source output enable signal, the data voltage is converted into the liquid crystal panel. Supplying to a data line of the; And And generating an intermediate voltage between the positive data voltage and the negative data voltage. 21. The method of claim 20, And generating a polarity control signal indicative of the polarity of the data voltage. 21. The method of claim 20, Inverting the polarity of the data voltage in units of two horizontal periods in response to the polarity control signal, and in response to the source output enable signal, first data, second data having the same polarity as the first data, the first and And sequentially outputting third and fourth data having different polarities from the second data. 23. The method of claim 22, The source output enable signal is, An odd pulse indicating the output of the first and third data voltages; And an even pulse that indicates an output of the second and fourth data voltages with a larger pulse width than the odd pulse. 24. The method of claim 23, The liquid crystal panel includes a first block closer to the data driving circuit, a second block located farther from the data driving circuit than the first block, and a third block farther from the data driving circuit than the second block. Including; The generating of the source output enable signal may include a source output enable signal of a first block including a first odd pulse and a first even pulse having substantially the same pulse widths, and a second pulse width wider than the first even pulse. Generating a source output enable signal of a second block comprising two even pulses, and a source output enable signal of a third block comprising a third even pulse having a wider pulse width than the second even pulse; ; The supplying of the data voltage to the data line of the liquid crystal panel may include outputting data to be displayed in the first block in response to the source output enable signal of the first block, and then enabling the source output of the second block. Outputting data to be displayed in the second block in response to a signal, and then outputting data to be displayed in the third block in response to a source output enable signal of the third block. Method of driving display device. 25. The method of claim 24, The intermediate voltage is, And a high logic period of the odd and even pulses is supplied to the data line. 25. The method of claim 24, A first source output enable signal in which pulses appear in units of two horizontal periods, and a pulse having a delay of about one horizontal period compared to the first source output enable signal and having a different pulse width according to the block appear in the unit of two horizontal periods. Generating a second source output enable signal and a selection control signal for selecting the source output enable signals; And alternately outputting the first and second source output enable signals in units of one horizontal period by using a multiplexer controlled according to the selection control signal.

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