KR101087786B1 - Semiconductor device and method for forming using the same - Google Patents

Abstract

According to an embodiment of the present invention, a buried gate embedded in an isolation layer and an active region is formed, an insulating film is formed on the buried gate, a conductive material is formed between the insulating films, and the planar height of the insulating film is formed on the conductive material. After the bit line conductive layer is formed, a bit line having a stacked structure of the bit line conductive layer and the conductive material is formed on the device isolation layer or the active region, thereby forming a bit line contact without a separate mask process. This reduces the time and cost required to perform the mask process, and provides a fundamental solution to the problem that bit line contacts are not accurately implemented due to high integration.

Flush Gate, Bitline Contact

Description

Semiconductor device and method for forming using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device including a buried gate, and more particularly, to a semiconductor device and a method of forming the bit line contact without additional mask processing.

Most modern electronic appliances are equipped with semiconductor devices. The semiconductor device includes electronic elements such as transistors, resistors, and capacitors, which are designed to perform partial functions of the electronic products and then integrated on a semiconductor substrate. For example, electronic products such as a computer or a digital camera include semiconductor devices such as a memory chip for storing information and a processing chip for controlling information, and the memory chip and the processing chip are semiconductors. And the electronic components integrated on a substrate.

On the other hand, the semiconductor devices need to be increasingly integrated in order to meet the excellent performance and low price required by the consumer. As the degree of integration of semiconductor memory devices increases, design rules decrease, and the pattern of semiconductor devices becomes smaller. As miniaturization and high integration of a semiconductor device progresses, the overall chip area increases in proportion to an increase in memory capacity, but the area of a cell area where a semiconductor device pattern is formed is actually decreasing. Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell region, so that a fine pattern with a reduced critical dimension of the pattern must be formed.

In particular, the contact connecting the upper and lower conductive wirings is greatly influenced by the design rule compared to the line / space pattern. In other words, as the device becomes highly integrated, as the size of the device decreases and the distance between the peripheral wiring decreases, the aspect ratio, which is a ratio of the diameter and the depth of the contact, increases, thereby forming a contact. It is important in the method of forming the device. Therefore, in the highly integrated semiconductor device having the multilayer conductive wiring, a precise and strict alignment between the masks is required in the contact forming process, so that the process margin is reduced or the process must be performed without margin.

1 is a plan view of a semiconductor device according to the prior art, Figures 2a to 2e is a cross-sectional view showing a method of forming a semiconductor device according to the prior art, (i) is a cross-sectional view cut y-y ', (ii) It is sectional drawing which cut x-x '.

As shown in FIG. 2A, an insulating film 16 is formed on the semiconductor substrate 10 on which the active region 14 defined as the device isolation film 12 is formed. Next, after forming a photoresist pattern (not shown) defining a recessed region on the insulating film 16, the photoresist pattern (not shown) is etched using an etching mask to etch the insulating film 16 and the semiconductor substrate 10. The set 18 is formed.

As shown in FIG. 2B, after the conductive material is formed over the entire area including the recess 18, an etch back is performed to form the buried gate 20 in the recess 18.

As shown in FIG. 2C, a capping insulating film 18 is formed over the entire area including the buried gate 20, and an insulating film 22 is formed over the buried gate 20.

As shown in FIG. 2D, after the photoresist pattern (not shown) defining the bit line contact is formed on the insulating layer 22, the photoresist pattern (not shown) is etched into the insulating film 22 and the capping insulating film 18. ) And the insulating layer 16 are etched to form bit line contact holes (not shown). Next, the conductive material 24 is formed on the whole including the bit line contact hole (not shown). Subsequently, although not illustrated, a bit line contact is formed by performing a planarization etching process on the conductive material 24 to expose the insulating layer 22.

As shown in FIG. 2E, the bit line electrode 26, the barrier metal 28, and the hard mask layer 30 are formed over the entire surface including the conductive material 24, and then the top of the hard mask layer 30 is formed. A photoresist pattern (not shown) defining a bit line is formed on the hard mask layer 30, the barrier metal 28, the bit line electrode 26, and the insulating layer 22 so that the insulating layer 16 is exposed as an etch mask. ) And the capping insulating layer 18 are etched to form a bit line.

Referring to the process illustrated in FIG. 2D, it can be seen that a photoresist pattern (not shown) forming process, that is, a mask process, for exposing the active region 14 is involved to form the bit line contact. However, there is a limit in defining a photoresist pattern that defines a fine contact hole due to high integration of a semiconductor device, which makes it difficult to form a contact hole.

According to the present invention, when a bit line contact of a semiconductor device including a buried gate is defined using a photoresist pattern, it is difficult to accurately implement the photoresist pattern as the bit line contact is miniaturized due to the high integration of the semiconductor device, and thus the bit line contact is not formed. To solve this problem.

The semiconductor device of the present invention is planarized with a conductive material provided on the device isolation layer and the active region and the bit line conductive layer having the same width as the conductive material, and the bit line conductive layer on sidewalls of the conductive material and the bit line conductive layer. And an insulating film having a height.

In this case, a lower portion of the insulating layer is partially embedded in the device isolation layer and the active region.

And a buried gate buried in the device isolation layer and the active region under the insulating film.

The hard mask layer may be further provided on the bit line conductive layer.

In this case, the hard mask layer and the sidewalls of the insulating film further comprises a spacer.

And an interlayer insulating film provided on the bit line conductive layer.

And a storage electrode contact between the spacer and the interlayer insulating layer.

A method of forming a semiconductor device according to an embodiment of the present invention includes forming a buried gate embedded in an isolation layer and an active region, forming an insulating film on the buried gate, forming a conductive material between the insulating film, and forming a conductive material on the conductive material. Forming a bit line conductive layer on the device isolation layer or the active region, and forming a bit line having a stacked structure of the bit line conductive layer and the conductive material on the device isolation layer or the active region. It is characterized by including.

The buried gate may be formed by forming a sacrificial insulating layer and a first hard mask layer on the entirety of the device isolation layer and the active region and a photoresist pattern defining a recess on the first hard mask layer. Forming a recess by etching the first hard mask layer, the sacrificial insulating layer, the device isolation layer, and the active region by using the photoresist pattern as an etch mask, and embedding a conductive material for a buried gate in the recess. Characterized in that it comprises a step.

 The forming of the insulating film may include forming an insulating film over the entire surface, performing a planarization etching process on the insulating film to expose the sacrificial insulating film, and removing only the sacrificial insulating film.

In this case, removing only the sacrificial insulating layer may be performed by using an etching selectivity between the insulating layer and the sacrificial insulating layer.

The etch selectivity of the insulating layer may be lower than that of the sacrificial insulating layer.

In the forming of the conductive material, the conductive material may be formed to have a thickness lower than that of the insulating film.

The forming of the bit line conductive layer may include forming the bit line conductive layer over the entire portion including the conductive material, and performing a planarization etching process on the bit line conductive layer to expose the insulating layer. Characterized in that it comprises a step.

The forming of the bit line may include forming a second hard mask layer on the bit line conductive layer, forming a photoresist pattern defining a bit line on the second hard mask layer, and forming the photoresist layer. And etching the second hard mask layer, the bit line conductive layer, and the conductive material using the pattern as an etching mask.

And after the forming of the bit line, forming a spacer insulating material on the sidewalls of the bit line and the insulating film, forming an interlayer insulating film over the entire surface including the spacer insulating material, and forming the interlayer insulating film on the interlayer insulating film. Forming a photoresist pattern defining a storage electrode contact; forming a storage electrode contact hole by etching the interlayer insulating layer using the photoresist pattern as an etch mask; and filling a conductive material in the storage electrode contact hole to form a storage electrode contact. It characterized in that it further comprises the step of forming.

The present invention can reduce the time and cost of performing the mask process by not performing the mask process in forming the bit line contact, and fundamentally solves the problem that the bit line contact is not accurately implemented due to high integration. To provide the effect.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3 is a plan view showing a semiconductor device according to the present invention, Figure 4 is a cross-sectional view showing a semiconductor device according to the invention, Figures 5a to 5g is a cross-sectional view showing a method of forming a semiconductor device according to the present invention (ⅰ ) Is a cross-sectional view of y-y1, and (ii) is a cross-sectional view of x-x1.

As shown in FIG. 4, the semiconductor device of the present invention includes a conductive material 116, a barrier metal layer 118, and an entire semiconductor substrate 100 including an active region 104 defined as an isolation layer 102. And a bit line having a stacked structure of the bit line conductive layer 120 and the hard mask layer 122. That is, the bit line according to the present invention preferably has a structure in which a conductive material 116 is provided below the bit line conductive layer 120 on the device isolation layer 102 as well as the active region 104. The conductive material 116 may be a bit line contact, and the conductive material 116 and the bit line conductive layer 120 may have the same width. In addition, an insulating layer 114 provided on the sidewalls of the stacked structure of the conductive material 116, the barrier metal layer 118, and the bit line conductive layer 120 to have a flattening height with an uppermost portion of the bit line conductive layer 120. More). In this case, the insulating layer 114 may be provided on the buried gate 112 embedded in the device isolation layer 102 and the active region 104. In addition, the semiconductor device may further include a spacer 126 provided on sidewalls of the hard mask layer 122 and the insulating layer 114.

As shown in FIG. 5A, an insulating layer 106 and a hard mask layer 108 are formed on the semiconductor substrate 100 including the active region 104 defined as the device isolation layer 102. Next, after the photoresist pattern (not shown) defining the recess is formed on the hard mask layer 108, the hard mask layer 108, the insulating layer 106, and the semiconductor are formed using the photoresist pattern (not shown) as an etching mask. The substrate 100 is etched to form the trench 110. Thereafter, the photoresist pattern (not shown) and the hard mask layer 108 are removed. Here, the insulating film 106 preferably has a sufficiently thick thickness to define the thickness of the insulating film that prevents oxidation of the buried gate formed in a subsequent step.

As shown in FIG. 5B, after the conductive material is formed over the entire portion including the trench 110, the buried gate 112 partially embedded in the trench 110 is formed by etching back the conductive material. In this case, the conductive material is preferably tungsten. Subsequently, after the insulating film 114 is formed, a planarization process is performed to expose the insulating film 106. Here, the insulating film 114 is preferably formed of a material having an etching selectivity different from that of the insulating film 106. More specifically, the insulating film 114 has a lower etching selectivity than the insulating film 106, so that the insulating film 106 is not etched when the insulating film 106 is etched. For example, the insulating film 114 is preferably a nitride film. The insulating film 114 preferably has a thickness thick enough to prevent oxidation of the buried gate 112.

As shown in FIG. 5C, after the photoresist pattern (not shown) exposing the cell region is formed, the insulating layer 106 of the cell region is removed using the photoresist pattern as an etch mask. Here, since the insulating film 106 and the insulating film 114 have different etching selectivity as described above, the insulating film 114 is not removed when the insulating film 106 is etched. More specifically, the insulating film 114 preferably has a lower etching selectivity than the insulating film 106. As a result, only the insulating film 114 provided on the buried gate 112 becomes protruded.

As shown in FIG. 5D, the conductive material 116 is formed on the entire top including the insulating layer 114. In this case, the conductive material 116 is preferably formed lower than the height of the insulating film 114. The reason for this is to further form a bit line conductive layer on the conductive material 116 so as to be the same as the height of the insulating film 114 in a subsequent process.

In this case, the conductive material 116 serves as a bit line contact that electrically connects the active region 104 and the bit line formed by a subsequent process. That is, by forming a bit line contact by a deposition method without performing a separate mask process to define a bit line contact as in the prior art, the time required for the process fundamentally solves the problem that the bit line contact is not implemented And cost can be reduced.

As shown in FIG. 5E, the barrier metal layer 118, the bit line conductive layer 120, and the hard mask layers 122 and 124 are disposed on the entire top including the insulating layer 114 and the conductive material 116. Form. In this case, the bit line conductive layer 120 preferably has a height flattened with the insulating layer 114.

As shown in FIG. 5F, after the photoresist pattern (not shown) defining the bit line is formed on the hard mask layer 124, the semiconductor substrate 100 is exposed with the photoresist pattern (not shown) as an etch mask. The hard mask layers 124 and 122, the bit line conductive layer 120, the barrier metal layer 118, and the conductive material 116 are etched to form bit lines. Thereafter, the hard mask layer 124 is removed. Here, the bit line has the structure described above not only on the active region 104 but also on the device isolation layer 102. That is, unlike the structure that is provided only on the active region 104 by defining a mask process only in a region where the bit line contact is to be provided as in the related art, the device isolation layer 102 provided between the active regions 104 is formed. The region also has a structure as described above in a continuous form.

As shown in FIG. 5G, an insulating material 126 for spacers is formed over the entirety including the bit lines. Next, after the interlayer insulating layer 128 is formed over the entire surface, a planarization etching process is performed on the interlayer insulating layer 128 to expose the hard mask layer 122. Thereafter, a photoresist pattern (not shown) defining a storage electrode contact hole is formed over the entire surface, and then the interlayer insulating layer 128 is etched to expose the semiconductor substrate 100 using an etching mask, thereby storing the storage electrode contact hole (not shown). Is preferably defined. Subsequently, after the conductive material is formed on the whole including the storage electrode contact hole (not shown), the planar etching process is performed to form the storage electrode contact 130.

As described above, the method for forming a bit line according to the present invention does not perform a separate mask process for defining a bit line contact, thereby achieving high integration and easily forming the bit line contact even when the pattern is miniaturized. Simplification offers the effect of reducing process costs and time.

1 is a plan view of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art, (i) is a cross-sectional view of y-y ', and (ii) is a cross-sectional view of x-x'.

3 is a plan view showing a semiconductor device according to the present invention.

4 is a cross-sectional view showing a semiconductor device according to the present invention.

5A to 5G are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention, (i) is a cross-sectional view of y-y1, and (ii) is a cross-sectional view of x-x1.

Claims (16)

A conductive material provided on the device isolation layer and the active region; A bit line conductive layer having the same width as the conductive material; And An insulating film having a height flattened with the bit line conductive layer on sidewalls of the conductive material and the bit line conductive layer; And a hard mask layer provided on the bit line conductive layer. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1, And a lower portion of the insulating layer is partially embedded in the device isolation layer and the active region. Claim 3 was abandoned when the setup registration fee was paid. The method according to claim 1, Under the insulating film And a buried gate embedded in the device isolation layer and the active region. delete Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 1, And a spacer on sidewalls of the hard mask layer and the insulating layer. Claim 6 was abandoned when the registration fee was paid. The method according to claim 1, And an interlayer insulating film provided on the bit line conductive layer. Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 5, And a storage electrode contact between the spacers. Forming a buried gate embedded in the device isolation layer and the active region; Forming an insulating film on the buried gate; Forming a conductive material between the insulating films; Forming a bit line conductive layer on the conductive material to have a height flattened with the insulating layer; And Forming a bit line having a stacked structure of the bit line conductive layer and the conductive material on the device isolation layer or the active region; Forming the conductive layer for the bit line Forming a conductive layer for the bit line on the whole of the conductive material; And And performing a planarization etching process on the bit line conductive layer to expose the insulating layer. Claim 9 was abandoned upon payment of a set-up fee. The method according to claim 8, Forming the buried gate is Forming a sacrificial insulating film and a first hard mask layer over the device isolation layer and the active region; Forming a photoresist pattern defining a recess on the first hard mask layer; Forming a recess by etching the first hard mask layer, the sacrificial insulating layer, the device isolation layer, and the active region using the photoresist pattern as an etch mask; And And embedding a conductive material for a buried gate in the recess. Claim 10 was abandoned upon payment of a setup registration fee. The method according to claim 9, Forming the insulating film Forming an insulating film over the whole; Performing a planar etching process on the insulating layer to expose the sacrificial insulating layer; And And removing only the sacrificial insulating film. Claim 11 was abandoned upon payment of a setup registration fee. Removing only the sacrificial insulating film And removing the insulating layer and the sacrificial insulating layer by using an etching selectivity. Claim 12 was abandoned upon payment of a registration fee. The method according to claim 10, And the etching selectivity of the insulating layer is lower than that of the sacrificial insulating layer. Claim 13 was abandoned upon payment of a registration fee. The method according to claim 8, Forming the conductive material A method of forming a semiconductor device, characterized in that formed on the entire upper portion having a lower thickness than the insulating film. delete Claim 15 was abandoned upon payment of a registration fee. The method according to claim 8, Forming the bit line having a stacked structure of the conductive layer for the bit line and the conductive material on the device isolation layer or the active region Forming a second hard mask layer on the bit line conductive layer; Forming a photoresist pattern defining a bit line on the second hard mask layer; And And etching the second hard mask layer, the bit line conductive layer, and the conductive material using the photoresist pattern as an etch mask. Claim 16 was abandoned upon payment of a setup registration fee. The method according to claim 8, After forming the bit line having the stacked structure of the bit line conductive layer and the conductive material on the device isolation layer or the active region, Forming a spacer insulating material on sidewalls of the bit line and the insulating film; Forming an interlayer insulating film over the entirety of the spacer insulating material; Forming a photoresist pattern defining a storage electrode contact on the interlayer insulating film; Etching the interlayer insulating layer using the photoresist pattern as an etching mask to form a storage electrode contact hole; And filling a conductive material in the storage electrode contact hole to form a storage electrode contact.

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