KR100860975B1 - Internal Voltage generating Ciucuit for Semiconductor Device - Google Patents

Abstract

The present invention relates to an internal voltage generation circuit of a semiconductor device having enhanced immunity to temperature. The internal voltage generation circuit of a semiconductor device according to the present invention includes: a temperature information output device for measuring temperature of the semiconductor device and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels; And a voltage selector which selects an internal voltage among the plurality of voltages according to the temperature information.

Semiconductor device, internal voltage, temperature information output device

Description

Internal voltage generating circuit of semiconductor device. {Internal Voltage generating Ciucuit for Semiconductor Device}

1 is a block diagram of a conventional internal voltage generation circuit.

FIG. 2 is a detailed circuit diagram of the bandgap portion 10 of FIG. 1.

3 is a detailed circuit diagram of the voltage generation unit 20 of FIG. 1.

4 is a configuration diagram of a conventional negative voltage pumping circuit.

5 is a detailed circuit diagram of the negative voltage detecting unit 41 of FIG. 4.

6 is a configuration diagram of a conventional high voltage pumping circuit.

FIG. 7 is a detailed circuit diagram of the high voltage detecting unit 61 of FIG. 6.

8 is a configuration diagram of a conventional core voltage generation circuit.

9 is a configuration diagram of an internal voltage generation circuit of a semiconductor device according to an embodiment of the present invention.

10 is a configuration diagram of an embodiment of the temperature information output device 300 of FIG. 9.

11 shows when each flag signal TEMPA, TEMPB, TEMPC is enabled.

FIG. 12 is a diagram illustrating an embodiment of the voltage generator 200 of FIG. 9.

FIG. 13 is a diagram illustrating an embodiment of the voltage selector 400 of FIG. 9.

* Explanation of symbols for the main parts of the drawings

100: band gap portion 200: voltage generation portion

300: temperature information output device 400: voltage selector

The present invention relates to a semiconductor device, and more particularly to a circuit for generating an internal voltage used in the semiconductor device.

In many semiconductor devices, various internal voltages having a different level from a power supply voltage supplied from outside are used. In particular, in the case of a semiconductor memory device (DRAM), it is higher than the external potential (VDD) applied to the gate (word line) of the gate of the cell transistor, VCORE, which is a voltage used in the core region of the memory device. VPP, the voltage, and negative voltage (VBB), which is lower than the ground voltage (VSS) used in the bulk of the cell transistor, are used.

Charge pumping (VBB, VPP) and down converting (VCORE) are used to create these internal voltages. After making the internal voltage (internal reference voltage (VREF)) as a reference, and using this method to create a second internal voltage (VBB, VPP, VCORE) again.

1 is a block diagram of a conventional internal voltage generation circuit.

The conventional internal voltage generation circuit VREF includes a band gap unit 10 and a voltage generation unit 20.

The bandgap unit 10 creates VBG, which is a voltage having a constant level with respect to PVT (Process, Voltage, Temperature) changes, and the voltage generator 20 uses the VBG to generate the internal voltage VREF. Create The bandgap 10 and the voltage generator 20 will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a detailed circuit diagram of the bandgap portion 10 of FIG. 1.

The bandgap portion uses a vertical PNP BJT transistor with little change in process. This is done by creating a Proportional to Absolute Temperature (PTAT) term that increases the amount of current flowing with temperature and a Complementary proportional to Absolute Temperature (CTAT) term that decreases the amount of current flowing with temperature.

In this circuit, the formula for a typical diode current versus voltage expressed as the emitter current of two BJTs (Q1, Q2) with a ratio of N: 1 under the assumption that node A and node B are virtually shorted is: .

Applying this to Q1 and Q2, respectively, is as follows.

,

,

Where I _Q1 and I _Q2 are the emitter currents flowing through each BJT.

If the potential of node A and node B is the same, the IPTAT current flowing through the resistor R1 is as follows.

And under the same circumstances, the ICTAT current flowing through the R2 resistor is the same.

Assuming the same amount of current flows through the same size MOS, the currents of M * IPTAT and K * ICTAT become M * IPTAT and K * ICTAT as indicated.

Based on this, the output voltage of the bandgap portion VBG is expressed as follows.

Properly adjust the values of M, R1, R2, R3, K and M so that temperature compensation occurs, the output VBG will have a constant value for PVT change. In general, the N, R1, R2, and R3 values are fixed and only the K and M values are adjusted to adjust the amount of current in PTAT and CTAT.

That is, the bandgap portion outputs VBG, which is a voltage having a constant value in the PVT change.

3 is a detailed circuit diagram of the voltage generator 20 of FIG. 1.

The voltage generator includes an OP amplifier 21, a PMOS transistor 22, and resistors 23.

In operation, VBG, which is the output voltage of the bandgap unit 10, is input through the OP amplifier, and the output of the OP amplifier is input to the gate of the PMOS transistor to drive it, and eventually the potential level of both inputs of the OP amplifier. Is the same. In other words, the potential level of the node C becomes VBG.

The potential VBG of the node C is divided by the resistors 23 and 24. Therefore, the internal voltage VREF = {VBG * (24 resistance + 23 resistance) / 24 resistance} according to the resistance ratio.

The internal voltage VREF generated through the above process may be used as an internal voltage of the semiconductor device, but may also be used to generate other internal voltages (eg, VCORE, VBB, and VPP).

Hereinafter, an example in which the internal voltage VREF made in the internal voltage generation circuit of FIG. 1 is used will be described with reference to FIGS. 4 through 8.

4 is a configuration diagram of a conventional negative voltage pumping circuit.

The negative voltage pumping circuit includes a negative voltage detecting unit 41, an oscillator unit 42, and a voltage pumping unit 43 + 44.

The negative voltage detection unit 41 outputs a detection signal bbweb for determining whether to drive the voltage pump 43 + 44 as a portion for detecting the level of the negative voltage VBB. In the negative voltage detecting unit 41 for detecting the negative voltage VBB, an internal voltage generated in the internal voltage generation circuit of FIG. 1 described above (VREFB: adds a subscript B in the sense that it is used to pump VBB) is used. This will be described later with reference to FIG. 5. The oscillator unit 42 receives the sensing signal bbweb and outputs a periodic wave osc. The voltage pumping unit 43 + 44 pumps the negative voltage VBB in response to the periodic wave osc output from the oscillator unit 42. The voltage pumping unit 43 + 44 includes the pump control unit 43 and the charge pump. It may be composed of a portion 44. In detail, the pump control unit 43 outputs the pump control signals p1, p2, g1, and g2 in response to the output signal osc of the oscillator unit, and the charge pump unit 44 outputs the pump control signals p1, p2, and g1. In response to g2), the negative voltage VBB is pumped.

Briefly describing the overall operation, when the level of the negative voltage VBB sensed by the negative voltage detector 41 is sufficiently low, the pumping operation is stopped, and the negative voltage VBB detected by the negative voltage detector 41 is stopped. When the level is high, the negative voltage (VBB) pumping operation is performed in the voltage pumping unit 43 + 44.

FIG. 5 is a detailed circuit diagram of the negative voltage detecting unit 41 of FIG. 4.

As shown in the figure, the ground voltage VSS is applied to the gate of the transistor P01, and the negative voltage VBB is applied to the gate of the transistor P02, respectively. Transistors P01 and P02 operate in a linear region and act as a resistor to distribute the voltages of high potential (VREFB) and low potential (VSS). For example, when the absolute value of the negative voltage VBB is small (meaning that the level of the negative voltage is high) and the resistance of the transistor P02 becomes large, the potential of the DET node is increased, and the sense signal bbweb is generated in the inverter I03. It will be output 'low' (to pump negative voltage), and if the absolute value of negative voltage (VBB) is large (because the level of negative voltage is low), the resistance of transistor P03 decreases, the potential of DET node will be lowered and inverter At I03, the sense signal bbweb will be output high (stops negative voltage pumping).

That is, the negative voltage detecting unit 41 detects the level of the negative voltage VBB by the voltage distribution of the transistors P01 and P02 receiving the ground voltage VSS and the negative voltage VBB, respectively.

As the high voltage in the negative voltage sensing unit 41 and the bulk voltage of the transistor P02, the internal voltage VREFB made in the internal voltage generation circuit of FIG. 1 may be used, and accordingly, the detection signal according to the level of the internal voltage VREFB may be used. There is a change in the negative voltage (VBB) level at which bbweb) is enabled.

6 is a configuration diagram of a conventional high voltage pumping circuit.

The high voltage pumping circuit includes a high voltage detecting unit 61, an oscillator unit 62, and a voltage pumping unit 63 + 64. The basic role of each part is the same as that of the negative voltage pumping circuit of FIG. 4, but because the high voltage VPP is pumped instead of the negative voltage VBB, a slight change is made.

The high voltage detector 61 detects the level of the high voltage VPP and outputs a detection signal ppes that determines whether to drive the voltage pump 63 + 64. In the high voltage detecting unit 61 for detecting the negative voltage VPP, an internal voltage VREFP (added in the sense that it is used to pump VPP) is used in the internal voltage generation circuit of FIG. This will be described later with reference to FIG. 7. The oscillator 62 receives a sensing signal ppes and outputs a periodic wave osc. The voltage pumping unit 63 + 64 pumps the high voltage VPP in response to the periodic wave output from the oscillator unit 62. The voltage pumping unit 63 + 64 includes the pump control unit 63 and the charge pump unit 64. It can be configured as. In detail, the pump control unit 63 outputs the pump control signals p1, p2, g1, and g2 in response to the output signal osc of the oscillator unit 62, and the charge pump unit 64 outputs the pump control signal p1. , p2, p3, g2) to pump the high voltage (VPP).

Briefly describing the overall operation, when the level of the high voltage VPP detected by the high voltage detector 61 is sufficiently high, the pumping operation is stopped, and the level of the high voltage VPP detected by the high voltage detector 61 is stopped. In the low case, the high voltage (VPP) pumping operation is performed in the voltage pumping unit 63 + 64.

FIG. 7 is a detailed circuit diagram of the high voltage detecting unit 61 of FIG. 6.

The high voltage detector detects the level of the high voltage VPP through voltage division of the high voltage VPP fed back from the charge pump unit 64 and comparison with the internal voltage VREFP. That is, when the high voltage VPP falls below a desired target level, the potential of the node d becomes lower than the internal voltage VREFP. Then, the transistor N05 forming the current mirror is turned on more strongly than the transistor N04, so that the logic level of the node f becomes 'low'. Therefore, sense signal ppes is output 'high' in inverter I03 (this causes high voltage to be pumped).

On the contrary, when the high voltage VPP is higher than the desired target level, the potential of the node d becomes higher than the reference voltage VREFP. At this time, the logic level of node f becomes 'high', and the sense signal ppes is output as 'low' in inverter I03. (The pumping of high voltage is stopped.)

The high voltage detection unit 61 uses the internal voltage VREFP made in the internal voltage generation circuit of FIG. 1 as a reference voltage to be compared with the high voltage VPP. Accordingly, there is a change in the level of the high voltage VPP in which the detection signal ppes is disabled according to the level of the internal voltage VREFP, which means that the level of the high voltage VPP being pumped changes.

8 is a configuration diagram of a conventional core voltage generation circuit.

Conventional core voltage generator (VCORE generator) down converts the external power to a constant internal potential by using a current mirror-type unit buffer buffer to make a constant internal potential, using this Make it a way to drive.

The voltage input to the circuit includes external voltages VDD and VSS, the ON signal indicating that the circuit can operate reliably and when it can be operated, and the internal voltage used as a reference voltage for making the core voltage VCORE. Add the subscript C because it is an internal voltage to make a voltage). The output voltage is the core voltage VCORE.

Explaining the approximate operation, the current mirror starts to operate when an ON signal is signaled to indicate that the circuit is operating normally. When the current mirror starts to operate, the potentials of VREFC and VCORE_Half become equal, and the VCORE voltage that is twice the value of VCORE_Half is output to the VCORE node.

Since the core voltage generation unit receives the internal voltage VREFC and outputs the core voltage VCORE which becomes the level of the internal voltage VREFC * 2, the internal voltage VREFC generated in the internal voltage generation circuit of FIG. ) Affects the level of the core voltage VCORE.

The conventional internal voltage generation circuit shown in FIG. 1 outputs an internal voltage VREF having a constant value according to temperature. However, in the case of VPP in the semiconductor memory device, it is advantageous that the temperature increases as the temperature decreases, and that the VBB increases as the temperature decreases (meaning that the absolute value decreases due to the negative voltage) in terms of write recovery time (tWR).

At low temperatures, the threshold voltage Vth of the transistor is increased. In this situation, it is necessary to supply a sufficient amount of charge when data is stored in the cell by raising the level of VPP and raising the level of VBB.

In addition, at a high temperature, on the contrary, it is necessary to lower the level of VBB. In the case of high temperature, the leakage current is increased so that the level of VBB is low to prevent this.

As described above, it is necessary to change the level of the internal voltage in accordance with the temperature in the semiconductor device. However, the conventional internal voltage generation circuit supplies only the internal voltage VREF having a constant magnitude with respect to the change in temperature. There is a problem that does not satisfy.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an internal voltage generation circuit of a semiconductor device that generates an internal voltage that varies with temperature.

An internal voltage generation circuit of a semiconductor device according to an embodiment of the present invention for achieving the above object includes a temperature information output device for measuring the temperature of the semiconductor device and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels; And a voltage selector which selects an internal voltage among the plurality of voltages according to the temperature information.

The voltage generation unit may generate the plurality of voltages through voltage division.

The internal voltage generation circuit may further include a band gap part generating a constant reference voltage which is not affected by temperature, and the voltage generation part may divide the reference voltage to generate the plurality of voltages. have.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

9 is a configuration diagram of an internal voltage generation circuit of a semiconductor device in accordance with an embodiment of the present invention.

The internal voltage generation circuit of the semiconductor device according to the present invention includes a voltage generator 200, a temperature information output device 300, and a voltage selector 400.

The temperature information output device 300 measures temperature of the semiconductor device and outputs temperature information TEMPA, TEMPB, and TEMPC. The temperature information may be in various forms. Here, the temperature information is shown in the form of displaying temperature information by flag signals TEMPA, TEMPB, and TEMPC, which are signals indicating temperature intervals.

The voltage generator 200 generates a plurality of voltages VREF_1, VREF_2, and VREF_3 having different levels. Here, the plurality of voltages VREF_1, VREF_2, and VREF_3 refer to voltages to be used as internal voltages VREF. The characteristic of the voltage generation unit of the present invention is to generate a plurality of voltages VREF_1, VREF_2, and VREF_3 having different levels. Therefore, a plurality of voltages VREF_1, VREF_2, and VREF_3 may be generated by voltage-dividing a power supply voltage (for example, VDD). As shown in the drawing, a plurality of voltages are received by receiving VBG from the band gap unit 100. (VREF_1, VREF_2, VREF_3) may be generated.

The voltage selector 400 selects the internal voltage VREF among the plurality of voltages VREF_1, VREF_2, and VREF_3 according to the temperature information TEMPA, TEMPB, and TEMPC provided from the temperature information output device 300.

The bandgap unit 100 outputs VBG, which is a voltage having a constant value with respect to the PVT change, as described in the prior art. As described above, when VBG is used when the voltage generation unit 200 generates the plurality of voltages VREF_1, VREF_2, and VREF_3, the internal voltage generation circuit of the semiconductor device of the present invention includes the band gap unit 100. .

FIG. 10 is a configuration diagram of an embodiment of the temperature information output device 300 of FIG. 9.

The temperature information output device (On Die Thermal Sensor) includes a temperature sensing unit 310 for outputting a voltage corresponding to the temperature one-to-one; An analog-digital converter 320 for converting the voltage output from the bandgap portion into a digital code; And a flag signal generator 330 which receives a digital code and generates a plurality of flag signals that are enabled at a specific temperature.

Specifically, the temperature sensing unit 310 has a change in the base-emitter (Vbe) of the bipolar junction transistor (BJT) of about -1.8mV in a bandgap circuit that is not affected by temperature or power supply voltage. It senses the temperature by using / ℃. The voltage VTEMP corresponding to the temperature is output 1: 1 by amplifying the base-emitter voltage Vbe of the slightly varying bipolar junction transistor. That is, the base-emitter voltage Vbe of the bipolar junction transistor that is lowered as the temperature is outputted is output. Since the temperature sensing unit 310 of the temperature information output device is a kind of band gap circuit, when the internal voltage generation circuit of the semiconductor device of the present invention includes the band gap unit 100, the temperature sensing unit of the temperature information output device is implemented. The 310 and the bandgap portion 100 of FIG. 9 may be configured in the same block.

The analog-to-digital converter 320 converts the voltage VTEMP output from the bandgap unit 310 into a digital code and outputs the digital-coded analog coder. Tracking Analog-Digital Converter) is widely used.

The flag signal generator 330 decodes a digital code and outputs a plurality of flag signals TEMPA, TEMPB, and TEMPC indicating a temperature section.

Each flag signal TEMPA, TEMPB, TEMPC is enabled when the temperature is above a certain temperature. FIG. 11 shows when each flag signal TEMPA, TEMPB, and TEMPC is enabled. The TEMPA, TEMPB, and TEMPC signals are enabled in order from low to high temperatures. Therefore, when TEMPA = 'low', TEMPB = 'low', and TEMPC = 'low', this indicates the lowest temperature range, and when TEMPA = 'high', TEMPB = 'high', TEMPC = 'high' Indicates that the interval is high.

For reference, in the exemplary embodiment shown in the drawing, three flag signals TEMPA, TEMPB, and TEMPC are output, but this is only an example, and the number of flag signals may be changed according to design.

FIG. 12 is a diagram illustrating an embodiment of the voltage generator 200 of FIG. 9.

The voltage generator generates a plurality of voltages VREF_1, VREF_2, and VREF_3 having different levels, and may generate the plurality of voltages VREF_1, VREF_2, and VREF_3 through voltage division.

Basically, voltages having different levels may be generated by voltage-dividing the power supply voltage VDD or an externally input voltage. However, in the drawing, VBG is input from the bandgap unit 100 and voltage-divided by this, thereby a plurality of voltages VREF_1, VREF_2, VREF_3) is shown for the embodiment to generate.

Referring to the figure, the voltage generator receives the VBG through the operational amplifier (OP amp) 201. The output of the operational amplifier 201 drives the transistor P08, and the g node, which is a positive terminal of the operational amplifier, is at the same potential level as VBG. The potential of the node g (= VBG) is divided according to the resistance ratios of the resistors R4 to R11 to generate a plurality of voltages VREF_1, VREF_2, and VREF_3 having different levels.

FIG. 13 is a diagram illustrating the configuration of the voltage selector 400 of FIG. 9.

The voltage selector includes a plurality of passgates PG1, PG2, and PG3 that receive a plurality of voltages VREF_1, VREF_2, and VREF_3, respectively, and the plurality of passgates PG1, PG2, and PG3 include temperature information TEMPA. , TEMPB, TEMPC) on / off. The voltage selected by the passgate turned on by the temperature information is output as the internal voltage VREF.

In detail, the flag signals TEMPA, TEMPB, and TEMPC indicating the temperature information and the pass gates PG1, PG2, and PG3 respectively correspond one-to-one. By default, the passgate is turned on when the flag signal corresponding to the passgate is enabled. However, even if the flag signal corresponding to itself is enabled, it is turned off when the higher flag signal-the flag signal enabled at a higher temperature-is enabled. For example, when TEMPA is enabled, passgate PG1 is on, but when TEMPB is also enabled, passgate PG1 is off. This is because the passgate PG2 must be turned on in this case. The passgate PG3 corresponding to the TEMPC representing the highest temperature is turned on when only the TEMPC is enabled. This is because there is no flag signal higher than the TEMPC in this case.

As shown in the figure, the voltage selector includes inverters I04 and I05 which receive flag signals TEMPA and TEMPB corresponding to pass gates PG1 and PG2; And outputs of the passgates PG1 and PG2 to the outputs of the NOA gates NO01 and NO02, including the NOA gates NO01 and NO02 that receive the outputs of the inverters I04 and I05 and the flag signals TEMPB and TEMPC. The on / off control is configured, and only the pass gate PG3 corresponding to the highest temperature may be directly controlled by the flag signal TEMPC corresponding to the highest temperature.

In the embodiment shown in the drawing, VREF_1, VREF_2, and VREF_3 are configured to be sequentially input to PG1, PG2, and PG3, so that the higher the temperature, the lower the internal voltage VREF is output (inversely proportional to temperature). The present invention may be configured to output a high level of the internal voltage VREF as the temperature is higher (proportional to temperature). In this case, VREF_1, VREF_2, and VREF_3 may be sequentially input to PG3, PG2, and PG1. .

The internal voltage VREF generated by the internal voltage generation circuit according to the present invention may be used directly as the internal voltage of the semiconductor device, and other internal voltages (eg, VBB, VPP, VCORE, as shown in the application of the prior art). Etc.) may be used as a reference voltage in generating the same. When the generated internal voltage VREF is used directly as the internal voltage of the semiconductor device as well as the reference voltage VREF used when generating other internal voltages VBB, VPP, and VCORE, Since the level of the voltage VREF can be varied with temperature, the level of newly generated internal voltages VBB, VPP, and VCORE can also be varied with temperature.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be appreciated by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention described above, there is an advantage that it is possible to change the level of the internal voltage of the semiconductor device according to the temperature.

Therefore, it is possible to satisfy the level of the internal voltage according to the temperature required by the semiconductor device.

In particular, when the present invention is used to pump VPP in a semiconductor memory device, it is possible to supply a sufficient amount of charge when data is stored in a cell by increasing the level of the internal voltage VPP as the temperature decreases. have.

In addition, when used to pump the VBB in the semiconductor memory device has the advantage that it is possible to reduce the leakage current (leakage current) in the cell by lowering the level of VBB as the temperature increases.

Claims (13)

delete delete A temperature information output device for measuring temperature of the semiconductor device and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels through voltage division; A voltage selector which selects an internal voltage among the plurality of voltages according to the temperature information; And It includes a band gap portion for generating a constant reference voltage is not affected by temperature, And the voltage generator generates the plurality of voltages by voltage-dividing the reference voltage. A temperature information output device for measuring temperature of the semiconductor device and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels; And A voltage selector configured to select an internal voltage among the plurality of voltages according to the temperature information; The voltage selector, A plurality of passgates receiving the plurality of voltages, respectively, And the plurality of passgates are turned on / off by the temperature information. A temperature information output device for measuring temperature of the semiconductor device and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels; And A voltage selector configured to select an internal voltage among the plurality of voltages according to the temperature information; The temperature information, And a plurality of flag signals each enabled at a predetermined temperature. The method of claim 5, The voltage selector, A plurality of passgates receiving the plurality of voltages, respectively, And the plurality of pass gates are turned on / off by the plurality of flag signals. The method of claim 6, The passgate and the flag signal correspond one to one, The passgate, And the flag signal corresponding to the pass gate is turned on when the flag signal is enabled. The method of claim 7, wherein The passgate, And an off state when the flag signal higher than the flag signal corresponding to the pass gate, which is enabled at a higher temperature, is turned off. The method of claim 8, The voltage selector, An inverter receiving the flag signal corresponding to the passgate; And an on-off control of the pass gate by an output of the noah gate, including a noah gate receiving the output of the inverter and the upper flag signal. Only the pass gate corresponding to the highest temperature is directly controlled by the flag signal corresponding to the highest temperature. A temperature information output device for measuring temperature of the semiconductor device and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels; And A voltage selector configured to select an internal voltage among the plurality of voltages according to the temperature information; The temperature information output device, A voltage sensing unit sensing a temperature and outputting a voltage corresponding to the temperature one-to-one; An analog-digital converter for converting the voltage into a digital code; And And a flag signal generator configured to receive the digital code and generate a plurality of flag signals that are enabled at a specific temperature. A temperature information output device for measuring temperature of the semiconductor memory device (DRAM) and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels; And A voltage selector configured to select an internal voltage among the plurality of voltages according to the temperature information; The internal voltage generation circuit of the semiconductor memory device (DRAM), wherein the internal voltage selected by the voltage selector is used as a reference voltage for making the core voltage VCORE of the memory device. A temperature information output device for measuring temperature of the semiconductor memory device (DRAM) and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels; And A voltage selector configured to select an internal voltage among the plurality of voltages according to the temperature information; And an internal voltage selected by the voltage selector is used as a reference voltage for pumping a high voltage VPP that is higher than a power supply voltage of the memory device. A temperature information output device for measuring temperature of the semiconductor memory device (DRAM) and outputting temperature information; A voltage generator configured to generate a plurality of voltages having different levels; And A voltage selector configured to select an internal voltage among the plurality of voltages according to the temperature information; And the internal voltage selected by the voltage selector is used as a reference voltage for pumping a negative voltage VBB which is lower than the ground voltage.

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