KR100855726B1 - Memory for thermal isolation of phase change memory cells, semiconductor memory device and method for fabricating a memory - Google Patents

Abstract

The memory comprises an array of memory cells, each memory cell comprising a resistive material; A first insulating material transversely surrounding the resistive material of each memory cell; And a heat spreader between the memory cells to insulate each memory cell.

Description

MEMORY FOR THERMAL ISOLATION OF PHASE CHANGE MEMORY CELLS, SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING A MEMORY}

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be more readily understood by reference to the following detailed description. The elements of the figures are not to scale with respect to each other. Like reference numerals designate corresponding similar parts.

1 illustrates one embodiment of an array of phase-change memory cells;

2 illustrates one embodiment of an array of phase-change memory cells comprising an insulating material;

3 illustrates another embodiment of an array of phase-change memory cells comprising an insulating material;

4A is a cross-sectional view of one embodiment of a phase-change memory element including insulating material;

4B is a cross-sectional view of another embodiment of a phase-change memory element that includes an insulating material;

4C is a cross-sectional view of another embodiment of a phase-change memory element including an insulating material;

5A is a cross-sectional view of another embodiment of a phase-change memory element that includes an insulating material;

5B is a cross-sectional view of another embodiment of a phase-change memory element that includes an insulating material;

6A is a cross-sectional view of another embodiment of a phase-change memory element that includes an insulating material.

FIG. 6B is a side cross-sectional view of the phase-change memory element illustrated in FIG. 6A;

FIG. 7 is a side view of one embodiment of a layout of a phase-change memory cell including a heat shield or spreader; FIG.

8 is a side view of another embodiment of a layout of phase-change memory cells including using an active metal line as a heat spreader;

9 is a plan view of one embodiment of an array of phase-change memory cells including a dummy ground line;

10A is a cross-sectional view of one embodiment of a layout of phase-change memory cells that includes a dummy ground line;

FIG. 10B is a side view of one embodiment of a layout of phase-change memory cells including a dummy ground line; FIG.

11 is a flow diagram illustrating one embodiment of a method of manufacturing a phase-change memory.

This application is related to US patent application Ser. No. 11 / 260,346, entitled “PHASE CHANGE MEMORY CELL,” filed October 27, 2005, which is incorporated herein by reference.

One form of non-volatile memory is resistive memory. Resistive memory uses the resistance value of a memory element to store one or more data bits. For example, a memory element programmed to have a high resistance value may represent a logic "1" data bit value, and a memory element programmed to have a low resistance value may represent a logic "0" data bit value. . The resistance value of the memory element is electrically switched by applying a voltage or current to the memory element. One type of resistive memory is magnetic random access memory (MRAM). Another form of resistive memory is phase-change memory. Although the present invention is described with respect to a phase-change memory, the present invention can be applied to any suitable type of resistive memory.

Phase-change memory uses a phase-change material for resistive memory elements. Phase-change materials exhibit two or more different states. The state of the phase-change material may also be referred to as an amorphous and crystalline state. In general, since the amorphous state exhibits higher resistivity than the crystalline state, the above states can be distinguished. In general, the amorphous state involves a more ordered atomic structure, while the crystalline state is characterized by a more ordered lattice. Some phase-change materials exhibit two or more crystalline states, such as face-centered cubic (FCC) states and hexagonal closest packing (HCP) states. These two crystalline states have different resistivities.

The phase change of the phase-change material can be reversibly induced. In this way, the phase-change material can change from an amorphous state to a crystalline state and also from a crystalline state to an amorphous state in response to a temperature change. Temperature changes for phase-change materials can be achieved in a variety of ways. For example, a laser can be directed to the phase-change material, a current can be driven through the phase-change material, or a current can be supplied through a resistive heater adjacent to the phase-change material. In either of these methods, controllable heating of the phase-change material induces a controllable phase change in the phase-change material.

Thermal crosstalk occurs when heat generated in a phase-change memory cell or other resistive memory cell is thermally conducted to a neighboring memory cell during a write operation of the memory cell. In a write operation, a large amount of heat may be present in a selected memory cell, but neighboring memory cells should not show a significant temperature rise. If the temperature rise at the location of the neighboring memory cell caused by the conducted heat is large enough, the state of the neighboring memory cell may be affected, and the data stored therein may be corrupted.

Conventional phase-change memories operating at room temperature are typically unaffected by thermal noise. For example, for a conventional phase-change memory using Ge ₂ Sb ₂ Te ₅ for resistive elements, the temperature increase of neighboring phase-change memory cells during a reset operation is typically up to about 50 ° C. to be. Therefore, this phase-change memory operating at room temperature typically has a maximum temperature of 110 ° C. or less, which is the maximum temperature of an amorphous bit that is resistant to crystallization for over 10 years. Therefore, this maximum temperature limits the phase-change memory data retention to 10 years. However, if the phase-change memory is operating at elevated temperatures, such as 70 ° C., intrinsic heat spreading will cause neighboring phase-change memory cell temperatures to remain below 110 ° C. specified during 10 years of data retention. It is no longer sufficient to ensure that it is.

One embodiment of the present invention provides a memory. The memory comprises an array of memory cells, each memory cell comprising a resistive material; A first insulating material transversely surrounding the resistive material of each memory cell; And a heat spreader between the memory cells to thermally isolate each memory cell.

1 is a diagram illustrating one embodiment of an array of phase-change memory cells 100. The memory array 100 includes thermal insulation material between the memory cells to prevent thermal noise from affecting data retention of the memory cells. The memory array 100 includes a plurality of phase-change memory cells 104a to 104d (collectively referred to as phase-change memory cells 104), a plurality of bit lines (BL) 112a and 112b (collectively). Bit lines 112), a plurality of word lines WLs 110a and 110b, and a plurality of ground lines GL 114a and 114b (collectively referred to as ground lines 114). ).

Each phase-change memory cell 104 is electrically coupled to a word line 110, a bit line 112, and a ground line 114. For example, phase-change memory cell 104a is electrically coupled to bit line 112a, word line 110a, and ground line 114a, and phase-change memory cell 104b is bit line 112a. ) Is electrically coupled to the word line 110b and the ground line 114b. Phase-change memory cell 104c is electrically coupled to bit line 112b, word line 110a and ground line 114a, and phase-change memory cell 104d is connected to bit line 112b, word line. Electrically coupled to 110b and ground line 114b.

Each phase-change memory cell 104 includes a phase-change element 106 and a transistor 108. Transistor 108 is a field effect transistor (FET) in the illustrated embodiment, and in other embodiments transistor 108 may be other suitable devices, such as bipolar transistors or 3D transistor structures. Phase-change memory cell 104a includes phase-change element 106a and transistor 108a. One side of the phase-change element 106a is electrically coupled to the bit line 112a, and the other side of the phase-change element 106a is electrically coupled to one side of the source-drain path of the transistor 108a. do. The other side of the source-drain path of transistor 108a is electrically coupled to ground line 114a. The gate of transistor 108a is electrically coupled to word line 110a. Phase-change memory cell 104b includes phase-change element 106b and transistor 108b. One side of the phase-change element 106b is electrically coupled to the bit line 112a and the other side of the phase-change element 106b is electrically coupled to one side of the source-drain path of the transistor 108b. . The other side of the source-drain path of transistor 108b is electrically coupled to ground line 114b. The gate of transistor 108b is electrically coupled to word line 110b.

Phase-change memory cell 104c includes phase-change element 106c and transistor 108c. One side of the phase-change element 106c is electrically coupled to the bit line 112b and the other side of the phase-change element 106c is electrically coupled to one side of the source-drain path of the transistor 108c. . The other side of the source-drain path of transistor 108c is electrically coupled to ground line 114a. The gate of transistor 108c is electrically coupled to word line 110a. Phase-change memory cell 104d includes phase-change element 106d and transistor 108d. One side of the phase-change element 106d is electrically coupled to the bit line 112b, and the other side of the phase-change element 106d is electrically coupled to one side of the source-drain path of the transistor 108d. . The other side of the source-drain path of transistor 108d is electrically coupled to ground line 114b. The gate of transistor 108d is electrically coupled to word line 110b.

In yet another embodiment, each phase-change element 106 is electrically coupled to ground line 114, and each transistor 108 is electrically coupled to bit line 112. For example, in the case of phase-change memory cell 104a, one side of phase-change element 106a is electrically coupled to ground line 114a. The other side of phase-change element 106a is electrically coupled to one side of the source-drain path of transistor 108a. The other side of the source-drain path of transistor 108a is electrically coupled to bit line 112a. In general, ground lines 114 have a lower potential than bit lines 112.

Each phase-change element 106 comprises a phase-change material that may be composed of various materials in accordance with the present invention. In general, chalcogenide alloys containing one or more elements from Group VI of the periodic table are useful as such materials. In one embodiment, the phase-change material of phase-change element 106 is composed of chalcogenide compound material such as GeSbTe, SbTe, GeTe or AgInSbTe. In another embodiment, the phase-change material may be chalcogen free, such as GeSb, GaSb, InSb or GeGaInSb. In other embodiments, the phase-change material may be composed of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S.

The memory array 100 includes insulating material between adjacent phase-change memory cells 104. In one embodiment each phase-change memory element 106 is surrounded by a material that provides thermal insulation, and the spaces between the memory cells are at least partially filled with a material that provides thermal conduction. The material providing thermal conduction loses any heat that leaks through the material providing thermal insulation around each phase-change element 106. The combination of easy heat spreading and insulation lowers the temperature of adjacent phase-change memory cells 104 during set and especially reset operations. Thus, thermal noise is reduced and data retention is improved.

In another embodiment a material with high thermal conductivity is located between adjacent phase-change memory cells 104. Between adjacent phase-change elements 106 is an additional metallic or semiconductor heat shield or heat spreader. As the heat spreader dissipates heat quickly over the length of several memory cells, it effectively functions to cool the phase-change elements 106 and shield adjacent phase-change elements 106 from heat. In one embodiment the heat spreader is formed as a 2D network between the phase-change elements 106. In another embodiment, the heat spreaders are formed in parallel between the phase-change elements 106 in the direction in which adjacent phase-change elements are nearest to each other in the memory array 100.

In another embodiment, a metal line is routed between adjacent phase-change elements 106. The metal line may be an active metal line in the memory array 100, such as ground line 114 or bit line 112. This embodiment illustrates that the phase-change element 106 and the bottom electrode of the phase-change memory cell 104 are underlying at a predetermined angle, such as 90 ° or other suitable angle, using line lithography. An additional advantage is that it can be formed up to metal lines and even selective etching of the underlying metal lines. Line lithography for a given lithography node has better resolution and linewidth control than a contact hole pattern, thus improving the stability of the geometric dimensions of the phase-change memory cell 104 and thus This improves the switching characteristics of the phase-change memory cell 104.

In the set-up operation of the phase-change memory cell 104a, the set current or voltage pulse is selectively enabled and sent to the phase-change element 106a via the bit line 112a, thereby bringing the transistor 108a into effect. The phase-change element 106a is heated above its crystallization temperature (but typically below the melting temperature) with the selected word line 110a for activation. In this way, the phase-change element 106a reaches its crystalline state in this setting operation. In the reset operation of the phase-change memory cell 104a, a reset current or voltage pulse is selectively enabled on the bit line 112a and sent to the phase-change material element 106a. The reset current or voltage rapidly heats the phase-change element 106a above its melting temperature. After the current or voltage pulse is turned off, the phase-change element 106a is quickly quenched cool to become amorphous. Phase-change memory cells 104b-104d and other phase change memory cells 104 in memory array 100 are set up and reset similarly to phase-change memory cell 104a using similar current or voltage pulses. .

2 is a diagram illustrating one embodiment of an array of phase-change memory cells 100a that includes an insulating material. The memory array 100a includes bit lines 112, word lines 110, phase-change memory cells 104, a first insulating material 120, and a second insulating material 122. Each phase-change memory cell 104 or each memory element 106 in each phase-change memory cell 104 is a first insulating material having low thermal conductivity, such as SiO ₂ , low-k material, porous Surrounded by SiO ₂ , aerogels, xerogels or other suitable insulating materials with low thermal conductivity. The second insulating material 122 is between the memory cells 104 and is in contact with the first insulating material 120. The second insulating material 122 includes a dielectric material having a higher thermal conductivity than the first insulating material 120. The second insulating material 122 includes SiN, SiON, AlN, TiO ₂ , Al ₂ O _3, or other suitable dielectric material having a higher thermal conductivity than the first insulating material 120.

The low thermal conductivity of the first insulating material 120 insulates the memory cells 104. The high thermal conductivity of the second insulating material 122 quickly dissipates any heat that leaks through the first insulating material 120 around the memory cells 104. The combination of thermal insulation due to the first insulating material 120 and thermal diffusion due to the second insulating material 122 lowers the temperature of the adjacent phase-change memory cells 104 during the set up and in particular the reset operation. Thus, thermal noise is reduced and data retention is improved.

FIG. 3 is a diagram illustrating still other embodiments of an array of phase-change memory cells 100b comprising an insulating material. Memory array 100b includes bit lines 112, word lines 110, phase-change memory cells 104, first heat spreader or shield lines 130, and an optional second heat spreader or shield. Lines 132. In one embodiment, the first heat spreader or shield lines 130 lie in parallel across the rows of the memory array 100b and the second heat spreader or shield lines 132 (only one is shown). ) Lie in parallel across the columns of memory array 100b. In yet another embodiment, the second heat spreader or shield lines 132 are excluded. In one embodiment, the first heat spreader or shield lines 130 are in a direction in which adjacent phase-change elements are closest to each other in the memory array 100b. In another embodiment, the first heat spreader or shield lines 130 and / or the optional second heat spreader or shield lines 132 are active like bit lines 112 or ground lines 114. Metal lines.

The first heat spreader or shield lines 130 and optional second heat spreader or shield lines 132 may be a material having a high thermal conductivity, such as SiN, metal, poly-Si, or other suitable having a high thermal conductivity. Contains substances. The space 134 between the first heat spreader or shield lines 130, and the second heat spreader or shield lines 132, and the memory cells 104 may be an interlayer dielectric, such as SiO ₂ , boro. Phosphosilicate glass (BPSG), borosilicate glass (BSG), low-k materials or other suitable dielectric materials. The first heat spreader or shield lines 130 and the optional second heat spreader or shield lines 132 quickly draw any heat from the memory cell 104 over the length of several memory cells 104. Disperse The first heat spreader or shield lines 130 and optional second heat spreader or shield lines 132 cool the phase-change elements 106 and remove adjacent phase-change elements 106 from the heat. Function effectively to shield. Thus, thermal noise is reduced and data retention is improved.

4A illustrates a stage of one embodiment of a phase-change memory element 200a that includes an insulating material. In one embodiment, the phase-change memory element 200a is a pillar phase-change memory element. Phase-change memory element 200a is adapted for use with phase-change memory cell 104 in memory array 100a (FIG. 2). The phase-change memory element 200a includes a first electrode 202, a phase-change material 204, a second electrode 206, a first insulating material 120, and a second insulating material 122. The first insulating material 120 has a lower thermal conductivity than the second insulating material 122. Phase-change material 204 provides a storage location for storing one, two, or several bits of data.

The phase-change material 204 is in contact with the first electrode 202 and the second electrode 206. The phase-change material 204 is completely surrounded in the transverse direction by the first insulating material 120 which defines the current path and thus the location of the phase-change area within the phase-change material 204. In this embodiment, the phase-change material 204 is cylindrical. The first insulating material 120 is in contact with the sides 212 of the second electrode 206. The second insulating material 122 surrounds the first insulating material 120. In yet another embodiment, the first insulating material 120 is in contact with two sides of the first electrode 202 and the second electrode 206.

The low thermal conductivity of the first insulating material 120 insulates the phase-change material 204. The high thermal conductivity of the second insulating material 122 quickly dissipates any heat that leaks through the first insulating material 120. The combination of thermal insulation due to the first insulating material 120 and thermal diffusion due to the second insulating material 122 further increases the temperature of the adjacent phase-change memory cells during the set-up and reset operation of the phase-change memory element 200a. Lower it.

4B illustrates a cross-sectional view of another embodiment of a phase-change memory element 200b. In one embodiment, phase-change memory element 200b is a filler phase-change memory element. Phase-change memory element 200b is adapted for use with phase-change memory cell 104 in memory array 100a (FIG. 2). Phase-change memory element 200b includes a first electrode 202, a phase-change material 204, a second electrode 206, a first insulating material 120, and a second insulating material 122. . The first insulating material 120 has a lower thermal conductivity than the second insulating material 122. Phase-change material 204 provides a storage location for storing one, two, or several bits of data.

The phase-change material 204 is in contact with the first electrode 202 and the second electrode 206. The phase-change material 204 is completely surrounded in the transverse direction by the first insulating material 120 which defines the current path and thus the location of the phase-change area within the phase-change material 204. In this embodiment the phase-change material 204 is hourglass shaped. The first insulating material 120 is in contact with the sides 212 of the second electrode 206. The second insulating material 122 surrounds the first insulating material 120.

The low thermal conductivity of the first insulating material 120 insulates the phase-change material 204. The high thermal conductivity of the second insulating material 122 quickly dissipates any heat that leaks through the first insulating material 120. The combination of thermal insulation due to the first insulating material 120 and thermal diffusion due to the second insulating material 122 further increases the temperature of the adjacent phase-change memory cells during the set-up and reset operation of the phase-change memory element 200b. Lower it.

4C illustrates a cross-sectional view of another embodiment of a phase-change memory element 200c. In one embodiment, phase-change memory element 200c is a filler phase-change memory cell. Phase-change memory element 200c is adapted for use with phase-change memory cell 104 in memory array 100a (FIG. 2). Phase-change memory element 200c includes a first electrode 202, a phase-change material 204, a second electrode 206, a first insulating material 120, and a second insulating material 122. . The first insulating material 120 has a lower thermal conductivity than the second insulating material 122. Phase-change material 204 provides a storage location for storing one, two, or several bits of data.

The phase-change material 204 is in contact with the first electrode 202 and the second electrode 206. The phase-change material 204 is completely surrounded in the transverse direction by the first insulating material 120 which defines the current path and thus the location of the phase-change area within the phase-change material 204. In this embodiment the phase-change material 204 is hourglass shaped. The second insulating material 122 is in contact with the sides 212 of the second electrode 206 and surrounds the first insulating material 120.

The low thermal conductivity of the first insulating material 120 insulates the phase-change material 204. The high thermal conductivity of the second insulating material 122 quickly dissipates any heat that leaks through the first insulating material 120. The combination of thermal insulation due to the first insulating material 120 and thermal diffusion due to the second insulating material 122 may result in the setting of the phase-change memory element 200c and in particular of the adjacent phase-change memory cells 104 during the reset operation. Lower the temperature.

5A illustrates a cross-sectional view of another embodiment of phase-change memory element 220a. In one embodiment phase-change memory element 220a is tapered through phase-change memory element. Phase-change memory element 220a is adapted for use with phase-change memory cell 104 in memory array 100a (FIG. 2). Phase-change memory element 220a includes a first electrode 202, a phase-change material 204, a second electrode 206, a first insulating material 120, and a second insulating material 122. . The first insulating material 120 has a lower thermal conductivity than the second insulating material 122. Phase-change material 204 provides a storage location for storing one, two or several bits of data.

Phase-change material 204 is first portion 222 in contact with first electrode 202 in 226 and second portion 224 in contact with second electrode 206 in 228. ). The phase-change material 204 is filled in a via opening with tapered sidewalls to provide a first portion 222. The phase-change material 204 is filled on the first portion 222 to provide a second portion 224. The first portion 222 of the phase-change material 204 has a tapered sidewall, has a maximum width or cross section at 230, and a minimum width or cross section at 226. The maximum width in reference numeral 230 of the first portion 222 may be less than the width or cross section of the second portion 224. The first portion 222 of the phase-change material 204 is completely transversely by the first insulating material 120 which defines the current path and thus the location of the phase-change area within the phase-change material 204. surrounded. The second insulating material 122 surrounds the first insulating material 120 and the second portion 224 of the phase-change material 204.

The low thermal conductivity of the first insulating material 120 insulates the first portion 222 of the phase-change material 204. The high thermal conductivity of the second insulating material 122 quickly dissipates any heat that leaks through the first insulating material 120. The combination of thermal insulation due to the first insulating material 120 and thermal diffusion due to the second insulating material 122 determines the temperature of the adjacent phase-change memory cells during the set-up and reset operation of the phase-change memory element 220a. Lower.

5B illustrates a cross-sectional view of another embodiment of phase-change memory element 220b. In one embodiment phase-change memory element 220b is tapered through phase-change memory element. Phase-change memory element 220b is adapted for use with phase-change memory cell 104 in memory array 100a (Figure 2). The phase-change memory element 220b includes a first electrode 202, a phase-change material 204, a second electrode 206, a first insulating material 120, and a second insulating material 122. . The first insulating material 120 has a lower thermal conductivity than the second insulating material 122. Phase-change material 204 provides a storage location for storing one, two or several bits of data.

The phase-change material 204 is in contact with the first electrode 202 and the second electrode 206. The phase-change material 204 is completely surrounded in the transverse direction by the first insulating material 120 which defines the current path and thus the position of the phase-change area within the phase-change material 204. In this embodiment the phase-change material 204 has tapered sidewalls. The first insulating material 120 contacts the side surfaces 210 of the first electrode 202 and the side surfaces 212 of the second electrode 206. The second insulating material 122 surrounds the first insulating material 120.

The low thermal conductivity of the first insulating material 120 insulates the phase-change material 204. The high thermal conductivity of the second insulating material 122 quickly dissipates any heat that leaks through the first insulating material 120. The combination of thermal insulation due to the first insulating material 120 and thermal diffusion due to the second insulating material 122 determines the temperature of the adjacent phase-change memory cells during the setup and especially the reset operation of the phase-change memory element 220b. Lower.

 6A illustrates a cross-sectional view of another embodiment of phase-change memory element 250, and FIG. 6B illustrates a cross-sectional side view of phase-change memory element 250. In one embodiment, phase-change memory element 250 is a bridge phase-change memory element. Phase-change memory element 250 is adapted for use with phase-change memory cell 104 in memory array 100a (FIG. 2). The phase-change memory element 250 may include a first electrode 202, a first contact 252, a phase-change material 204, a spacer 256, a second contact 254, a second electrode 206, First insulating material 120, and second insulating material 122. The first insulating material 120 has a lower thermal conductivity than the second insulating material 122. Phase-change material 204 provides a storage location for storing one, two or several bits of data.

The phase-change material 204 is in contact with the first contact 252 and the second contact 254 separated by the spacer 256. The first contact 252 is in contact with the first electrode 202, and the second contact 254 is in contact with the second electrode 206. The phase-change material 204 is surrounded by the first insulating material 120, except where the phase-change material 204 is in contact with the contacts 252, 254 and the spacer 256. The second insulating material 122 surrounds the first insulating material 120.

The low thermal conductivity of the first insulating material 120 insulates the phase-change material 204. The high thermal conductivity of the second insulating material 122 quickly dissipates any heat that leaks through the first insulating material 120. The combination of thermal insulation due to the first insulating material 120 and thermal diffusion due to the second insulating material 122 determines the temperature of the adjacent phase-change memory cells during the set-up and reset operation of the phase-change memory element 250. Lower.

7 illustrates a side view of one embodiment of a layout 300 for phase-change memory cells that includes a heat shield or diffuser. Layout 300 for phase-change memory cells is adapted for use with memory array 100b (FIG. 3). Layout 300 includes substrate 302, bit line 112, ground line 114, transistors 108, contacts 304, contacts 306, phase-change elements 106, and columns. Diffusers or shields 130. Bit line 112 and ground line 114 are in separate metallization layers. In one embodiment bit line 112 includes W or other suitable metal and is in a lower metallization layer than ground line 114 comprising Al, Cu or other suitable metal. In another embodiment, the bit line 112 includes Al, Cu or other suitable metal, and is in a metallization layer higher than the ground line 114 that includes W or other suitable metal.

In one embodiment bit line 112 is perpendicular to ground line 114. One side of the source-drain path of each transistor 108 is electrically coupled to ground line 114 via a contact 306 comprising Cu, W or other suitable conductive material. The other side of the source-drain path of each transistor 108 is electrically coupled to the bit line 112 via a contact 304 and a phase-change element 106 comprising Cu, W or other suitable conductive material. Ring. The gate of each transistor 108 is electrically coupled to a word line 110 comprising doped poly-Si, W, TiN, NiSi, CoSi, TiSi, WSi _x or other suitable material. In one embodiment memory element 106 is a heater cell, active-in-via cell, pillar cell or other suitable phase-change memory element.

Heat spreader or shield lines 130 are provided between adjacent phase-change elements 106 that are close to each other and are not separated by ground line 114. Heat spreader or shield lines 130 include a material having high thermal conductivity, such as SiN, metal, poly-Si or other suitable material having high thermal conductivity. The space 134 between the heat spreader or shield lines 130 and the phase-change elements 106 may be an interlayer dielectric such as SiO ₂ , Boro-PhosphoSilicate Glass (BPSG), BoroSilicate Glass (BSG), low-k. Filled with material or other suitable dielectric material. The heat spreader or shield line 130 quickly dissipates any heat from the phase-change element 106 over the length of several memory cells. Thus, the heat spreader or shield lines 130 function effectively to cool the phase-change elements 106 and shield adjacent phase-change elements from heat.

FIG. 8 illustrates a side view of another embodiment of a layout 320 for phase-change memory cells that includes using an active metal line as a heat spreader. The layout 320 for phase-change memory cells is adapted for use with the memory array 100b (FIG. 3). Layout 320 includes substrate 302, bit line 112, ground lines 114, transistors 108, contacts 304, contacts 306, and phase-change elements 106. Include. Bit line 112 and ground line 114 are in separate metallization layers. In one embodiment bit line 112 includes W or other suitable metal and is in a lower metallization layer than ground line 114 comprising Al, Cu or other suitable metal. In another embodiment, the bit line 112 includes Al, Cu or other suitable metal, and is in a metallization layer higher than the ground line 114 that includes W or other suitable metal. In any case, the bit line 112 advances perpendicular to the word lines 110.

In one embodiment bit line 112 is perpendicular to ground line 114. One side of the source-drain path of each transistor 108 is electrically coupled to the bit line 112 via a contact 306 comprising Cu, W or other suitable conductive material. The other side of the source-drain path of each transistor 108 is electrically coupled to the ground line 114 via a contact 304 and a phase-change element 106 comprising Cu, W or other suitable conductive material. Ring. The gate of each transistor 108 is electrically coupled to a word line 110 (not shown) comprising doped poly-Si, W, TiN, NiSi, CoSi, TiSi, WSi _x or other suitable material. do. In one embodiment the memory element 106 is a heater cell, active-in-via cell, filler cell or other suitable phase-change memory element.

In one embodiment the bit line 112 is in a metallization layer lower than the ground lines 114. Phase-change elements 106 are coplanar with bit line 112 such that bit line 112 functions as a heat spreader or shield line 130. In one embodiment bit lines 112 include insulating sidewall spacers that form sublithographic openings between bit lines 112. Phase-change material is filled in sublithography openings between the spacers to provide phase-change elements 106. The spacer material includes a dielectric material having low thermal conductivity to insulate the phase-change elements 106. Each bit line 112 provides a heat spreader. Bit line 112 quickly dissipates any columns from adjacent phase-change elements 106 over the length of several memory cells. Thus, the bit line 112 effectively functions to cool the phase-change elements 106 and shield adjacent phase-change elements 106 from heat.

9 illustrates a top view of one embodiment of phase-change memory cells 400 including a dummy ground line 402. The array of phase-change memory cells 400 includes bit lines 112, ground lines 114, dummy ground lines 402, word lines 110, and shallow trench isolation (STI) 404. do. Memory cells are coupled to bit lines 112 through contacts 304. Memory cells are coupled to ground lines 114 via contacts 306. STI 404 or other suitable transistor isolation is provided between the bit lines 112 in parallel with the bit lines 112. The word lines 110 are perpendicular to the bit lines 112 and parallel to the ground lines 114 and the dummy ground lines 402. As shown in memory cell contacts 304, dummy ground lines 402 provide a thermal insulation material between rows of memory cells. In addition, as shown in memory cell contacts 304, ground lines 114 also provide thermal insulation material between adjacent memory cells.

FIG. 10A illustrates a cross-sectional view of one embodiment of a layout 400 for phase-change memory cells that includes a dummy ground line 402, and FIG. 10B illustrates one of the layout 400 through the phase-change element 106. The side view of an Example is illustrated. The layout 400 includes a substrate 302, transistors 108, isolation gates 406, ground lines 114, dummy ground lines 402, a capping layer 410, spacers ( 408, phase-change elements 106, phase-change element contacts 304 each including an electrode, ground line contacts 306, electrodes 416, bit lines 112, and dielectric material 412 and 414.

Transistors 108 that select phase-change elements 106 are formed on the substrate 302. Gates of transistors 108 are electrically coupled to word lines 110. Isolation gates 406 are formed on the substrate 302 between transistors 108. Dielectric material 414 is deposited over transistors 108 and isolation gates 406. Phase-change element contacts 304 electrically couple one side of the source-drain path of each transistor 108 to phase-change element 106, and ground line contacts 306 connect each transistor ( The other side of the source-drain path of 108 is electrically coupled to ground line 114. Spacers 408 surround phase-change elements 106 and optionally phase-change element contacts 304 to provide sublithography width to phase-change elements 106.

Spacers 408 insulate the phase-change elements 106. Dummy ground lines 402 extend between phase-change elements 106 that are not separated by ground line 114. Dummy ground lines 402 and ground lines 114 provide heat spreaders to dissipate heat passing through spacer 408 from phase-change elements 106. In one embodiment, the capping layer 410 of SiN or other suitable material caps the ground lines 114 and the dummy ground lines 402. Optionally, capping material 410 is also formed on the sidewalls of dummy ground lines 402 and ground lines 114. The capping layer 410 functions as a masking layer in the storage node etch, further insulates the phase-change elements 106 and reduces the width of the openings in which the phase-change material is deposited. The electrodes 416 electrically couple the phase-change elements 106 to the bit line 112.

11 is a flow diagram illustrating one embodiment of a method 500 of manufacturing a phase-change memory. Metal lines 114 and 402 with capping layer 410 and optional sidewall spacers at 502 are formed over preprocessed wafer 302. In 504, the gaps between the metal lines are filled with oxide or dielectric material 412. Storage node lithography at 506 is performed as lines perpendicular to the metal lines 114 and 402. In another embodiment, storage node lithography is performed as holes along paths running perpendicular to the metal lines 114 and 402. In another embodiment storage node lithography is performed at an angle less than 90 ° with respect to the metal lines 114 and 402 along the paths.

Storage node contact holes at 508 are etched into the self-aligned oxide or dielectric material 412 relative to the metal lines 114 and 402. Low-k dielectric or oxide spacer 408 in 510 is formed by deposition and etching, and then insulates the phase-change element. In reference numeral 512 electrode material 304 is deposited and planarized in the contact holes. In 514 the electrode material 304 is recess etched to form the opening and the first electrode. In 516, phase-change material 106 is deposited over electrode material 304 to form phase-change element 106. In one embodiment step 510 is moved after step 514 and before step 516. In reference numeral 518 electrode material 416 is deposited over phase-change material 106 to form a second electrode. At 520, upper metallization layers including bit lines 112 are formed.

Embodiments of the present invention provide a phase-change memory array layout that insulates adjacent phase-change memory cells. By insulating adjacent phase-change memory cells, thermal noise is reduced and data retention is improved. Embodiments of the present invention allow for operating temperatures above 80 ° C. for phase-change memories, and provide improved data stability at low temperatures.

According to the present invention, a memory is provided that reduces thermal noise and improves data retention by insulating adjacent phase-change memory cells, and a method of manufacturing the memory.

Claims (26)

In memory, An array of memory cells, each memory cell including a resistive element; A first insulating material surrounding the resistive element of each memory cell; And And a heat spreader between the memory cells to thermally isolate each memory cell. The method of claim 1, And the first insulating material is selected from the group consisting of SiO ₂ , porous SiO ₂ , aerogel, xerogel and low-k dielectrics. The method of claim 1, And the heat spreader comprises a second insulating material selected from the group consisting of SiN, SiON, AlN, TiO ₂ and Al ₂ O ₃ . The method of claim 1, The heat spreader comprises a second insulating material in contact with the first insulating material, And the first insulating material has a lower thermal conductivity than the second insulating material. The method of claim 1, And the resistive element comprises a phase-change material element. The method of claim 1, And the heat spreader comprises one of an electrically insulating material and an electrically conductive material. The method of claim 1, And the resistive element is configured to increase in temperature in response to a write operation. The method of claim 1, And the resistive element comprises a magnetic memory element. In memory, An array of resistive memory cells; An insulating material having a first thermal conductivity around the memory cells; And And lines of material having a second thermal conductivity higher than the first thermal conductivity between the lines of memory cells to insulate the memory cells. The method of claim 9, Wherein said lines are selected from the group consisting of SiN, metal and poly-Si. The method of claim 9, And said lines comprise electrical lines. The method of claim 9, And the insulating material is selected from the group consisting of SiO ₂ , BPSG, BSG, and low-k dielectrics. The method of claim 9, And the memory cell comprises phase-change memory cells. In a semiconductor memory device, An array of resistive memory cells; And And means for dissipating heat from each memory cell during a write operation to prevent heating of adjacent memory cells. The method of claim 14, And the memory cells comprise at least one of Ge, Sb, Te, Ga, As, In, Se, and S. In the method of manufacturing a memory, Providing an array of resistive memory cells, each resistive memory cell comprising a resistive element; Surrounding each resistive element with a first insulating material having a first thermal conductivity; And Filling between the resistive elements with a second insulating material having a second thermal conductivity greater than the first thermal conductivity. The method of claim 16, Providing the array of resistive memory cells comprises providing an array of phase-change memory cells. The method of claim 16, Surrounding each resistive element with the first insulation material comprises surrounding each resistive element with a first insulation material selected from the group consisting of SiO ₂ , porous SiO ₂ , airgel, xerogel and low-k dielectrics. Memory manufacturing method comprising a. The method of claim 16, Filling between the resistive elements with the second insulating material comprises filling between the resistive elements with a second insulating material selected from the group consisting of SiN, SiON, AlN, TiO ₂ and Al ₂ O ₃ . A memory manufacturing method characterized by the above-mentioned. In the method of manufacturing a memory, Providing an array of resistive memory cells, each resistive memory cell comprising a resistive element; And Providing heat spreader or shielding lines between rows of the memory cells to insulate the memory cells. The method of claim 20, Providing the heat spreader or shielding lines comprises providing a metal line coplanar with the resistive elements. The method of claim 20, Providing the heat spreader or shield lines comprises providing one of a bit line and a ground line coplanar with the resistive elements. The method of claim 20, Providing the array of resistive memory cells comprises providing an array of phase-change memory cells. In the method of manufacturing a memory, Forming metal lines having a capping layer on the preprocessed wafer; Filling gaps between the metal lines with a first insulating material; Performing storage node lithography along paths at an angle to the metal lines; Etching storage node contact holes into the first insulating material self-aligned to the metal lines; Forming recessed first electrodes in the contact holes; Forming a second insulating material on the walls of the contact holes before or after forming the first electrode; Depositing a resistive material over the first electrodes to provide resistive material elements; And Forming a second electrode over the resistive material. The method of claim 24, Forming the metal lines comprises forming ground lines and dummy ground lines. The method of claim 24, Forming the metal lines comprises forming the metal lines to insulate adjacent resistive material elements.

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