KR100655779B1 - Precharging circuit for driving amoled displays - Google Patents

Abstract

A precharge circuit for driving an AMOLED(Active Matrix Organic Light Emitting Diode) is provided to reduce the layout area of a data driving chip and power consumption by not using an operation amplifier. A precharge circuit for driving an AMOLED includes a first precharge voltage generation transistor(M1) for generating precharge voltage of a data line according to the input of predetermined current; a second charging transistor(M2) and a discharging current source(IBIAS) for making capacitive load(Cp) of the data line; and first and second switching transistors(SW1,SW2) for controlling the operation of the first and second transistors, where the first and second transistors are N-type transistors. The precharge circuit receives turn-on voltage between gate and source stages of the first transistor through a source stage of the second transistor by connecting the source stage of the second transistor to the gate stage of the first transistor.

Description

PRECHARGING CIRCUIT FOR DRIVING AMOLED DISPLAYS}

1 is a configuration diagram of a conventional AMOLED display device.

2 is a pixel circuit diagram of FIG.

3 is a configuration diagram of a data driving circuit of FIG. 1.

4 is a configuration diagram of the D / A conversion circuit of FIG.

5 is a configuration diagram of a D / A conversion circuit and a gradation voltage generation circuit of a conventional AMOLED display device.

FIG. 6 is an operational model diagram of a precharge and pixel circuit associated with FIG. 5; FIG.

FIG. 7 is a circuit diagram of a voltage driver in the D / A conversion circuit of FIG. 5; FIG.

8 is a configuration diagram of a precharge circuit for driving an AMOLED according to the present invention.

9 is an operation timing diagram of the present invention.

Fig. 10 is a circuit diagram to which the present invention is applied to a pixel circuit.

11 is a voltage waveform diagram of a timing-specific data line in the present invention.

12 is an application example of the present invention.

13 is a complementary circuit block diagram of the present invention.

<Description of the symbols for the main parts of the drawings>

210: current DAC 220: pixel circuit

M1, M2: Transistor SW1-SW4: Switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display driving apparatus, and more particularly, to a precharge circuit for driving an AMOLED used to increase the data driving speed in a low current region when an active matrix organic light emitting display device (AMOLED) is driven in a current mode. .

Techniques for forming thin film transistors (TFTs) on substrates have been extensively advanced in recent years, and their application to active matrix display devices is progressing.

In particular, a TFT using a polysilicon film has a higher field effect mobility than a TFT using a conventional amorphous silicon film, thereby enabling high speed operation. As a result, it has become possible to execute pixel control by a drive circuit formed on the same substrate as the pixel in the conventional pixel control executed by the drive circuit outside the substrate.

This type of active matrix display device is focused on many advantages, such as the reduced manufacturing costs that can be achieved by integrating various circuits and devices on the same substrate, miniaturization of the display device, increased throughput, and higher throughput. come.

At present, active matrix EL display devices equipped with EL (Electro Luminescence) elements as self-light emitting elements have been actively studied. The EL display device is also called an organic EL display (OELD) or an organic light emitting display device (OLED), and the active matrix organic light emitting display device is called an AMOLED.

Unlike liquid crystal display devices, organic display devices are self emissive. The EL element is configured such that the EL layer is sandwiched between a pair of electrodes, and the organic light emitting layer formed between the first electrode (cathode), which is an electron injection electrode, and the second electrode (anode), which is an hole injection electrode, is formed. When electrons and holes are injected into the electrons, the excitons generated by pairing electrons and holes fall from the excited state to the ground state and are extinguished and emit light.

These OLEDs operate with DC bias of 2 to 30 volts. The brightness of the OLED can be controlled by adjusting the voltage or current applied to the anode and cathode. The relative amount of light generated is called gray level.

OLEDs generally operate optimally when operating in current mode.

The light output is more stable in constant current driving than in constant voltage driving. This is in contrast to many other display technologies that typically operate in voltage mode. Therefore, active matrix displays using OLED technology require a specific pixel structure to provide a current mode of operation.

Generally in matrix addressable OLED (AMOLED) devices, multiple OLEDs are formed on a single substrate and arranged in regular grid pattern groups. Several OLED groups forming a column of the grid may share a common cathode or cathode line. Several OLED groups forming the rows of the grid may share a common anode or anode line. Certain groups of individual OLEDs emit light when their cathode lines and anode lines are activated at the same time. OLED groups within the matrix can form one pixel in the display, with each OLED generally serving as one sub-pixel or pixel cell.

OLEDs have excellent features such as wide viewing angle, high speed response and high contrast, so they can be used as pixels in graphic displays, television image displays or surface light sources, and can be used like plastics. The device can be formed on a flexible transparent substrate, can be made very thin and light, and has good color, making it suitable for flat panel displays (FPDs).

In addition, it can display three colors of R (Red), GGreen) and B (Blue), and it requires less backlight than the well-known liquid crystal display (LCD), which consumes less power. It is also attracting much attention as the next generation full color display device because of its excellent color.

"Display device and display device" of Korean Patent Application No. 2005-8376 filed in Korea filed with priority claim to JP-2004-00022974 and JP-P-2004-00282758 with respect to the conventional display device using the display device as described above. Looking at the contents of the "drive circuit for" and the prior art cited in this patent are as follows.

The display device 100 shown in FIG. 1 is driven based on a sequential line driving and scanning method. The scanning line driver circuit 102 drives the plurality of scanning lines 121 in a predetermined order in response to the scanning synchronization signal.

The data line driver circuit 101 drives the plurality of data lines 111 in association with the scanning line 121 selectively driven by the scanning line driver circuit 102 so that the pixel 105 can display display data. To help.

The data line driving circuit 101 divides each data line 111 by dividing the period for displaying the display data into two periods, a first period called a precharge period and a second period called a current drive period. Drive it.

2 illustrates a circuit diagram of the pixel 105 of the display device 100 of FIG. 1.

As shown in Fig. 2, the pixel 105 includes an electroluminescent element 130, a driving TFT 131, a switch 132, and a capacitor 135, which is a capacitive element, which emits light according to an EL (electroluminescence) phenomenon. ) Is included.

FIG. 3 shows a circuit configuration of the data line driver circuit 101 of FIG.

As shown in FIG. 3, the data line driver circuit 101 includes a shift register circuit 112, a data register circuit 113, a data latch circuit 114, a D / A conversion circuit 115, and an input buffer circuit ( 116, a timing control circuit 117, and a reference current source 118.

The data register circuit 113 is a memory circuit that stores display data, and the data register circuit 113 stores display data in synchronization with a signal output from the shift register circuit 112.

The data latch circuit 114 reads display data stored in the data register circuit 113 in synchronization with the latch signal from the timing control circuit 117 and then outputs the read data to the D / A conversion circuit 115. do. The D / A conversion circuit 115 generates a current to be output onto the data line 111 based on the data from the data latch circuit 114.

4 shows a detailed circuit configuration of the D / A conversion circuit 115.

As shown in FIG. 4, the D / A conversion circuit 115 includes a conversion circuit 151 and a precharge circuit 152 for each data line 111. The conversion circuit 151 performs the D / A conversion of the plurality of reference currents weighted in a binary manner using the display data to generate a gradation current for the display data.

The precharge circuit 152 includes a quadrature-addition circuit 153, a voltage driver 154, and switches 155, 156, and 157, and has the same impedance characteristic as the input impedance characteristic of the pixel 105 shown in FIG. 2. The quasi-addition circuit 153 and the voltage driver 154 generate a gradation voltage that is adaptable to the input impedance characteristic of the pixel 105 based on the gradation current from the conversion circuit 151.

Further, the precharge circuit 152 outputs a gray voltage and a gray current, and switches the data lines through switching of the switches 155, 156, and 157 in the order of the precharge period and the current driving period in one horizontal driving period. Voltage drive and current drive of 111 are performed.

In the data line driving circuit 101, the data line driving period for driving the data line 111 is divided into two periods, a precharge period and a current driving period.

In the precharge period, the data line driving circuit 101 drives the data line 111 by the voltage driving circuit with high driving capability, and this driving is referred to as voltage driving. In the current driving period, the data line driving circuit 101 drives the data line 111 at a current having a constant current value by the constant current source circuit, and this driving is referred to as current driving.

The data line driver circuit 101 outputs a gray voltage in the precharge period to drive the data line 111 during voltage driving. The capacitor 135 for each pixel 105 is charged to a predetermined voltage in a short period of time using its output gray voltage. In addition, the pixel 105 can be driven with high precision by the gradation current output from the data line driving circuit 101 in the current driving period, thereby achieving display with high precision.

FIG. 5 illustrates a conventional D / A conversion circuit and a gradation voltage generation circuit used in a display device using AMOLED, and FIG. 6 illustrates an operation model diagram of a precharge and pixel circuit associated with FIG. 5.

In FIG. 5, the gradation voltage generation circuit 15 generates a plurality of second gradation voltages based on the gradation setting data and the first gradation voltage generation circuit 21 which generates a plurality of first gradation voltages based on the gradation setting data. And a second gray voltage generator 22 and a multiplexer 23 to generate. The multiplexer 23 outputs one of a plurality of first gray voltages and a plurality of second gray voltages in parallel to the D / A conversion circuit 14 as a plurality of gray voltages.

The D / A conversion circuit 14 includes a decoder 24, a gray voltage selection circuit 25, a voltage driver 26, a first switch 27, a current driver 28, and a second switch 29. .

The decoder 24 decodes display data for one pixel supplied from the data latch circuit and outputs the decoded data to the gray voltage selection circuit 25. The gray voltage selection circuit 25 selects a specific gray voltage from a plurality of gray voltages supplied from the gray voltage generation circuit 15 based on the display data supplied from the decoder 24. The gray voltage selection circuit 25 outputs this selection data to the voltage driver 26 or the current driver 28.

The voltage driver 26 can drive a corresponding one of the data lines 6 with high driving capability. For example, voltage driver 26 is provided with a voltage follower circuit or a source follower circuit. The voltage driver 26 drives the data line 6 to a voltage corresponding to the voltage supplied from the gradation voltage selection circuit 25. The current driver 28 can drive the data line 6 with a constant current.

Therefore, the data line 6 and the pixel 5 are voltage driven at a high speed in the precharge period by the voltage driver 26, and the data line 6 and the pixel 5 are driven by the current driver 28 in the current driving period. Current is driven by a predetermined current at. In voltage driving, both the value and direction of the current flow can be changed. On the other hand, in current driving, the current value is constant and the direction of the current flow does not change.

The current driver 28 shown in FIG. 6 is composed of a P-channel transistor, which generates a current Id and then, based on the selected second gradation voltage supplied from the gradation voltage selection circuit 25, the data line. It supplies to (6). The current driver 28 is composed of a single transistor made of a P-channel transistor because the first TFT 34 of the pixel 5 is an N-channel transistor. In the case where the first TFT 34 of the pixel 5 is composed of P channel transistors, it is preferable that the current driver 28 is composed of N channel transistors.

7 shows a detailed circuit configuration of the voltage driver 26 in the D / A conversion circuit 14. As shown in FIG.

7, the output stage of the voltage driver 26 is of a push-pull type, and since the first TFT 34 of the pixel 5 is an N channel transistor, the differential input transistors are P channel transistors. When the differential input transistors are N channel transistors, the voltage range is narrowed by the threshold voltage Vth. Therefore, by using the same P channel transistors as the differential input transistors, the voltage range can be widened near the ground potential.

However, as shown in FIG. 7, a voltage driver using an operational amplifier is typically composed of a compensating resistor and a capacitor for overcoming an excessive capacitance load of a plurality of transistors and data lines, and the aforementioned Korean Patent Application No. 2005-8376. Arcs do not escape this category.

A voltage driver of the type shown in FIG. 7 must be formed for each data channel. Since the voltage driver is composed of a plurality of transistors and compensation capacitors, it must occupy a considerable area in the data driving chip, and excessive current consumption is inevitable.

In addition, when attempting to design a voltage driver directly to a panel by using a system on glass (SOG) circuit design, and to reduce the production cost of the drive system, it is very likely that the voltage driver circuit complexity does not achieve sufficient voltage driver performance.

That is, when driving a flat panel display device using a flat panel display element such as a conventional AMOLED in current mode, the data current transfer speed to the intended pixel circuit is greatly increased due to parasitic capacitance generated in the data line of the flat panel display device. As the driving current is lowered as the level of the driving current decreases, the driving speed is increased by using the data line precharge circuit.

However, conventional precharge circuits are typically implemented in the form of a voltage follower using an operational amplifier, and such precharge circuits have problems such as using excessive transistors, chip area, and current consumption compared to their functions.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to provide a simple configuration and low operating current without using an operational amplifier when implementing data line precharge of a flat panel display using AMOLED. The present invention provides a precharge circuit for driving an AMOLED.

According to an aspect of the present invention, there is provided a precharge circuit for driving an AMOLED, including: a first transistor for generating a precharge voltage of a data line according to a predetermined current input; A charging second transistor and a discharge current source for charging / discharging the capacitive load of the data line to an intended voltage; And first and second switching transistors for controlling the operations of the first and second transistors.

Each of the first and second transistors is an N-type transistor, and a source terminal of the second transistor is connected to a gate terminal of the first transistor, so that the gate-to-source turn-on voltage of the first transistor is the source of the second transistor. It is preferred to be configured to be fed through the bottom end.

The apparatus may further include a power dissipation preventing element for reducing an operating current of the first and second transistors for generating the precharge voltage, the charging second transistor, the discharge current source, and the first and second switching transistors when the precharge circuit is inactive. It is preferable.

The present invention for achieving the above object, the current DAC for generating a current corresponding to the input digital data; A first transistor for generating a required data line precharge voltage according to the current generated by the current DAC; A second transistor for charging the capacitive load of the data line to a desired voltage; A current source coupled to the second transistor to provide a discharge passage of the capacitive load of the data line; And first and second switching transistors for controlling the operation of the first and second transistors.

The first and second transistors are N-type transistors, respectively, and the drain terminal of the first transistor is connected to the gate terminal of the second transistor while the current output from the current DAC is input through the first switch transistor. The gate terminal may be connected to the second transistor source terminal to receive a gate-to-source turn-on voltage of the first transistor through the second transistor. The first and second transistors may be P-type, Of course, it can be configured as a complementary type to the N-type transistor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following examples are merely to illustrate the present invention is not limited to the contents of the present invention.

8 shows a precharge circuit for driving an AMOLED according to the present invention, which is a configuration diagram of a basic unit of a unit channel constituting a data driving chip.

As shown, a current DAC 210 that generates a current corresponding to this input digital data from an n-bit digital data input, and a required data line precharge according to the current generated by the current DAC 210. A transistor M1 for generating a voltage, a transistor M2 for charging / discharging a capacitive load C _p , which is a parasitic capacitance of a data line, and a current source I _BIAS , the transistor When switching transistors SW1 and SW2 and scan control signal SCAN are enabled for the operation control of the M1 and M2, the output current of the current DAC 210 is supplied to a data line. It consists of a switching transistor SW3.

In the configuration of FIG. 8, the basic elements constituting the fetch charge circuit of the present invention are the transistors M1 and M2 and the current source I _BIAS .

First, the switch SW1 is an N-type transistor, and a drain terminal is connected to the current DAC 210, and a precharge enable signal PCEN, which is a signal for operating the precharge circuit of the present invention, is connected to the gate terminal. The input terminal is configured to be switched on when the pre-enable enable signal PCEN is input, and the drain terminal of the transistor M1 is connected to the source terminal of the switch SW1.

In addition, the switch SW2 is an N-type transistor. Like the switch SW1, the switch SW2 is configured to be switched on when the precharge enable signal PCEN is input to the gate terminal, and the source terminal of the switch SW2 is configured to be switched on. It is connected to the gate terminal of the transistor M1.

The transistor M1 is an N-type transistor, the source terminal of the switch SW1 is connected to the drain terminal, the source terminal of the switch SW2 is connected to the gate terminal, and the source terminal is connected to ground. When the switches SW1 and SW2 are turned on, the data line precharge voltage is generated according to the current generated by the current DAC 210.

In addition, the transistor M2 is an N-type transistor, and a gate terminal is connected between the source terminal of the switch SW1 and the drain terminal of the transistor M1, and the drain terminal is connected to the voltage source VDD. The terminal is connected to the gate terminal of the transistor M1 and the source terminal of the switch SW2 to charge the capacitive load C _p of the data line Data on the switch SW1 to an intended voltage. do.

The current source I _BIAS is a constant current source, one end of which is connected to the source terminal of the transistor M2, and the other end of which is grounded so that the capacitive load C _p of the data line is switched. A discharge path is formed to discharge to ground through SW2.

The switch SW3 is an N-type transistor, a source terminal of which is connected to the current DAC 210, and a drain terminal of which is connected to a drain terminal and a data line of the switch SW2. The scan control signal SCAN is input so that the output of the current DAC 210 is supplied to the data line when the scan control signal SCAN is enabled.

In addition, the transistor M1 may be fabricated on a semiconductor substrate, or may be a TFT formed on the glass of the panel, and the components M1, M2, SW1-SW3 except the current DAC 210 may be formed in the panel. It may be composed of a TFT on the glass.

The resistor R _p of the data line and the capacitor C _p , which are capacitive loads, are parasitic resistances and parasitic capacitances.

The operation of the present invention configured as described above will be described with reference to FIG. 10 showing an operation timing diagram of the present invention of FIG. 9 and a configuration when the circuit of FIG. 8 is applied to the pixel circuit 220 of an arbitrary panel.

First, referring to the timing diagram of FIG. 9, Period A is a frame time, and typically 1/60 seconds or 1/30 seconds is used. However, this frame time can vary widely depending on the application of the panel.

The frame time is composed of a low time period represented by period B and a light emitting time represented by period C. In addition, a row time period B is divided into a precharge period D and a current programming time period E. The operation in this time domain is the same as in the related art.

When an arbitrary row (or scan line) is selected in the present invention based on the timing as shown in FIG. 9, a current corresponding to the input digital data is generated by the current DAC 210, and a precharge enable signal PCEN is generated. Is enabled.

In the period in which the precharge enable signal PCEN is enabled (precharge period), the switches SW1 and SW2 are turned on, so that the output current of the current DAC 210 passes through the switch SW1 and becomes a transistor. It reaches the drain of M1.

At this time, the gate-to-source voltage of the transistor M1 is input so that the source voltage of the transistor M2 is input to the gate of the transistor M1 so that a voltage necessary for the output current of the current DAC 210 is formed.

The data line becomes the gate voltage of the transistor M1 because the switch SW2 is turned on. The capacitive load C _P , which is a parasitic capacitance of the data line, is the transistor M2. It can be charged by and discharged by the current source (I _BIAS ) to be able to _induce a voltage corresponding to the intended current to the large capacitive load (C _P ) in a short time.

After that, when the precharge enable signal PCEN is disabled and the scan control signal SCAN is enabled, the output current of the current DAC 210 is supplied to the data line of the panel through the switch SW3. Will be.

At the end of the precharge period (period D), the current programming period (period E) starts. In this period, the current output from the current DAC 210 and the drain current of the driving transistor MD of the pixel circuit 220 It should be possible to be identical within a short time, and for this purpose, the driving transistor MD of the pixel circuit 220 should be similar to the I _DS -V _GS characteristic of the transistor M1. This is because the voltage induced in the data line by the current output from the current DAC 210 is determined by the I _DS -V _GS characteristic of the transistor M1.

Meanwhile, in order to implement the characteristics of the TFT driving transistor MD formed on the organic substrate with the transistor M1 formed on the semiconductor substrate, the transistor M1 may not be a simple transistor. For example, a source degeneration resistor may be added to the transistor M1, or two transistors may be connected in series to operate one transistor.

In the current programming section, the drain current of the driving transistor MD should converge to the current value of the current DAC 210 in a short time, and the accuracy of the convergence is the current programming section, the data current level, and the data line. It is determined by the degree of matching between the parasitic capacitance C _P and the transistor M1 and the driving transistor MD. This relationship is also applied to the prior art as it is.

FIG. 11 illustrates a voltage waveform diagram of a data line for each timing in the present invention. When the precharge enable signal PCEN is enabled at T ₁ , the data line voltage is at the precharge voltage level at an initial voltage V ₁ . Is charged with V ₂ .

This precharge voltage level is determined by I _DATA which is the output current of the current DAC 210 of FIG. 8 and the device parameters of the transistor M1, and the precharge voltage equation is as follows.

Where W = channel width of transistor M1, L = channel length of transistor M1, COX = unit capacitance / unit area, VT = transistor ( The threshold voltage of M1, μ = mobility of transistor M1.

The precharge rate is determined by the current supply capability of the transistor M2 during charging of the data line and by the current source I _BIAS during discharging.

If the required voltage variation of the data line is 5V, the parasitic capacitance 100pF, and the driving bias current is 100uA, the required precharge time is 5us. Therefore, under such conditions, sufficient precharge speed can be expected.

When the scan control signal SCAN is enabled at T ₂ after the precharge period is completed, some voltage adjustment occurs while driving the driving transistor MD of the pixel circuit 220 with I _DATA . The degree of matching between the current-voltage characteristic of the transistor M1 of the precharge circuit and the current-voltage characteristic of the driving transistor MD of the pixel circuit 220 is determined.

In FIG. 11, V ₁ denotes an initial voltage of a data line, V ₂ denotes a data line voltage formed by a precharge operation, and V ₃ and V ₄ denote a final data line voltage. In addition, it means a voltage formed by current driving according to the characteristics of the driving transistor MD of the pixel circuit 220. That is, after charging to the precharge voltage, the data line voltage should be precisely adjusted with the current DAC 210. The two voltages after the fine adjustment are indicated by V ₃ and V ₄ .

12 is an application example of the present invention, and shows a configuration for reducing the operating current of the present invention.

The switch SW4 is further provided in the precharge circuit of FIG. 8. In the switch SW4, the precharge enable signal PCEN is input to the gate terminal, the source terminal is grounded, and the drain terminal is The P-type transistor is connected to the source terminal of the switch SW1, the drain terminal of the transistor M1, and the gate terminal of the transistor M2 to turn on the precharge enable signal PCEN.

Referring to this operation, when the precharge enable signal PCEN is enabled, the switch SW4 is turned off, and the precharge circuit of FIG. 8 performs normal operation.

On the other hand, when the precharge enable signal PCEN is disabled, the switch SW4 is turned on to prevent unnecessary current from flowing in the precharge circuit of FIG. 8 so as to reduce unnecessary operating current.

FIG. 13 illustrates a configuration of a complementary form of the precharge circuit of the present invention of FIG. 8, and since the operation thereof is the same as that of FIG. 8, detailed description thereof is weak. In addition, in FIG. 13, the switch SW4 may be additionally configured in the same manner as in FIG. 12.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art various modifications of the present invention without departing from the spirit and scope of the invention described in the claims below Or it may be modified.

As described above, the present invention has the following effects.

First, since the present invention can be configured in a very simple form without using an operational amplifier in the precharge circuit as in the related art, the area and power consumption of the data driving chip can be greatly reduced.

Second, the yield of the driving chip can be increased by simplifying the driving circuit.

Third, circuits that can only be implemented with semiconductor chips can be converted into circuits that are simple enough to SOG, which can lead to breakthroughs in current-driven technology.

Fourth, not only a small area AMOLED display panel but also a large area panel having excessive data line capacitance can secure the stability of the voltage driver during the precharge operation.

Claims (10)

A first transistor for generating a precharge voltage for generating a precharge voltage of the data line according to a predetermined current input; A charging second transistor and a discharge current source for charging / discharging the capacitive load of the data line to an intended voltage; And First and second switching transistors for controlling the operation of the first and second transistors; A precharge circuit for driving an AMOLED comprising a. The gate-to-source turn-on voltage of the first transistor of claim 1, wherein the first and second transistors are N-type transistors, respectively, and a source terminal of the second transistor is connected to a gate terminal of the first transistor. Precharge circuit for driving the AMOLED, characterized in that configured to be supplied via the source terminal of the second transistor. The precharge circuit of claim 1, further comprising a power consumption preventing element for reducing an operating current of each element when the precharge circuit is not operated. 4. The precharge circuit of claim 3, wherein the power consumption preventing element is a switching transistor. The precharge circuit of claim 1, wherein the first transistor has a source degeneration resistor inserted therein or two transistors are connected in series. A current DAC for generating a current corresponding to the input digital data; A first transistor for generating a required data line precharge voltage according to the current generated by the current DAC; A second transistor for charging the capacitive load of the data line to a desired voltage; A current source coupled to the second transistor to provide a discharge passage of the capacitive load of the data line; And First and second switching transistors for controlling the operation of the first and second transistors; A precharge circuit for driving an AMOLED comprising a. The second transistor of claim 6, wherein the first and second transistors are N type transistors, respectively, and the drain terminal of the first transistor is configured to input a current output from the current DAC through the first switch transistor. Is connected to a gate terminal of the gate terminal, and the gate terminal is connected to the second transistor source terminal to receive the gate-source turn-on voltage of the first transistor through the second transistor. Circuit. The precharge circuit of claim 7, wherein each of the first and second transistors is a P type and is complementary to the N type transistor. 7. The power dissipation preventing element of claim 6, wherein the first transistor for generating the precharge voltage, the second transistor for charging, the current source for discharging, and the first and second switching transistors reduce the power consumption when the precharge circuit is not operated. A precharge circuit for driving an AMOLED further comprising. The method of claim 6, wherein the first transistor is configured to variously control the precharge voltage with respect to the input current by inserting a source degeneration resistor or by connecting two transistors in series. Precharge circuit for driving AMOLED.

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