KR100625792B1 - Semiconductor memory device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device capable of supporting high-speed operation by reducing precharge time. The present invention provides a memory cell array including a plurality of memory cells connected to a word line and a bit line to store data. block; A bit line sense amplifier array block connected to only one end of the bit line pair and having a plurality of bit line sense amplifier blocks for detecting and amplifying a level difference between the bit line pairs; And a plurality of precharge auxiliary means for performing precharge by the bit line sense amplifier block at both ends of the bit line pair.

Shared, precharged, active area, extended, bitline pairs

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}             

1 is a core block circuit diagram of a semiconductor memory device according to the prior art.

FIG. 2 is a diagram illustrating a process of accessing memory cell data of the semiconductor memory device of FIG. 1; FIG.

FIG. 3 is a diagram illustrating a layout in an area 'A' marked in the semiconductor memo device of FIG. 1. FIG.

4 is a core block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a process of accessing data of the semiconductor memory device of FIG. 4; FIG.

FIG. 6 is a diagram illustrating a layout of the first and third bit line sense amplifier blocks and the auxiliary precharge unit of FIG. 5. FIG.

* Explanation of symbols for the main parts of the drawings

420, 440, 460, 480: precharge auxiliary unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly to a semiconductor memory device capable of reducing precharge time.

As the operation speed of semiconductor memory devices is increased, the demand for speeding up data input / output increases.

Various methods are being developed to speed up data input and output, and one of them is to rapidly develop and precharge data pairs.

In other words, the data input / output speed is determined by the sum of the time for developing the data input / output line pair and the time for precharging the data input / output line pair.

Therefore, reducing the precharge time for the data input / output line pairs improves the data input / output speed.

1 is a core block circuit diagram of a semiconductor memory device according to the prior art.

Referring to FIG. 1, a semiconductor memory device according to the related art includes a memory cell array block 10 including a plurality of unit memory cells 12 and 14 connected to a word line and a bit line to store data, and a memory cell array. And a bit line sense amplifier array block 20 and 30 including a plurality of bit line sense amplifiers for sensing and amplifying the bit line pairs BL and BLb of the block 10.

The bit line sense amplifier array block 20 includes a plurality of bit line sense amplifier blocks 22 and 24 provided in units of bit line pairs, and the bit line sense amplifier block 22 includes bit line and bit line sense. Precharge / equalize to precharge the bitline separator 22a for disconnecting / connecting the amplifier (not shown in the figure) and the bitline pairs BL0 and BLb0 and to keep their voltage levels the same. And a bit line sense amplifier (not shown) for detecting and amplifying the difference in voltage levels of the bit line pairs.

FIG. 2 is a diagram illustrating a process of accessing memory cell data of the semiconductor memory device of FIG. 1.

First, the active command ACT is applied to overdrive the word line WL to VCORE + VTn higher than the power supply voltage VCORE. Memory cell data stored in the active capacitor of the word line WL flows into the positive bit line BL at a minute voltage.

Subsequently, the bit line separator 22a connects the bit line pairs BL and BLb to the bit line sense amplifiers in response to the activation of the upper / lower bit line split signals BISH and BISL. The level difference between the bit line pairs BL and BLb to which cell data is applied is sensed and amplified.

Thereafter, when the precharge command PRE is applied to drive the word line WL to the power supply voltage VSS level, the transistor of the memory cell is inactivated. In addition, the equalization signal bleq is activated by the precharge command PRE, so that the precharge / equalization unit 22b pre-sets the bit line pairs BL and BLb to the precharge voltage level VCORE x 1/2. Take it up.

Finally, the bit line separator 22a breaks the bit line pair and the bit line sense amplifier array block in response to the deactivation of the bit line separation signals BISH and BISL.

For reference, the semiconductor memory device includes a dummy cell to compensate for the failure of the cell. As shown in the drawing, the unit memory cell 12 is a general cell and the unit memory cell 14 is a dummy cell.

In addition, the semiconductor memory device allows two adjacent memory cell array blocks to share a bit line sense amplifier array block, thereby allowing the bit line sense amplifier to have a space twice as large as that of the bit line pair. As such, by implementing the bit line sense amplifier in a larger area, the bit line can be detected and amplified quickly with a large driving force.

The memory cell array block and the bit line sense amplifier array block described above will be described at a layout level.

FIG. 3 is a diagram illustrating a layout in an area 'A' marked in the semiconductor memo device of FIG. 1.

Referring to FIG. 3, a semiconductor memory device may include a unit memory cell 12 located at a word line WL0 and a bit line BL0 in a memory cell array block 10, a unit memory cell 14 located at a dummy word line DWL0 and a dummy bit line. And a bit line separator 22a for connecting the bit line sense amplifier and the bit line pairs BL and BLb in the bit line sense amplifier array block 20.

As shown in the figure, it can be seen that the width b of the bit line sense amplifier block is twice the width a between the bit line pairs.

Meanwhile, in the semiconductor memory device according to the related art, since the bit line sense amplifier block is positioned twice of the bit line pair in order to improve the detection and amplification speed of the bit line sense amplifier, the semiconductor memory device is connected to one end of the bit line pair. It is only driven by the bitline sense amplifier block.

Therefore, the precharge time of the device becomes long. This is because the precharge is performed only at one end of the bit line, so that the distance from the bit line sense amplifier block to the other end of the same bit line pair is relatively long, thereby increasing the parasitic capacitance of the bit line.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device capable of supporting high-speed operation by reducing the precharge time.

According to an aspect of the present invention, there is provided a semiconductor memory device including: a memory cell array block having a plurality of memory cells connected to a word line and a bit line to store data; A bit line sense amplifier array block connected to only one end of the bit line pair and having a plurality of bit line sense amplifier blocks for detecting and amplifying a level difference between the bit line pairs; And a plurality of precharge auxiliary means for precharging by the bit line sense amplifier blocks at both ends of the bit line pair.

According to another aspect of the present invention, a semiconductor memory device may include: a first bit line sense amplifier block connected to one end of a first bit line pair; A second bit line sense amplifier block connected to the other end of the second bit line pair; A third bit line sense amplifier block connected to one end of the third bit line pair; And precharge auxiliary means for connecting the first and third bit line sense amplifier blocks to one end of the second bit line pair in response to an auxiliary precharge signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a core block diagram of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4, a core block according to an embodiment of the present invention includes a memory cell array block 100 having a plurality of memory cells connected to a word line WL and a bit line BL and BLb to store data. And a bit line sense amplifier array block (200, 300) connected to only one end of the bit line pair and having a plurality of bit line sense amplifier blocks for detecting and amplifying the level difference between the bit line pairs. A plurality of precharge auxiliary units 420, 440, 460, and 480 are provided to allow precharges to be performed at both ends of the bit line pairs BL and BLb by the blocks 220, 240, 320, and 340.

Looking back, the semiconductor memory device may include a first bit line sense amplifier block 220 connected to one end of the first bit line pair BL0 and BLb0 and a second connected to the other end of the second bit line pair BL1 and BLb1. The second bit line sense amplifier block 240, the third bit line sense amplifier block 320 connected to one end of the third bit line pair BL2 and BLb2, and the first and third signals in response to the auxiliary precharge signal. A precharge auxiliary unit 420 is provided to connect the bit line sense amplifier blocks 220 and 240 to one end of the second bit line pair BL1 and BLb1.

Looking at the precharge auxiliary unit 420 in detail, the precharge auxiliary unit 420 has a gate terminal connected to the dummy word line DWL0 and is disposed between the first sub bit line BLB0 and the second positive bit line BL1. A gate terminal is connected to the first NMOS transistor NM1 having a drain-source path and the dummy word line DWL0, and the drain-source path is connected between the second positive bit line BL1 and the second sub bit line BLb1. And a third NMOS transistor NM2 having a gate terminal connected to the dummy word line DWL0 and having a drain-source path between the second sub bit line BLb1 and the third positive bit line BL2. An NMOS transistor NM3 is provided.

FIG. 5 is a diagram illustrating a process of accessing data of the semiconductor memory device of FIG. 4.

First, when the active command ACT is applied, the deactivated auxiliary precharge signal is applied to the dummy word line DWL so that the precharge auxiliary unit 420 is deactivated, and thus, the first sub bit line to the third positive bit line BLb0. , BL1, BLb1, BL2 are not connected to each other.

Subsequently, when the precharge command PRE is applied, the activated auxiliary precharge signal is applied through the dummy word line DWL, and thus the precharge auxiliary unit 420 is activated to activate the first sub bit line to the third positive bit. The lines BLb0, BL1, BLb1, BL2 are connected.

Accordingly, when the precharge command is applied, the other end of the second bit line pair BL1 and BLb1 is formed by the second bit line sense amplifier block 320, and the one end of the second bit line pair BL1 and BLb1 is formed by the second bit line sense amplifier block 320. Precharging is performed by the first and third bit line sense amplifier blocks 220 and 240.

For reference, the auxiliary precharge signal is applied through the dummy word line DWL to drive the precharge auxiliary unit 420. The dummy word line DWL is a dummy memory cell for replacing a normal memory cell when the normal memory cell fails. It is for driving.

6 is a diagram illustrating a layout of the first and third bit line sense amplifier blocks 220 and 240 and the auxiliary precharge unit 420 of FIG. 5.

As shown in FIG. 6, the auxiliary precharge unit 420 realizes that the first to third NMMOS transistors NM1, NM2, and NM3 are implemented in the dummy memory cell area, thereby reducing the precharge time without increasing the area. Can be.

In addition, the auxiliary precharge unit 420 extends the active regions of the first and third NMOS transistors NM1 and NM3 to the active regions of the bit line isolation units 220 and 240.

Specifically, the semiconductor memory device may include first to third bit line pairs BL0 / BLb0, BL1 / BLb1, and BL2 / BLb2, and one side of the first and third bit line pairs BL0 / BLb0 and BL2 / BLb2. First and third bit line sense amplifier blocks 220 and 240 connected to the first and third bit line sense amplifier blocks 220 and 240, first and second dummy word lines DWL0 and DWL1 formed in a row direction, and a first sub bit. A first active region and a first dummy word of the first NMOS transistor NM1 formed in parallel between the line BLb0 and the second positive bit line BL1 and extending to the first bit line sense amplifier block 220. A second bit line is sensed in parallel between the second active region of the second NMOS transistor NM2 formed perpendicular to the line DWL0 and between the second sub bit line BLb1 and the third positive bit line BL2. And a third active region of the third NMOS transistor NM3 extended to the amplifier block.

Therefore, the above-described semiconductor memory device according to the present invention senses and amplifies memory cell data through a first bit line sense amplifier block connected to one end of a bit line pair. Precharged by the first bit line sense amplifier block, and the other end of the bit line pair is precharged by the second and third bit line sense amplifier blocks formed adjacent to the other end through the precharge auxiliary unit.

That is, since precharge is performed from both ends of the bit line pair, a fast precharge time can be obtained, and the data input / output time is faster.

In addition, by implementing the above-described precharge auxiliary unit in the dummy memory cell region, it is possible to obtain a fast precharge time without increasing the area.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

 The present invention described above is connected to one end of the bit line pair bit line sense amplifier block for sensing and amplifying the memory cell data, and when precharged to be connected to the adjacent bit line pair through the precharge auxiliary unit, the bit line pair Precharge is performed at both ends of the circuit to reduce the precharge time.

In addition, since the precharge auxiliary part is formed in the dummy memory cell area, the precharge time can be improved without increasing the area.

Claims (9)

A memory cell array block having a plurality of memory cells connected to word lines and bit lines to store data; A bit line sense amplifier array block connected to only one end of the bit line pair and having a plurality of bit line sense amplifier blocks for detecting and amplifying a level difference between the bit line pairs; And A plurality of precharge auxiliary means for precharging by the bit line sense amplifier blocks at both ends of the bit line pair; Semiconductor memory device comprising a. The method of claim 1, The precharge auxiliary means, A semiconductor memory device, characterized in that implemented in the region in which a dummy memory cell for replacing the normal memory cell is formed. A first bit line sense amplifier block coupled to one end of the first bit line pair; A second bit line sense amplifier block connected to the other end of the second bit line pair; A third bit line sense amplifier block connected to one end of the third bit line pair; And Precharge auxiliary means for coupling the first and third bit line sense amplifier blocks to one end of the second bit line pair in response to an auxiliary precharge signal; Semiconductor memory device comprising a. The method of claim 3, And the auxiliary precharge signal is inactivated upon application of an active command and activated upon application of a precharge command. The method of claim 4, wherein The precharge auxiliary means, A semiconductor memory device, characterized in that implemented in the region in which a dummy memory cell for replacing the normal memory cell is formed. The method of claim 5, The precharge auxiliary means, A first NMOS transistor having a gate terminal connected to the dummy word line and having a drain-source path between the first sub bit line and the second positive bit line; A second NMOS transistor having a gate terminal connected to the dummy word line, and having a drain-source path between the second positive bit line and the second sub bit line; A third NMOS transistor having a gate terminal connected to the dummy word line, and having a drain-source path between the second sub bit line and the third positive bit line; A semiconductor memory device comprising: a. The method of claim 6, And the auxiliary precharge signal is applied through the dummy word line. The method of claim 7, wherein And the active regions of the first and third NMOS transistors are extended to the first and third bit line sense amplifier blocks, respectively. First to third bit line pairs formed in a column direction; First and second bit line sense amplifier blocks connected to one end of the first and third bit line pairs to sense and amplify data, respectively; First and second dummy word lines formed in a row direction; A first active region of a first NMOS transistor formed in parallel between the first sub bit line and the second positive bit line and extending to the first bit line sense amplifier block; A second active region of a second NMOS transistor formed perpendicular to the first dummy word line; And A third active region of the third NMOS transistor formed in parallel between the second sub bit line and the third positive bit line and extending to the second bit line sense amplifier block; Semiconductor memory device comprising a.

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