KR100594198B1 - Multichannel RAMBUS system - Google Patents

Abstract

The present invention discloses a multichannel Rambus system using Rambus memory. The rambus system of the present invention includes a clock generator, a semiconductor memory, a memory controller, a data bus, and a clock transmission line. The clock transmission line is composed of a transmission clock transmission line and a reception clock transmission line. The semiconductor memory and the memory controller are connected to a transmission clock transmission line, a reception clock transmission line and a data bus. A plurality of channels connecting the memory controller and the semiconductor memory are formed, and these channels are connected in parallel to the memory controller. In one channel, the tTR of the reception clock and the transmission clock is less than one.

Description

Multichannel Rambus System

1 is a circuit diagram illustrating a conventional single channel Rambus system.

FIG. 2 is a timing diagram showing a phase difference between a reception clock and a transmission clock at point A of FIG.

3 is a timing diagram showing a phase difference between a reception clock and a transmission clock at point B in FIG.

4 is a diagram illustrating a multi-channel Rambus system according to the present invention.

5 is a timing diagram showing a phase difference between a reception clock and a transmission clock at points A, B, C, and D of FIG.

<Description of Symbols for Main Parts of Drawings>

100,400: Clock generator 110,410: Memory controller

120,122,420,421: semiconductor memory

The present invention relates to a multichannel rambus system, and more particularly, to a multichannel rambus system using a RAMBUS memory.

Recently, in order to operate computer memory, graphics circuits, video, etc. at high speed, each device requires fast bandwidth and short response time. RAMBUS memory is used to meet this demand. Rambus memory is a high-performance memory device that transmits or stores data to a Rambus memory controller (RMC) at the edge of clock falling and rising at an input / output frequency of 300 MHz to 400 MHz.

Rambus memory transfers data and clock in the same direction to reduce skew of the data and clock. That is, in a memory circuit using a rambus memory, data and clocks in the rambus memory propagate along the databus and clock transmission lines. In this case, the clock is a clock for transmission (Clock To Master: CTM) transmitted from the clock generator to the Rambus memory controller and a clock for reception (Clock From Master: CFM) from the Rambus memory controller to Rambus memory. Divided.

1 is a diagram illustrating a conventional single channel Rambus system. Referring to FIG. 1, in a rambus system using the conventional rambus memories 120 and 122, one channel is formed from the rambus memory controller 110, and a plurality of rambus memories 120 and 122 are sequentially connected on one channel. do. The clock is generated from the clock generator 100 and supplied to the Rambus memory controller 110 and the Rambus memories 120 and 122, respectively. Each Rambus memory 120,122 is connected to a databus, CTM and CFM transmission line. The CTM and CFM on the channel have the same frequency, but the phases vary depending on the distance from the Rambus memory controller 110. Therefore, the CTM and CFM input to the Rambus memories 120 and 122 placed in the channel have different phases.

CTM and CFM are turned around at point A located in Rambus memory controller 110, where they have the same phase. 2 is a timing diagram showing phases of CTM and CFM at point A. FIG. However, as the positions of the rambus memories 120 and 122 move away from the rambus memory controller 110, the phase of the CFM becomes relatively slower than that of the CTM. 3 is a timing diagram showing the phase difference between CTM and CFM at point B. FIG. That is, the phase difference between the CTM and the CFM is generated according to the positions of the Rambus memories 120 and 122 placed in the channel. The phase difference between the CTM and the CFM is called tTR. tTR is expressed by Equation (1).

Here, tcycle is 360 ° as a phase corresponding to one cycle of the clock. Therefore, tTR becomes 0 when the phase difference between CTM and CFM is 0 °, tTR becomes 1 when the phase difference is 360 °, and tTR becomes 2 when the phase difference is 720 °. The response time of the Rambus memory controller is determined by the sum of the response time of the Rambus memory and tTR. Therefore, the response time of the Rambus memory controller is generally affected by the value of tTR, and when the channel having a large tTR is used, the response time of the Rambus memory controller is increased.

As a result, when the number of Rambus memories that can be connected to one channel is increased to increase the capacity of the memory, tTR in the channel is increased, thereby increasing the response time of the Rambus memory controller. Currently, in memory circuits using Rambus memory, Rambus memory can be extended to tTR = 5 on one channel, and further expansion is not suitable for circuit design. That is, there is a problem in that the expansion of the rambus memory is limited due to this tTR.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in a memory circuit using a rambus memory, the capacity of the memory is extended without being limited by tTR to the number of rambus memories that can be connected to one rambus memory controller. The objective is to provide a multichannel Rambus system that can do this.

The multi-channel Rambus system of the present invention for achieving the above object, the clock generator for generating a clock signal, at least one semiconductor memory for storing data, the operation of storing data in the semiconductor memory and the data stored in the semiconductor memory A memory controller for controlling an operation of recalling the data, a data bus electrically connected between the semiconductor memory and the memory controller to transfer data between the memory controller, and a clock generated by the clock generator. And a clock transmission line for transmitting a clock signal from the clock generator to the memory controller and a clock transmission line for transmitting a clock signal from the memory controller to the semiconductor memory.

In this case, each of the semiconductor memory and the memory controller is connected to the transmission clock transmission line, the reception clock transmission line and the data bus, and a plurality of channels connecting the semiconductor memory and the memory controller are formed. The channels are connected in parallel to the memory controller.

The turn around point of the transmission clock transmission line and the reception clock transmission line is preferably the memory controller. The memory controller may be a Rambus DRAM controller, and the semiconductor memory may be a Rambus DRAM.

According to the present invention, it is possible to minimize the response time of the memory controller and improve the memory capacity of the circuit by further connecting more semiconductor memories without increasing the response time of the memory controller.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments, only the present embodiments are provided to make the disclosure of the present invention complete and to fully inform the person skilled in the art the scope of the present invention. It is apparent that various modifications and improvements can be made by those skilled in the art within the spirit and scope of the invention.

4 is a diagram illustrating a multi-channel rambus system according to the present invention. Referring to FIG. 4, the multi-channel Rambus system of the present invention uses a rambus memory, and includes a clock generator 400, semiconductor memories 420, 421, 422, and 423, a memory controller 410, a data bus, and a clock transmission line 430.

The clock generator 400 generates a clock signal. The clock signal thus generated is supplied with a clock to a memory in the circuit.

The clock transmission line 430 is connected to each of the semiconductor memories 420, 421, 422, and 423 and the memory controller 410 starting from the clock generator 400, and is turned around in the memory controller 410. The clock transmission line 430 is divided into a reception clock transmission line 434 and a transmission clock transmission line 432. The transmission clock transmission line 432 is a clock transmission line in a direction from the clock generator 400 to the memory controller 410. The reception clock transmission line 434 is a clock transmission line in the direction from the memory controller 410 to the semiconductor memory 434.

The memory controller 410 controls the data transfer of the semiconductor memories 420, 421, 422, and 423, and is preferably a Rambus memory controller. Channels formed between the memory controller 410 and the semiconductor memory are connected in parallel to the memory controller 410.

The semiconductor memories 420, 421, 422, and 423 are elements that store data, and are preferably rambus memories. One or more semiconductor memories form channels that connect the memory controller 410 and the semiconductor memories 420, 421, 422, and 423, respectively, and each channel is connected in parallel to the memory controller 410. One channel may be connected to one or more semiconductor memories. The semiconductor memories 420, 421, 422, 423 are controlled by the memory controller 410 with respect to data transfer.

One or more semiconductor memories 420, 421, 422, and 423 are connected to a channel, and each semiconductor memory is connected to a transmission clock transmission line 432, a reception clock transmission line 434, and a data bus.

Each channel is configured such that tTR of the channel is 1 or less. Thus, the number of semiconductor memories connected to one channel is determined by the tTR of the channel. The turn-around points of the transmission clock transmission line and the reception clock transmission line in each channel are points A, B, C, and D in FIG. 4, and the phase difference is always 0 degrees at these points. Since each channel is connected in parallel to the memory controller 410, tTR in the entire circuit is fixed to 1 or less. Fig. 5 is a timing diagram showing the phase difference between the transmission clock CTM and the reception clock CFM at points A, B, C, and D. Referring to FIG. 5, it can be seen that phases of a transmission clock and a reception clock at points A, B, C, and D are the same.

As a result, since tTR affecting the response time of the memory controller in the present invention is limited to 1 or less, the response time of the memory controller is reduced.

As described above, the multi-channel Rambus system according to the present invention can reduce the response time of the memory controller by forming channels in parallel with the memory controller and fixing tTR of each channel to 1 or less. In addition, by forming more channels having a tTR of 1 or less in parallel, the capacity of the memory can be expanded without further increasing the response time of the memory controller.

Claims (3)

A clock generator for generating a clock signal; One or more semiconductor memories for storing data; A memory controller controlling an operation of storing data in the semiconductor memory and an operation of loading data stored in the semiconductor memory; A data bus electrically connected between the semiconductor memory and the memory controller to transfer data therebetween; And A transmission clock transmission line for supplying a clock generated by the clock generator to the semiconductor memory and the memory controller and transmitting a clock signal from the clock generator to the memory controller and the clock signal from the memory controller to the semiconductor memory. A clock transmission line comprising a receiving clock transmission line, Each of the semiconductor memory and the memory controller is connected to the transmission clock transmission line, the reception clock transmission line and the data bus; A channel connecting the semiconductor memory and the memory controller is formed, and the channel is formed in plural, Each of the channels is connected to the memory controller in parallel, and the phase difference of the channel divided by 360 ° is 1 or less. The multi-channel rambus system of claim 1, wherein a turnaround point of the transmission clock transmission line and the reception clock transmission line is the memory controller. 3. The multi-channel rambus system of claim 1 or 2, wherein the memory controller is a rambus DRAM controller and the semiconductor memory is a rambus DRAM.

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