KR100482462B1 - Manufacturing method of polysilicon thin film transistor of liquid crystal display device - Google Patents
Manufacturing method of polysilicon thin film transistor of liquid crystal display device Download PDFInfo
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- KR100482462B1 KR100482462B1 KR10-1998-0057447A KR19980057447A KR100482462B1 KR 100482462 B1 KR100482462 B1 KR 100482462B1 KR 19980057447 A KR19980057447 A KR 19980057447A KR 100482462 B1 KR100482462 B1 KR 100482462B1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 32
- 239000010409 thin film Substances 0.000 title abstract description 16
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 7
- 239000010410 layer Substances 0.000 claims abstract description 103
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 39
- 239000007772 electrode material Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
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Abstract
본 발명은 단순한 공정으로 오프셋 영역을 형성하여 누설 전류를 줄일 수 있는 액정 표시 장치의 폴리실리콘-박막 트랜지스터의 제조방법을 개시한다. 개시된 본 발명은 기판상에 비정질 실리콘층을 형성하고, 레이져빔 어닐링하여, 폴리 실리콘으로 된 채널층을 형성하는 단계와, 상기 채널층 상에 게이트 절연막과 게이트 전극용 금속막을 증착한다음 소정 크기로 상기 게이트 절연막과 게이트 전극용 금속막을 에칭하여 게이트 전극을 형성하는 단계로, 상기 에칭시 게이트 전극용 금속막을 과도 식각하여, 게이트 절연막의 선폭보다 게이트 전극의 크기가 작도록 게이트 전극을 형성하는 단계와, 상기 게이트 전극 상부, 노출된 게이트 절연막 상부 및 채널층 상부에 불순물이 도핑된 오프셋층을 형성하는 단계와, 상기 기판 결과물 표면에 층간 절연막을 증착하는 단계와, 상기 채널층 상부의 오프셋층이 소정 부분 노출되도록 층간 절연막의 소정 부분을 식각하는 단계와, 상기 노출된 오프셋층에 각각 소오스, 드레인 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention discloses a method of manufacturing a polysilicon-thin film transistor of a liquid crystal display device capable of reducing the leakage current by forming an offset region in a simple process. According to the present invention, an amorphous silicon layer is formed on a substrate, and the laser beam is annealed to form a channel layer made of polysilicon, and a gate insulating film and a metal film for a gate electrode are deposited on the channel layer. Etching the gate insulating film and the metal film for the gate electrode to form a gate electrode, wherein the gate electrode metal film is excessively etched during the etching to form the gate electrode so that the gate electrode is smaller than the line width of the gate insulating film; Forming an offset layer doped with impurities on the gate electrode, an exposed gate insulating layer, and an upper portion of the channel layer, depositing an interlayer insulating layer on a surface of the substrate, and forming an offset layer on the channel layer. Etching a predetermined portion of the interlayer insulating film to partially expose the exposed portion, and Characterized in that it comprises a source, comprising: forming a drain electrode.
Description
본 발명은 액정 표시 장치의 폴리실리콘-박막 트랜지스터의 제조방법에 관한 것으로, 보다 구체적으로는, 추가되는 마스크없이 오프셋 영역을 형성할 수 있는 액정 표시 장치의 폴리실리콘-박막 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a polysilicon-thin film transistor of a liquid crystal display device, and more particularly, to a method for manufacturing a polysilicon-thin film transistor of a liquid crystal display device capable of forming an offset region without an additional mask. .
일반적으로 폴리실리콘을 채널층으로 이용하는 폴리실리콘-박막 트랜지스터는 비정질 실리콘을 채널층으로 하는 박막 트랜지스터와 비교하였을 때, 소형화가 가능하고, 빠른 구동 능력을 가진다.In general, a polysilicon-thin film transistor using polysilicon as a channel layer can be miniaturized and has a fast driving capability as compared with a thin film transistor using amorphous silicon as a channel layer.
또한, 액정 표시 장치에 적용하였을 경우에는, 얇고 작은 모듈을 형성하여, 컴팩트한 디스플레이 장치를 구현할 수 있고, 드라이브 IC와 박막 트랜지스터가 동시에 형성되므로써, 비용도 감축된다.In addition, when applied to a liquid crystal display device, a thin and small module can be formed to implement a compact display device, and the cost is reduced by forming a drive IC and a thin film transistor at the same time.
이러한 폴리실리콘 박막 트랜지스터는 높은 드레인 전계로 인하여 높은 누설 전류가 발생되는데, 이를 방지하기 위하여, 오프셋 영역 또는 LDD(lightly doped drain) 영역을 형성하는 공정이 제안되었다.The polysilicon thin film transistor generates a high leakage current due to a high drain electric field. To prevent this, a process of forming an offset region or a lightly doped drain (LDD) region has been proposed.
먼저, 오프셋 영역을 형성하는 공정은, 도 1에 도시된 바와 같이, 유리 기판(1) 상부에 비정질 실리콘층을 형성한다음, 이 비정질 실리콘층을 액티브 형태로 패터닝하고, 결정질화 공정을 진행하여, 폴리실리콘층(2)을 형성한다. 이어, 게이트 절연막(3)을 증착한다음, 그 상부에 게이트 전극용 물질을 증착한다. 그후에, 게이트 전극용 물질을 소정 부분 패터닝하여, 게이트 전극(4)을 형성하고, 게이트 절연막(3)은 게이트 전극(4)의 선폭 보다는 소정폭만큼 크게 형성한다. 이때, 게이트 전극(4)의 끝단과 게이트 절연막(3)의 끝단까지의 거리(A)를 오프셋 영역이라 한다.First, as shown in FIG. 1, in the process of forming the offset region, an amorphous silicon layer is formed on the glass substrate 1, then the amorphous silicon layer is patterned into an active form, and the crystallization process is performed. , The polysilicon layer 2 is formed. Subsequently, the gate insulating film 3 is deposited, and then a gate electrode material is deposited thereon. Thereafter, the gate electrode material is partially patterned to form the gate electrode 4, and the gate insulating film 3 is formed to be larger than the line width of the gate electrode 4 by a predetermined width. At this time, the distance A between the end of the gate electrode 4 and the end of the gate insulating film 3 is called an offset region.
그리고나서, 게이트 절연막(3) 및 게이트 전극(4)을 마스크로 하여, 노출된 폴리실리콘층(2)에 N형의 고농도 불순물을 주입하여, 소오스, 드레인 영역(5a,5b)을 형성한다. Then, using the gate insulating film 3 and the gate electrode 4 as a mask, an N-type high concentration impurity is implanted into the exposed polysilicon layer 2 to form the source and drain regions 5a and 5b.
그후, 층간 절연막(6)을 증착하고, 소오스, 드레인 영역(5a,5b)이 노출되도록 소정 부분 패터닝한다음, 금속 배선(7)을 형성한다. 이때, 오프셋 영역(A)에는 게이트 절연막(3)이 존재하므로 불순물이 도핑되어 있지 않아, 상대적으로 전계를 낮추게된다. 따라서, 누설 전류를 방지할 수 있다. Thereafter, the interlayer insulating film 6 is deposited, and a predetermined portion is patterned so that the source and drain regions 5a and 5b are exposed, and then the metal wiring 7 is formed. At this time, since the gate insulating layer 3 exists in the offset region A, impurities are not doped, thereby lowering the electric field relatively. Therefore, leakage current can be prevented.
또한, 종래의 다른 방법으로 LDD 영역을 갖는 폴리실리콘-박막 트랜지스터는, 도 2에 도시된 바와 같이, 유리 기판(10) 상부에 비정질 실리콘층을 형성한다음, 이 비정질 실리콘층을 액티브 형태로 패터닝하고, 결정질화 공정을 진행하여, 폴리실리콘층(11)을 형성한다. 이어, 게이트 절연막(12)을 증착한다음, 그 상부에 게이트 전극용 물질을 증착한다. 그후에, 게이트 전극용 물질과 게이트 절연막(12)을 순차적으로 패터닝하여, 게이트 전극(13)을 형성한다. 이때, 게이트 절연막(12)과 게이트 전극(13)의 선폭은 같다. In addition, in another conventional method, a polysilicon-thin film transistor having an LDD region forms an amorphous silicon layer on the glass substrate 10 as shown in FIG. 2, and then patterned the amorphous silicon layer in an active form. Then, the crystallization process is performed to form the polysilicon layer 11. Subsequently, the gate insulating film 12 is deposited, and then a gate electrode material is deposited thereon. Thereafter, the gate electrode material and the gate insulating film 12 are sequentially patterned to form the gate electrode 13. At this time, the line widths of the gate insulating film 12 and the gate electrode 13 are the same.
그리고나서, 게이트 절연막(12) 및 게이트 전극(13)을 마스크로 하여, 노출된 폴리실리콘층(11)에 N형의 저농도 불순물을 주입하여, LDD 영역(14a,14b)을 형성한다. Then, using the gate insulating film 12 and the gate electrode 13 as a mask, an N-type low concentration impurity is implanted into the exposed polysilicon layer 11 to form LDD regions 14a and 14b.
그후, 절연막(15)을 증착한다음, 게이트 절연막(12) 및 게이트 전극(13)을 감싸도록 절연막(15)을 패터닝한다. 그리고나서, 절연막(15)을 마스크로 하여, 노출된 폴리실리콘층(11)에 고농도 불순물 이온을 주입하여 고농도 불순물 영역(16a,16b)을 형성한다. Thereafter, the insulating film 15 is deposited, and then the insulating film 15 is patterned to surround the gate insulating film 12 and the gate electrode 13. Then, using the insulating film 15 as a mask, high concentration impurity ions are implanted into the exposed polysilicon layer 11 to form high concentration impurity regions 16a and 16b.
그런다음, 층간 절연막(17)을 증착한다음, 고농도 불순물 영역(16a,16b)이 노출되도록 층간 절연막(17)을 소정 부분 패터닝한다음, 노출된 부분과 콘택되도록 금속 배선(7)을 형성한다. 이때, 고농도 불순물 영역(16a,16b) 사이에 존재하는 저농도 불순물 영역(14a,14b)이 존재하므로, 드레인 영역에서의 전계를 상대적으로 낮추게 되어, 누설 전류를 방지할 수 있다. Then, the interlayer insulating film 17 is deposited, the interlayer insulating film 17 is partially patterned to expose the high concentration impurity regions 16a and 16b, and the metal wiring 7 is formed to contact the exposed portion. . At this time, since the low concentration impurity regions 14a and 14b existing between the high concentration impurity regions 16a and 16b exist, the electric field in the drain region is relatively lowered, thereby preventing leakage current.
그러나, 상기와 같이 누설전류를 낮추기 위한 오프셋 영역을 형성하는 방법 또는 LDD 영역을 형성하는 방법은 다음과 같은 문제점이 있다.However, the method of forming the offset region or the LDD region for reducing the leakage current as described above has the following problems.
먼저, 오프셋 영역을 형성하는 방법은 일반적인 폴리실리콘-박막 트랜지스터 보다 게이트 절연막을 게이트 전극 보다 크게 패터닝하기 위하여 추가의 마스크 공정이 필요하게 된다. 이로인하여, 일반적인 폴리실리콘-박막 트랜지스터 공정보다 공정이 복잡해지는 문제점을 갖는다.First, the method of forming the offset region requires an additional mask process to pattern the gate insulating film larger than the gate electrode than the general polysilicon thin film transistor. As a result, there is a problem that the process is more complicated than a general polysilicon-thin film transistor process.
또한, LDD 영역을 형성하는 방법은 일반적인 폴리실리콘-박막 트랜지스터보다 게이트 전극을 감싸도록 절연막을 패터닝하는 공정과, LDD 이온을 주입하는 공정이 추가되므로, 제조 공정이 복잡해지고, 제조 비용또한 상승하게 된다.In addition, the method of forming the LDD region adds a step of patterning the insulating film to surround the gate electrode and a step of injecting LDD ions to the gate electrode rather than a general polysilicon thin film transistor, thereby increasing the manufacturing process and increasing the manufacturing cost. .
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 단순한 공정으로 오프셋 영역을 형성하여 누설 전류를 줄일 수 있는 액정 표시 장치의 폴리실리콘-박막 트랜지스터의 제조방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method of manufacturing a polysilicon-thin film transistor of a liquid crystal display device capable of reducing the leakage current by forming an offset region by a simple process.
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 실시예에 따르면, 본 발명은 기판상에 비정질 실리콘층을 형성하고, 레이져빔 어닐링하여, 폴리 실리콘으로 된 채널층을 형성하는 단계와, 상기 채널층 상에 게이트 절연막과 게이트 전극용 금속막을 증착한다음 소정 크기로 상기 게이트 절연막과 게이트 전극용 금속막을 에칭하여 게이트 전극을 형성하는 단계로, 상기 에칭시 게이트 전극용 금속막을 과도 식각하여, 게이트 절연막의 선폭보다 게이트 전극의 크기가 작도록 게이트 전극을 형성하는 단계와, 상기 게이트 전극 상부, 노출된 게이트 절연막 상부 및 채널층 상부에 불순물이 도핑된 오프셋층을 형성하는 단계와, 상기 기판 결과물 표면에 층간 절연막을 증착하는 단계와, 상기 채널층 상부의 오프셋층이 소정 부분 노출되도록 층간 절연막의 소정 부분을 식각하는 단계와, 상기 노출된 오프셋층에 각각 소오스, 드레인 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, according to an embodiment of the present invention, the present invention comprises the steps of forming an amorphous silicon layer on the substrate, the laser beam annealing, to form a channel layer of polysilicon, Depositing a gate insulating film and a gate electrode metal film on the channel layer, and etching the gate insulating film and the gate electrode metal film to a predetermined size to form a gate electrode, wherein the gate electrode metal film is excessively etched during the etching, Forming a gate electrode such that a gate electrode is smaller than a line width of the gate insulating layer, forming an offset layer doped with impurities on the gate electrode, an exposed gate insulating layer, and an upper portion of the channel layer; Depositing an interlayer insulating film on the surface, and interlayer so that the offset layer on the channel layer is partially exposed And etching a predetermined portion of the smoke, it characterized in that it includes forming the respective source and drain electrodes to the exposed offset layer.
본 발명에 의하면, 게이트 전극을 형성하는 공정시, 게이트 전극 물질을 과도 식각하여, 오프셋 영역을 구축하므로써, 별도의 오프셋 영역을 형성하기 위한 마스크 공정이 배제된다.According to the present invention, in the process of forming the gate electrode, a mask process for forming another offset region is eliminated by over-etching the gate electrode material to form an offset region.
또한, 폴리실리콘층을 형성하였던 PECVD 방식으로 노출된 폴리실리콘막 상부, 게이트 절연막 상부 및 게이트 전극 상부에 폴리실리콘 보다 밴드갭이 큰 N+ a-si:H층 또는 N+ μc-si:H층으로 된 오프셋층을 형성하므로써, 누설 전류를 큰 폭으로 감소시킬 수 있다.In addition, an N + a-si: H layer or an N + μc-si: H layer having a band gap larger than that of polysilicon on the polysilicon layer, the gate insulating layer, and the gate electrode exposed by the PECVD method in which the polysilicon layer was formed. By forming the offset layer, the leakage current can be greatly reduced.
이에따라, 제조 비용의 상승없이 누설 전류를 감소시킬 수 있다. Accordingly, the leakage current can be reduced without raising the manufacturing cost.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2c는 본 발명의 일 실시예에 따른 액정 표시 장치의 폴리실리콘-박막 트랜지스터의 제조방법을 설명하기 위한 각 공정별 단면도이다. 2A to 2C are cross-sectional views of respective processes for explaining a method of manufacturing a polysilicon thin film transistor of a liquid crystal display according to an exemplary embodiment of the present invention.
먼저, 도 3a를 참조하여, 유리 기판(20) 상부에 PECVD(plasma enhanced chemical vapor deposition) 방식으로 실리콘층을 형성한다. 이때, 증착 당시의 실리콘층은 결정이 없는 비정질 실리콘층이다. 그후, 이러한 비정질 실리콘층을 결정질화하기 위하여, 레이져 어닐링 공정을 실시하여, 폴리실리콘층(21)을 형성한다. 그후에, 폴리실리콘층 상부에 게이트 절연막(22)과 게이트 전극용 물질을 순차적으로 적층한다음, 게이트 전극용 물질 상부에 게이트 전극을 한정하기 위한 레지스트 패턴(24)을 형성한다. 그런다음, 레지스트 패턴(24)을 마스크로 하여, 게이트 전극용 물질 및 게이트 절연막(22)을 패터닝하여 게이트 전극(23)을 형성한다. 이때, 게이트 전극용 물질을 식각할 때, 게이트 전극용 물질과 게이트 절연막 물질과 식각 선택비가 높은 물질을 이용하여 과도 식각을 진행하여, 게이트 전극(23)이 레지스트 패턴(24)의 선폭보다는 좁은 선폭을 갖도록 한다. 이에따라, 게이트 전극(23)의 선폭은 게이트 절연막(22)의 선폭보다 약간 작게되어, 별도의 마스크 공정없이 수직 오프셋 영역이 형성된다. 그리고나서, 폴리실리콘층(21)을 액티브 형태로 패터닝한다. 이때, 게이트 전극(23)을 형성한다음, 폴리실리콘층(21)을 패터닝함에 따라, 폴리실리콘층(21)과 게이트 절연막(22)간의 계면 특성을 향상시킬수 있다.First, referring to FIG. 3A, a silicon layer is formed on a glass substrate 20 by plasma enhanced chemical vapor deposition (PECVD). At this time, the silicon layer at the time of deposition is an amorphous silicon layer without a crystal. Thereafter, in order to crystallize such an amorphous silicon layer, a laser annealing process is performed to form the polysilicon layer 21. Thereafter, the gate insulating film 22 and the gate electrode material are sequentially stacked on the polysilicon layer, and then a resist pattern 24 for defining the gate electrode is formed on the gate electrode material. Then, the gate electrode 23 is formed by patterning the gate electrode material and the gate insulating film 22 using the resist pattern 24 as a mask. In this case, when the gate electrode material is etched, the etching process is performed using the gate electrode material, the gate insulating material, and the material having a high etching selectivity, so that the gate electrode 23 has a narrower line width than the line width of the resist pattern 24. To have. Accordingly, the line width of the gate electrode 23 is slightly smaller than the line width of the gate insulating film 22, so that a vertical offset region is formed without a separate mask process. Then, the polysilicon layer 21 is patterned in an active form. At this time, the gate electrode 23 is formed and then the polysilicon layer 21 is patterned, so that the interface characteristics between the polysilicon layer 21 and the gate insulating film 22 can be improved.
그리고 난 다음, 도 3b에 도시된 바와 같이, 상기 실리콘층을 형성하였던 PECVD 방식으로, 비등방성 증착방식으로 고농도 N형 불순물이 도핑된 수소화 비정질 실리콘층(이하, N+ a-si:H층) 또는 고농도 N형 불순물이 도핑된 수소화된 미세 결정질 실리콘층(이하, N+ μc-si:H층)을 형성하여, 오프셋층(25)을 형성한다. 또한, 불순물이 도핑되지 않은 a-si:H층 또는 μc-si:H층을 증착한다음, N형의 불순물을 이온 주입하여 오프셋층(25)을 형성할 수 있다. 이때, 오프셋층(25)은 비등방성으로 증착되므로, 폴리실리콘층(21) 상부, 노출된 게이트 절연막(22) 상부 및 게이트 전극(23) 상부에만 형성되고, 상기 채널층을 형성하였던 PECVD 방식으로 형성되므로, 별도의 추가 비용이 없다.Then, as illustrated in FIG. 3B, a hydrogenated amorphous silicon layer doped with a high concentration of N-type impurities by an anisotropic deposition method using PECVD, which forms the silicon layer (hereinafter, N + a-si: H layer). Alternatively, an offset layer 25 is formed by forming a hydrogenated fine crystalline silicon layer (hereinafter, N + μc-si: H layer) doped with a high concentration N-type impurity. In addition, an a-si: H layer which is not doped with impurities, or After depositing the μc-si: H layer, the N-type impurities may be ion implanted to form the offset layer 25. In this case, since the offset layer 25 is anisotropically deposited, the offset layer 25 is formed only on the polysilicon layer 21, on the exposed gate insulating layer 22, and on the gate electrode 23, and in the PECVD method in which the channel layer is formed. As it is formed, there is no additional cost.
여기서, 상기 폴리실리콘층(21) 상부에 형성되는 오프셋층(25a)을 수직 오프셋층이 되고, 게이트 절연막(22) 상부에 형성되는 오프셋층을 수평 오프셋(25b)층이 된다.Here, the offset layer 25a formed on the polysilicon layer 21 becomes a vertical offset layer, and the offset layer formed on the gate insulating film 22 becomes a horizontal offset 25b layer.
이와같이 오프셋층을 N+ a-si:H층 또는 N+ μc-si:H층으로 형성하면, 폴리실리콘층보다 상기 N+ a-si:H층 또는 N+ μc-si:H층의 밴드갭이 훨씬 크므로(N+ a-si:H층의 밴드갭:1.8eV, 불순물이 도핑된 폴리실리콘층의 밴드갭:1.14eV), 누설 전류를 더 많이 감소시키게 된다.In this way the offset layer N + a-si: H layer or an N + μc-si: when forming the H layer, polysilicon layer than the N + a-si: H layer or an N + μc-si: the H layer bandgap Since this is much larger (bandgap of N + a-si: H layer: 1.8 eV, impurity doped polysilicon layer: 1.14 eV), the leakage current is further reduced.
그후, 결과물 상부에 층간 절연막(26)을 증착한다.Thereafter, an interlayer insulating film 26 is deposited on the resultant.
그리고나서, 도 3c에 도시된 바와 같이, 수직 오프셋층(25a)의 소정 부분이 노출되도록 층간 절연막(26)의 소정 부분을 식각한다음, 노출된 수직 오프셋층(25a)과 각각 콘택되도록, 소오스, 드레인 전극(27)을 형성한다.Then, as shown in FIG. 3C, a predetermined portion of the interlayer insulating film 26 is etched so that a predetermined portion of the vertical offset layer 25a is exposed, and then the source is contacted with the exposed vertical offset layer 25a, respectively. The drain electrode 27 is formed.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 게이트 전극을 형성하는 공정시, 게이트 전극 물질을 과도 식각하여, 오프셋 영역을 구축하므로써, 별도의 오프셋 영역을 형성하기 위한 마스크 공정이 배제된다.As described in detail above, according to the present invention, in the process of forming the gate electrode, a mask process for forming a separate offset region is eliminated by over-etching the gate electrode material to form an offset region.
또한, 폴리실리콘층을 형성하였던 PECVD 방식으로 노출된 폴리실리콘막 상부, 게이트 절연막 상부 및 게이트 전극 상부에 폴리실리콘 보다 밴드갭이 큰 N+ a-si:H층 또는 N+ μc-si:H층으로 된 오프셋층을 형성하므로써, 누설 전류를 큰 폭으로 감소시킬 수 있다.In addition, an N + a-si: H layer or an N + μc-si: H layer having a larger band gap than polysilicon on the polysilicon layer, the gate insulating layer, and the gate electrode exposed by the PECVD method in which the polysilicon layer was formed. By forming the offset layer, the leakage current can be greatly reduced.
이에따라, 제조 비용의 상승없이 누설 전류를 감소시킬 수 있다. Accordingly, the leakage current can be reduced without raising the manufacturing cost.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1 및 도 2는 종래의 폴리실리콘-박막 트랜지스터의 제조방법을 설명하기 위한 단면도.1 and 2 are cross-sectional views illustrating a conventional method for manufacturing a polysilicon thin film transistor.
도 3a 내지 도 3c는 본 발명에 따른 폴리실리콘-박막 트랜지스터의 제조방법을 설명하기 위한 각 공정별 단면도.3A to 3C are cross-sectional views of respective processes for explaining a method of manufacturing a polysilicon thin film transistor according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
20 : 기판 21 : 폴리실리콘층20: substrate 21: polysilicon layer
22 : 게이트 절연막 23 : 게이트 전극22 gate insulating film 23 gate electrode
24 : 레지스트 패턴 25 : 오프셋층24: resist pattern 25: offset layer
26 : 층간 절연막 27 : 소오스, 드레인 전극26 interlayer insulating film 27 source, drain electrode
Claims (5)
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| US8790967B2 (en) | 2007-05-31 | 2014-07-29 | Samsung Display Co., Ltd. | Method of fabricating polycrystalline silicon layer, TFT fabricated using the same, method of fabricating TFT, and organic light emitting diode display device having the same |
| US8513669B2 (en) | 2007-08-22 | 2013-08-20 | Samsung Display Co., Ltd. | Thin film transistor including metal or metal silicide structure in contact with semiconductor layer and organic light emitting diode display device having the thin film transistor |
| US8101952B2 (en) | 2008-03-27 | 2012-01-24 | Samsung Mobile Display Co., Ltd. | Thin film transistor, method of fabricating the same, and organic lighting emitting diode display device including the same |
| US8253141B2 (en) | 2008-07-14 | 2012-08-28 | Samsung Mobile Display Co., Ltd. | Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the thin film transistor |
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| Publication number | Publication date |
|---|---|
| KR20000041547A (en) | 2000-07-15 |
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