KR100460806B1 - Semiconductor device - Google Patents

Abstract

The present invention relates to a structure of a capacitor array. In particular, in a codec product that codes / decodes data recorded in a capacitor array in a u-law manner, a gain characteristic change of a codec product that varies with or without molding compound of a capacitor array is described. To improve, cover the dummy metal layer on top of the pattern of the capacitor array to prevent the gain characteristics from changing due to increasing parasitic capacitors due to the pressure of the molding compound, or to determine the off-set voltage according to the package type. By changing the capacitor size of the capacitor array appropriately, the present invention relates to a semiconductor device in which a change in gain characteristics with and without molding is eliminated.

Description

Semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a capacitor array, and more particularly, to a semiconductor device for use in a codec product that codes / decodes data recorded in a capacitor array in a u-law manner.

In general, the A-Law method and the u-Law method can be divided according to the method of coding and decoding in the D / A converter of a codec product. Although the A-Law method and the u-Law method have various differences, the A-Law method Outputs an analog signal "0" when converting the digital signal "0", and the u-Law method has an off-set voltage and thus has a constant level of output value when converting the digital signal "0".

The u-Law off-set voltage is formed as a specific capacitor array located at the edge of the capacitor array in the chip, and the area ratio is very large in determining the off-set voltage by the area ratio.

However, the off-set voltage value changes before or after the package of the capacitor array, that is, with or without molding compound.

The change of off-set voltage is calculated by the area ratio of the parasitic capacitors present in the capacitor array due to the pressing pressure of the molding compound during package progression. Will change.

The change in the off-set voltage changes the gain characteristics, which degrades the quality of the codec product.

1 is a schematic diagram showing a circuit of a capacitor array according to a conventional u-Law method, including some capacitor arrays 1 determining off-set voltages, a plurality of capacitor arrays 10 storing predetermined data, and In accordance with a predetermined input control signal (Vin), the signal output from the capacitor array (1, 10) and a predetermined comparison voltage (Vref) is received and compared to the comparison means 15 for outputting a corresponding signal Consists of.

That is, the off-set voltage and gain characteristics are determined by the ratio of the area of the plurality of capacitor arrays 1 and the plurality of capacitor arrays 10, and at the pressing pressure of the compounds during molding. Due to the increase in parasitic capacitors between the capacitor arrays and the area ratio between the capacitor array 1 and the plurality of capacitor arrays 10 which determine the off-set voltage due to the parasitic capacitors, the area ratio of the u-Law capacitor array is changed. Off-set voltage and gain characteristics change.

FIG. 2 is a plan view illustrating a unit structure of the capacitor for the offset voltage of FIG. 1, wherein the semiconductor substrate 3, the first electrode 5 formed on the substrate 3, and the first electrode 5 are illustrated in FIG. A second electrode 7 spaced apart from the second electrode, an insulating film (not shown) formed between the first electrode 5 and the second electrode 7, and a first electrode electrically connected to the first electrode 5. A metal layer 8 and a second metal layer 9 electrically connected to the second electrode 7 are formed.

The planar structure of such a capacitor is a plan view of a 0.055 capacitor unit (0.055 Cu; Capacitor unit) of the capacitor array (1) for the off-set voltage of FIG. 1, one second to the first electrode (5) An electrode 7 is formed to form a capacitor unit.

FIG. 3 is a graph showing gain tracking characteristics under conventional conditions, and is a graph showing gain characteristics before using a pre-packing molding compound and after using a post-packaging molding compound.

As shown in the graph, the output gain of the capacitor array has a stable gain that falls within the tolerance range of the international communication protocol before the package, but the tolerance range of ± 47.1dBm after using the molding compound after package It can be seen that it outputs an unstable gain value significantly out of 0.38 dB).

SUMMARY OF THE INVENTION In order to solve the problems of the prior art, an object of the present invention is to provide an offset voltage according to the presence or absence of molding compound of a capacitor array in a codec product that codes / decodes data recorded in a capacitor array in a u-law manner. The present invention provides a semiconductor device that compensates for the deterioration of gain characteristics of a specific capacitor for determining process and capacitor structure.

In order to achieve the above object, a structure of a semiconductor device according to an embodiment of the present invention includes a first capacitor formed on a semiconductor substrate in a unit capacitor that determines an off-set voltage of a semiconductor coded and decoded by a u-Law method. An electrode, a second electrode formed to be spaced apart from the first electrode, a third electrode formed to be spaced apart from the first electrode, an insulating film formed between the first electrode and the second and third electrodes, and the first electrode And a first metal layer electrically connected to the second metal layer, and a second metal layer electrically connected to the second electrode.

In addition, in order to achieve the above object, a structure of a semiconductor device according to another embodiment of the present invention is a unit capacitor for determining an off-set voltage of a semiconductor coded and decoded by a u-Law method, formed on a semiconductor substrate. A first electrode, a second electrode formed to be spaced apart from the first electrode, a third electrode formed to be spaced apart from the first electrode, an insulating film formed between the first electrode, and the second and third electrodes, And a first metal layer electrically connected to the first electrode, and a second metal layer electrically connected to the second and third electrodes.

In addition, in order to achieve the above object, a structure of a semiconductor device according to another embodiment of the present invention, a capacitor array formed on a semiconductor substrate, an insulating film formed on the capacitor array, and formed on the insulating film It is formed of a dummy metal layer that serves as a buffer during molding.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 is a schematic diagram illustrating a circuit of a capacitor array by a u-Law method according to an embodiment of the present invention, in which a part of the capacitor array 30 determining an offset voltage and a plurality of pieces of predetermined data are stored. Comparing means 70 for receiving and comparing the capacitor array 50 and the signal output from the capacitor array in accordance with a predetermined input control signal (Vin) and a predetermined comparison voltage (Vref) and then outputs a signal corresponding thereto. It consists of.

That is, according to the present invention, by installing one more capacitors 33 and 37 in the capacitor array 30 that determines the offset voltage as shown in the drawing, parasitic capacitors between the arrays increase due to the pressing pressure of the compound during molding. The parasitic capacitor prevents the area ratio between the capacitor array 30 and the plurality of capacitor arrays 50, which determine the off-set voltage, from increasing further, thereby preventing the off-set voltage and gain characteristics of the u-Law capacitor array from changing. To compensate.

FIG. 5 is a plan view illustrating a unit structure of the capacitor for the offset voltage of FIG. 4 according to an embodiment of the present invention. The semiconductor substrate 20 and the first electrode 33 formed on the substrate 20 are shown in FIG. And a second electrode 35 formed to be spaced apart from the first electrode 33, a third electrode 37 formed to be spaced apart from the first electrode 33, and a first electrode 33 and a second electrode. And an insulating film (not shown) formed between the third electrodes 35 and 37, the first metal layer 41 electrically connected to the first electrode 33, and the second electrode 35. The second metal layer 43 is formed.

That is, as described above, the second and third electrodes 35 and 37 are spaced apart from each other on the first electrode 33, and only the first and second electrodes 33 and 35 are respectively formed of the metal layer 41, 43 and the third electrode 37 is not electrically connected.

The capacitor structure as described above is preferably used in a ceramic package that does not use molding compound.

FIG. 6 is a plan view showing a unit structure of the capacitor for the offset voltage of FIG. 4 according to another embodiment of the present invention. The semiconductor substrate 20 and the first electrode 33 formed on the substrate 20 are shown in FIG. And a second electrode 35 formed to be spaced apart from the first electrode 33, a third electrode 37 formed to be spaced apart from the first electrode 33, and a first electrode 33 and a second electrode. And an insulating film (not shown) formed between the third electrodes 35 and 37, the first metal layer 41 electrically connected to the first electrode 33, and the second and third electrodes 35 and 37. ) Is formed of a second metal layer 45 electrically connected thereto.

That is, as described above, the second and third electrodes 35 and 37 are formed on the first electrode 33 to be spaced apart from each other, and the first metal layer 41 is electrically connected to the first electrode 33. The second metal layer 45 is electrically connected to the second and third electrodes 35 and 37.

Such a structure is preferably used in a capacitor process for packaging using a molding compound, and the third electrode 37 relatively reduces the area ratio that increases due to the parasitic capacitor of the capacitor array generated during molding. It is possible to prevent the set voltage from changing.

FIG. 7 is a layout diagram illustrating a fabrication structure of a capacitor array according to still another embodiment of the present invention. The capacitor array 30 is formed on the semiconductor substrate 20 and determines an offset voltage. A plurality of capacitor arrays 50 storing data, an insulating film (not shown) formed on the capacitor arrays 30 and 50, and a dummy metal layer formed on the insulating film to buffer the molding. 80).

The dummy metal layer 80 is a buffer metal layer that reduces the pressure of the compound applied to the capacitor array when molding the semiconductor chip on which the capacitor arrays 30 and 50 are formed. Increases and changes in off-set voltage can be prevented.

FIG. 8 is a graph showing gain tracking characteristics under the conditions of the present invention, which shows the gain characteristics before using the pre-packing molding compound and after using the post-packaging molding compound.

As shown in the graph, it can be seen that the output gain of the capacitor array has a stable gain within the tolerance range of the international communication protocol regardless of the presence or absence of molding compound of the pre-package or post-package capacitor array. .

Therefore, as described above, the present invention covers the dummy metal layer on the pattern of the capacitor array or improves the off-set voltage according to the package type in order to improve the gain characteristic change of the codec product that varies depending on the molding compound. By changing the capacitor size of the capacitor array to be determined, it is possible to eliminate the change in gain characteristics with and without molding.

1 is a schematic diagram illustrating a circuit of a capacitor array according to a conventional u-Law method.

FIG. 2 is a plan view illustrating a unit structure of the capacitor for the offset voltage of FIG. 1.

3 is a graph showing gain tracking characteristics under conventional conditions.

4 is a schematic diagram illustrating a circuit of a capacitor array by a u-Law method according to an embodiment of the present invention.

5 is a plan view illustrating a unit structure of the capacitor for the offset voltage of FIG. 4 according to an embodiment of the present invention.

6 is a plan view illustrating a unit structure of the capacitor for the offset voltage of FIG. 4 according to another embodiment of the present invention.

7 is a layout diagram illustrating a manufacturing structure of a capacitor array according to another embodiment of the present invention.

8 is a graph showing gain tracking characteristics under the conditions of the present invention.

* Explanation of symbols for the main parts of the drawings

20: semiconductor substrate. 30: Some capacitor that determines the off-set voltage.

33: First electrode. 35: second electrode.

37: third electrode. 41: first metal layer.

43, 45: second metal layer. 50: array of capacitors.

80: dummy metal layer.

Claims (6)

In the unit capacitor to determine the off-set voltage of the semiconductor coding and decoding in a u-Law method, A first electrode formed on the semiconductor substrate; A second electrode spaced apart from the first electrode; A third electrode spaced apart from the first electrode; An insulating film formed between the first electrode and the second and third electrodes; A first metal layer electrically connected to the first electrode; And And a second metal layer electrically connected to the second electrode. The method of claim 1, wherein the capacitor array structure, A semiconductor device comprising a capacitor array structure used in a step of not performing a molding compound process. In the unit capacitor to determine the off-set voltage of the semiconductor coding and decoding in a u-Law method, A first electrode formed on the semiconductor substrate; A second electrode spaced apart from the first electrode; A third electrode spaced apart from the first electrode; An insulating film formed between the first electrode and the second and third electrodes; A first metal layer electrically connected to the first electrode; And And a second metal layer electrically connected to the second and third electrodes. The method of claim 3, wherein the capacitor array structure, A semiconductor device comprising a capacitor array structure used in a step of performing a molding compound step. A capacitor array formed on the semiconductor substrate; An insulating film formed on the capacitor array; And A semiconductor device, characterized in that formed on the insulating film formed of a dummy metal layer that serves as a buffer during molding. The method of claim 5, wherein the capacitor array structure, A semiconductor device comprising a capacitor array structure used in a step of not performing a molding compound process.

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