KR100457409B1 - Method for forming metal interconnection of semiconductor device to stably form barrier layer of metal interconnection by simple process and stabilize contact resistance - Google Patents

Method for forming metal interconnection of semiconductor device to stably form barrier layer of metal interconnection by simple process and stabilize contact resistance Download PDF

Info

Publication number
KR100457409B1
KR100457409B1 KR1019970079327A KR19970079327A KR100457409B1 KR 100457409 B1 KR100457409 B1 KR 100457409B1 KR 1019970079327 A KR1019970079327 A KR 1019970079327A KR 19970079327 A KR19970079327 A KR 19970079327A KR 100457409 B1 KR100457409 B1 KR 100457409B1
Authority
KR
South Korea
Prior art keywords
layer
titanium
film
metal
metal interconnection
Prior art date
Application number
KR1019970079327A
Other languages
Korean (ko)
Other versions
KR19990059130A (en
Inventor
손현철
김장식
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019970079327A priority Critical patent/KR100457409B1/en
Publication of KR19990059130A publication Critical patent/KR19990059130A/en
Application granted granted Critical
Publication of KR100457409B1 publication Critical patent/KR100457409B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to stably form a barrier layer of a metal interconnection by a simple process and stabilize contact resistance by inserting a reaction control layer into a Ti layer to be used as a barrier metal layer or a intermetal adhesion layer to control a reaction of TiSix or TiNx and by performing an RTP(rapid thermal process) at a single temperature. CONSTITUTION: A substrate(11) having a contact hole is prepared. The first titanium layer(13a) is formed on the resultant structure. A titanium nitride layer(13e) or a titanium oxide layer is formed as a reaction control layer(13b) on the first titanium layer. The second titanium layer(13c) is formed on the reaction control layer. An RTP is performed in an atmosphere of ammonia or nitrogen to make the first titanium layer react with the substrate or a metal layer(14) formed on the substrate so that a titanium silicide layer(13d) or a titanium metal compound layer is formed in the base part of the contact hole while the second titanium layer is transformed into a titanium nitride layer. A metal layer is deposited to fill the contact hole.

Description

반도체 소자의 금속 배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 금속 배선의 베리어 메탈층 또는 금속간 접착층으로 사용될 티타늄(Ti) 박막 내에 반응 조절막을 삽입하고 단일 온도 조건으로 급속 열처리(Rapid Thermal Oxide ;이하 RTP라 함) 공정을 실시하여 금속 배선의 베리어 메탈층을 안정성 있게 형성하고 콘택 저항을 안정화시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming metal wirings in semiconductor devices, and more particularly, to insert a reaction control film into a titanium (Ti) thin film to be used as a barrier metal layer or an intermetallic adhesive layer of a metal wiring, and to perform rapid heat treatment under a single temperature condition. It relates to a method for forming a metal wiring of a semiconductor device capable of stably forming the barrier metal layer of the metal wiring by performing a process (referred to as RTP) and to stabilize the contact resistance.

일반적으로, 티타늄/티타늄나이트라이드(Ti/TiN) 또는 티타늄실리사이드/티타늄나이트라이드(TiSi2/TiN)와 같은 메탈 콘택에 사용되는 베리어 메탈 층착시, 메탈 콘택에 Ti을 증착한 후 NH3 분위기하에서 RTP 공정을 실시한다. 이때, 콘택 홀에 증착된 Ti의 기판쪽은 실리콘과 반응하여 티타늄실리사이드(TiSix) 화합물을 형성하고 표면쪽은 NH3와 반응하여 티타늄나이트라이드(TiNx)를 형성한다. 그러나 RTN으로 형성된 TiNx의 경우, x〈0.5인 Ti-리치 TiN이고 TiSix와 TiNx의 최적 반응 온도가 서로 달라 단일 온도 RTN의 경우 TiNx과 TiSix의 두께비 조절이 어렵게 된다.In general, when depositing a barrier metal used for a metal contact such as titanium / titanium nitride (Ti / TiN) or titanium silicide / titanium nitride (TiSi 2 / TiN), Ti is deposited on the metal contact under NH 3 atmosphere. Perform the RTP process. At this time, the substrate side of Ti deposited in the contact hole reacts with silicon to form a titanium silicide (TiSi x ) compound, and the surface side reacts with NH 3 to form titanium nitride (TiN x ). However, in the case of TiN x formed of RTN, since Ti <rich TiN having x <0.5 and optimum reaction temperatures of TiSi x and TiN x are different from each other, it is difficult to control the thickness ratio of TiN x and TiSi x in a single temperature RTN.

이러한 문제점을 해결하기 위하여, 종래에는 RTN 공정을 두 온도 조건에서 진행하여 반응을 조절하므로써 TiNx 과 TiSix의 두께 비율을 조절하는 방법을 사용하였으나, 공정 과정이 복잡하고 소자의 동작 안정화를 얻을 수 없는 문제점이 있다.In order to solve this problem, conventionally, a method of adjusting the thickness ratio of TiN x and TiSi x by controlling the reaction by proceeding the RTN process at two temperature conditions, but the process is complicated and the operation of the device can be stabilized There is no problem.

따라서, 본 발명은 금속 배선의 베리어 메탈층 또는 금속층간 접착층으로 사용될 Ti 내에 TiSix 또는 TiNx의 반응을 조절하기 위한 반응 조절막을 삽입하고 단일 온도의 RTP 공정을 실시하여, 금속 배선의 장벽층을 단순한 공정으로 안정되게 형성하고 콘택 저항을 안정화시키므로써 소자의 수율을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to insert a reaction control film for controlling the reaction of TiSix or TiN x in Ti to be used as the barrier metal layer or intermetallic adhesive layer of the metal wiring, and to perform a single temperature RTP process to simplify the barrier layer of the metal wiring. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device capable of improving the yield of the device by stably forming the process and stabilizing the contact resistance.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 하부 구조가 형성된 기판 상부에 층간 절연막을 형성하고 선택된 영역을 패터닝하여 콘택홀을 형성하는 단계와, 상기 콘택홀을 포함한 전체 구조 상부에 베리어 메탈층인 제 1 티타늄막, 반응 방지막 및 제 2 티타늄막을 순차적으로 형성하는 단계와, 급속 열처리 공정을 실시하여, 상기 콘택 홀 기저부의 제 1 티타늄막과 상기 기판의 실리콘 또는 금속의 반응으로 티타늄실리사이드층 또는 티타늄 메탈 화합물층을 형성하고, 상기 콘택 홀 기저부의 제 2 티타늄막과 상기 콘택 홀 측벽 및 상기 절연막 상부의 제 1 및 제 2 티타늄막을 티타늄나이트라이드막으로 변화시키는 단계와, 전체 구조 상부에 금속층을 형성하여 콘택 홀을 매립하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In accordance with another aspect of the present invention, there is provided a method of forming a metal wiring in a semiconductor device, the method including: forming an interlayer insulating film on a substrate on which a lower structure is formed and forming a contact hole by patterning a selected region; Sequentially forming a first titanium film, a reaction prevention film, and a second titanium film, which are barrier metal layers on the structure, and performing a rapid heat treatment process, thereby forming a first titanium film of the contact hole base part and a silicon or metal of the substrate. Reacting to form a titanium silicide layer or a titanium metal compound layer, and changing the second titanium film and the contact hole sidewalls and the first and second titanium films on the insulating film to a titanium nitride film as a whole; Forming a metal layer on top of the structure to fill the contact holes; It characterized.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 1(a) 내지 1(c)는 본 발명의 제 1 실시 예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도로서, Ti 박막이 금속 배선의 장벽층으로 사용되는 경우를 나타낸다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to a first embodiment of the present invention, wherein a Ti thin film is used as a barrier layer of the metal wirings. Indicates the case where it is used.

도 1(a)에 도시된 바와 같이, 실리콘 기판(11) 상부에 층간 절연막(12)을 형성한 후 선택된 영역을 패터닝하여 콘택 홀을 형성한다. 이후 콘택 홀을 포함하는 전체 구조 상부에 베리어 메탈층(13)으로 사용될 제 1 Ti막(13a), 반응 조절막(13b) 및 제 2 Ti막(13c)을 순차적으로 형성한다. 이때, 반응 조절막(13b)으로는 TiN 또는 Ti-옥사이드가 사용될 수 있다.As shown in FIG. 1A, a contact hole is formed by forming an interlayer insulating film 12 on the silicon substrate 11 and patterning a selected region. Thereafter, the first Ti film 13a, the reaction control film 13b, and the second Ti film 13c to be used as the barrier metal layer 13 are sequentially formed on the entire structure including the contact hole. In this case, TiN or Ti-oxide may be used as the reaction control layer 13b.

도 1(b)에 도시된 바와 같이, 암모니아(NH3) 또는 질소(N2) 분위기 하에서 RTP(Rapid Thermal Process ;RTP) 공정을 실시한다. 이때 콘택 기저부에서는 반응 조절막(13b) 하부의 제 1 Ti막(13a)의 Ti과 실리콘 기판(11)의 실리콘이 반응하여 TiSix층(13d)이 형성되며, 콘택 기저부 반응 조절층 상부의 제 2 티타늄막(13c), 콘택 측벽 및 층간 절연막(12) 상의 제 1 및 제 2 Ti막(13a, 13c)은 RTP 공정에 의해 TiNx막(13e)으로 변화된다.As shown in FIG. 1B, a rapid thermal process (RTP) process is performed under ammonia (NH 3 ) or nitrogen (N 2 ) atmosphere. At this time, Ti on the contact base portion of the first Ti film 13a under the reaction control film 13b reacts with silicon on the silicon substrate 11 to form a TiSix layer 13d, and the second on the contact base reaction control layer. The first and second Ti films 13a and 13c on the titanium film 13c, the contact sidewall and the interlayer insulating film 12 are changed to the TiN x film 13e by the RTP process.

도 1(c)에 도시된 바와 같이, 베리어 메탈층(13)이 형성된 전체 구조 상부에 금속층(14)을 형성한다. 이때, 금속층(14)으로는 알루미늄(Al), 텅스텐(W) 및 구리(Cu) 중 어느 하나가 사용된다.As shown in FIG. 1C, the metal layer 14 is formed on the entire structure where the barrier metal layer 13 is formed. At this time, any one of aluminum (Al), tungsten (W) and copper (Cu) is used as the metal layer 14.

이와 같이, TiN 또는 Ti-옥사이드를 베리어 메탈 또는 금속층간 접착층으로 사용되는 Ti 사이에 삽입시켜 티타늄-실리사이데이션 및 티타늄-나이트라이데이션 반응의 반응 조절막으로 사용한다. TiN를 반응 조절막으로 사용할 경우 RTN 공정을 600℃ 이상에서 실시하더라도 Ti층 사이에 삽입된 TiN 또는 Ti-옥사이드막이 티타늄-실리사이데이션 반응을 조절하여 TiN 상부의 Ti이 NH3와 충분히 반응하여 원하는 두께의 TiNx이 형성될 수 있으며, RTN 공정을 단순화시키고 균일한 티타늄-실리사이드/TiNx 박막을 형성하여 콘택 저항을 안정화시킬 수 있다. 또한 이러한 방식으로 형성된 TiNx은 스퍼터 방식으로 제조된 TiN에 비하여 더욱 밀도가 높아 텅스텐-플러그 또는 텅스텐-배선용으로도 적합하다.As such, TiN or Ti-oxide is intercalated between Ti used as a barrier metal or an intermetallic adhesive layer to be used as a reaction control film for titanium-silicide and titanium-nitride reactions. When using TiN as a reaction control film, even if the RTN process is performed at 600 ° C. or higher, the TiN or Ti-oxide film interposed between the Ti layers controls the titanium-silicide reaction so that the Ti on the TiN reacts with NH 3 sufficiently. A thickness of TiN x may be formed, and the contact resistance may be stabilized by simplifying the RTN process and forming a uniform titanium-silicide / TiN x thin film. In addition, the TiN x formed in this manner is more dense than the TiN produced by the sputtering method and is suitable for tungsten-plug or tungsten-wiring.

도 2(a) 내지 2(c)는 본 발명의 제 2 실시 예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to a second embodiment of the present invention.

도 2(a)에 도시된 바와 같이, 하부 금속층(21)이 형성된 기판 상부에 층간 절연막(22)을 형성한 후 선택된 영역을 패터닝하여 콘택 홀을 형성한다. 이후 콘택 홀을 포함하는 전체 구조 상부에 베리어 메탈층(23)으로 사용될 제 1 Ti막(23a), 반응 조절막(23b) 및 제 2 Ti막(23c)을 순차적으로 형성한다. 이때, 반응 조절막(23b)으로는 TiN 또는 Ti-옥사이드가 사용될 수 있다.As shown in FIG. 2A, an interlayer insulating layer 22 is formed on the substrate on which the lower metal layer 21 is formed, and then a selected region is patterned to form a contact hole. Thereafter, the first Ti film 23a, the reaction control film 23b, and the second Ti film 23c to be used as the barrier metal layer 23 are sequentially formed on the entire structure including the contact hole. In this case, TiN or Ti-oxide may be used as the reaction control film 23b.

도 2(b)에 도시된 바와 같이, 암모니아(NH3) 또는 질소(N2) 분위기 하에서 RTP(Rapid Thermal Process ;RTP) 공정을 실시한다. 이때 콘택 기저부에서는 반응 조절막(23b) 하부의 제 1 Ti막(23a)의 Ti과 하부 금속층(21)의 금속이 반응하여 Ti-메탈 화합물층(23d)이 형성되며, 콘택 기저부 반응 조절층 상부의 제 2 티타늄막(23c)과 콘택 측벽 및 층간 절연막(22) 상의 제 1 및 제 2 Ti막(23a, 23c)은 RTP 공정에 의해 TiNx막(23e)으로 변화된다.As shown in FIG. 2 (b), a rapid thermal process (RTP) process is performed in an ammonia (NH 3 ) or nitrogen (N 2 ) atmosphere. At this time, the Ti-metal compound layer 23d is formed by reacting Ti of the first Ti film 23a under the reaction control film 23b with the metal of the lower metal layer 21 at the contact base, and forming the Ti-metal compound layer 23d on the contact bottom reaction control layer 23b. The first and second Ti films 23a and 23c on the second titanium film 23c and the contact sidewalls and the interlayer insulating film 22 are changed to the TiN x film 23e by the RTP process.

도 2(c)에 도시된 바와 같이, 베리어 메탈층(23)이 형성된 전체 구조 상부에 상부 금속층(24)을 형성한다. 이때, 상부 금속층(24)으로는 알루미늄(Al), 텅스텐(W) 및 구리(Cu) 중 어느 하나가 사용된다.As shown in FIG. 2 (c), the upper metal layer 24 is formed on the entire structure where the barrier metal layer 23 is formed. At this time, any one of aluminum (Al), tungsten (W) and copper (Cu) is used as the upper metal layer 24.

상술한 바와 같이 본 발명에 따르면, 금속 배선의 장벽층 또는 금속산 접착층으로 사용될 티타늄 또는 금속간 접착층으로 사용될 티타늄 박막 증착시, 하나의 티타늄 챔버에서 장벽층의 공정을 진행할 수 있고 소자의 콘택 저항을 안정화시킬 수 있다. 또한 공정 단순화에 의해 스루우-풋을 향상시킬 수 있고 고밀도의 티타늄나이트라이드를 형성하므로써 텅스텐-플러그 및 텅스텐 와이어링 공정을 안정화시킬 수 있어 소자의 수율이 향상되는 탁월한 효과가 있다.As described above, according to the present invention, when depositing a titanium thin film to be used as a barrier layer of a metal wiring or a titanium or an intermetallic adhesive layer to be used as a metal acid adhesive layer, the barrier layer may be processed in one titanium chamber and the contact resistance of the device may be improved. It can be stabilized. In addition, through-put can be improved by the process simplification, and the formation of high-density titanium nitride can stabilize the tungsten-plug and tungsten wiring process, thereby improving the yield of the device.

도 1(a) 내지 1(c)는 본 발명의 제 1 실시 예에 따른 반도체 소자의 금속 배선을 형서하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to form a metal wiring of a semiconductor device according to a first embodiment of the present invention.

도 2(a) 내지 2(c)는 본 발명의 제 2 실시 예에 따른 반도체 소자의 금속 배선을 형서하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to form a metal wiring of a semiconductor device according to a second embodiment of the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 : 실리콘 기판 21 : 하부 금속층11 silicon substrate 21 lower metal layer

12, 22 : 층간 절연막 13, 23 : 베리어 메탈층12, 22: interlayer insulation film 13, 23: barrier metal layer

13a, 23a : 제 1 티타늄막 13b, 23b : 반응 조절막13a, 23a: first titanium film 13b, 23b: reaction control film

13c, 23c : 제 2 티타늄막 13d : 티타늄실리사이드층13c and 23c: second titanium film 13d: titanium silicide layer

13e, 23e : 티타늄나이트라이드층 14 : 금속층13e, 23e: titanium nitride layer 14: metal layer

23d : 티타늄-메탈 화합물층 24 : 상부 금속층23d: titanium-metal compound layer 24: upper metal layer

Claims (1)

콘택홀이 형성된 기판이 제공되는 단계;Providing a substrate on which contact holes are formed; 상기 콘택홀을 포함한 전체 구조 상부에 제1 티타늄막을 형성하는 단계;Forming a first titanium film on the entire structure including the contact hole; 상기 제1 티타늄막 상에 반응 조절막으로 티타늄나이트라이드막 또는 티타늄옥사이드막을 형성하는 단계;Forming a titanium nitride film or a titanium oxide film as a reaction control film on the first titanium film; 상기 반응 조절막 상에 제2 티타늄막을 형성하는 단계;Forming a second titanium film on the reaction control film; 암모니아 또는 질소 분위기에서 급속 열처리 공정을 실시하여 상기 제1 티타늄막과 상기 기판 또는 상기 기판 상에 형성된 금속층을 반응시켜 상기 콘택홀의 기저부에 티타늄실리사이층 또는 티타늄 메탈 화합물층을 형성하는 동시에 상기 제2 티타늄막을 티타튬나이트라이드막으로 변화시키는 단계; 및A rapid heat treatment is performed in an ammonia or nitrogen atmosphere to react the first titanium film and the metal layer formed on the substrate or the substrate to form a titanium silicide layer or a titanium metal compound layer on the bottom of the contact hole. Changing the film to a titanium nitride film; And 상기 콘택홀이 매립되도록 금속층을 증착하는 단계를 포함하는 반도체 소자의 금속 배선 형성방법.And depositing a metal layer to fill the contact hole.
KR1019970079327A 1997-12-30 1997-12-30 Method for forming metal interconnection of semiconductor device to stably form barrier layer of metal interconnection by simple process and stabilize contact resistance KR100457409B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970079327A KR100457409B1 (en) 1997-12-30 1997-12-30 Method for forming metal interconnection of semiconductor device to stably form barrier layer of metal interconnection by simple process and stabilize contact resistance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970079327A KR100457409B1 (en) 1997-12-30 1997-12-30 Method for forming metal interconnection of semiconductor device to stably form barrier layer of metal interconnection by simple process and stabilize contact resistance

Publications (2)

Publication Number Publication Date
KR19990059130A KR19990059130A (en) 1999-07-26
KR100457409B1 true KR100457409B1 (en) 2005-02-23

Family

ID=37376844

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970079327A KR100457409B1 (en) 1997-12-30 1997-12-30 Method for forming metal interconnection of semiconductor device to stably form barrier layer of metal interconnection by simple process and stabilize contact resistance

Country Status (1)

Country Link
KR (1) KR100457409B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4998157A (en) * 1988-08-06 1991-03-05 Seiko Epson Corporation Ohmic contact to silicon substrate
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
JPH0661179A (en) * 1992-08-04 1994-03-04 Kawasaki Steel Corp Method of decreasing contact resistance
US5654235A (en) * 1994-08-18 1997-08-05 Oki Electric Industry Co., Ltd. Method of manufacturing contact structure using barrier metal

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4998157A (en) * 1988-08-06 1991-03-05 Seiko Epson Corporation Ohmic contact to silicon substrate
US5240880A (en) * 1992-05-05 1993-08-31 Zilog, Inc. Ti/TiN/Ti contact metallization
JPH0661179A (en) * 1992-08-04 1994-03-04 Kawasaki Steel Corp Method of decreasing contact resistance
US5654235A (en) * 1994-08-18 1997-08-05 Oki Electric Industry Co., Ltd. Method of manufacturing contact structure using barrier metal

Also Published As

Publication number Publication date
KR19990059130A (en) 1999-07-26

Similar Documents

Publication Publication Date Title
EP0279588B1 (en) Contact in a contact hole in a semiconductor and method of producing same
US6787468B2 (en) Method of fabricating metal lines in a semiconductor device
US6602782B2 (en) Methods for forming metal wiring layers and metal interconnects and metal interconnects formed thereby
JPH0777206B2 (en) Method for forming TiN barrier layer having selectively (111) crystal orientation
US5563097A (en) Method for fabricating semiconductor device
KR100290467B1 (en) Method of forming a metal barrier film in a semiconductor device
KR100559028B1 (en) Copper wiring formation method of semiconductor device
KR100457409B1 (en) Method for forming metal interconnection of semiconductor device to stably form barrier layer of metal interconnection by simple process and stabilize contact resistance
KR100560289B1 (en) Metal wiring formation method of semiconductor device
KR19980060526A (en) Metal wiring formation method of semiconductor device
KR100521051B1 (en) Method of forming a metal wiring in a semiconductor device
KR980011915A (en) Method of forming metal wiring
KR19990059074A (en) Metal wiring formation method of semiconductor device
KR100499401B1 (en) Method for forming metal interconnection layer of semiconductor device
KR100463236B1 (en) Barrier Metals of Semiconductor Devices
KR100525903B1 (en) Metal wiring formation method of semiconductor device
KR100477819B1 (en) Barrier Metal Film Formation Method of Semiconductor Device
KR19980057024A (en) Metal wiring formation method of semiconductor device
KR100342826B1 (en) Method for forming barrier metal layer of semiconductor device
KR0172770B1 (en) Method of forming barrier metal layer including silicide
KR100314273B1 (en) Diffusion Prevention Layer Formation Method
KR100593138B1 (en) Method of forming a metal wiring in a semiconductor device
KR100217916B1 (en) Forming method for barrier metal layer of semiconductor device
KR20000043053A (en) Metalization of semiconductor device
KR100277854B1 (en) Contact wiring formation method

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101025

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee