KR100434704B1 - Capacitor of semiconductor device and Method for fabricating the same - Google Patents
Capacitor of semiconductor device and Method for fabricating the same Download PDFInfo
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- KR100434704B1 KR100434704B1 KR10-2001-0087239A KR20010087239A KR100434704B1 KR 100434704 B1 KR100434704 B1 KR 100434704B1 KR 20010087239 A KR20010087239 A KR 20010087239A KR 100434704 B1 KR100434704 B1 KR 100434704B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000003990 capacitor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims description 42
- 229910017109 AlON Inorganic materials 0.000 claims abstract description 36
- 229910010282 TiON Inorganic materials 0.000 claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 claims abstract description 28
- 238000003860 storage Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims description 35
- 238000000137 annealing Methods 0.000 claims description 31
- 239000010408 film Substances 0.000 claims description 31
- 239000007789 gas Substances 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 239000012495 reaction gas Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 239000000376 reactant Substances 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims 4
- 239000010410 layer Substances 0.000 description 18
- 230000004888 barrier function Effects 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 238000009832 plasma treatment Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 캐패시터 및 그 제조방법에 관한 것으로, 본 발명에 따른 반도체소자의 캐패시터는, 반도체기판상에 형성된 스토리지노드전극; 상기 스토리지노드전극표면에 형성되고 AlON 및 TiON으로 구성된 유전체막; 상기 AlON 및 TiON 으로 구성된 유전체막 상에 형성된 상부전극;을 포함하여 구성되고, 본 발명에 따른 반도체소자의 캐패시터 제조방법은, 반도체기판상에 스토리지노드 전극을 형성하는 단계; 상기 스토리지노드전극표면에 AlON과 TiON 으로 구성된 유전체막을 형성하는 단계; 및 상기 AlON과 TiON으로 구성된 유전체막상에 상부 전극을 형성하는 단계를 포함하여 구성된다.The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same. The capacitor of the semiconductor device according to the present invention includes a storage node electrode formed on a semiconductor substrate; A dielectric film formed on the storage node electrode surface and composed of AlON and TiON; And an upper electrode formed on the dielectric film formed of the AlON and TiON. The method of manufacturing a capacitor of a semiconductor device according to the present invention includes: forming a storage node electrode on a semiconductor substrate; Forming a dielectric film composed of AlON and TiON on the storage node electrode surface; And forming an upper electrode on the dielectric film composed of AlON and TiON.
Description
본 발명은 반도체소자의 캐패시터 및 그 제조방법에 관한 것으로서, 보다 상세하게는 AlON의 우수한 누설전류 특성과 TiON의 높은 유전율을 이용하여 정전용량을 증가시키고 누설전류 특성을 개선시킬 수 있는 반도체소자의 캐패시터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same. More specifically, a capacitor of a semiconductor device capable of increasing capacitance and improving leakage current characteristics by using excellent leakage current characteristics of AlON and high dielectric constant of TiON. And to a method for producing the same.
소자가 고집적화됨에 따라 안정된 소자동작을 위해 필요한 셀당 캐패시터턴스는 변화가 없는 반면 캐패시터 셀 크기는 점점 줄어 들어 AlON 나 TiON의 단일 막으로는 캐패시터의 충분한 정전용량과 낮은 누설전류를 동시에 확보할 수 없다.As devices become more integrated, the capacitance per cell required for stable device operation remains unchanged, while the capacitor cell size gradually decreases, and a single layer of AlON or TiON cannot simultaneously ensure sufficient capacitance and low leakage current of the capacitor.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, AlON의 우수한 누설전류 특성과 TiON의 높은 유전율을 이용하여 정전용량을 증가시키고 누설전류 특성을 개선시킬 수 있는 반도체소자의 캐패시터 및 그 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the problems of the prior art, a capacitor of a semiconductor device that can increase the capacitance and improve the leakage current characteristics by using the excellent leakage current characteristics of AlON and high dielectric constant of TiON and The purpose is to provide a method of manufacturing the same.
도 1 내지 도 11은 본 발명의 일실시예에 따른 반도체소자의 캐패시터 및 그 제조방법을 설명하기 위한 공정별 단면도.1 to 11 are cross-sectional views illustrating processes of a capacitor of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.
도 12 내지 도 22는 본 발명의 다른 실시예에 따른 반도체소자의 캐패시터 및 그 제조방법을 설명하기 위한 공정별 단면도.12 to 22 are cross-sectional views illustrating processes of a capacitor and a method of manufacturing the same according to another embodiment of the present invention.
[도면부호의설명][Description of Drawing Reference]
11 : 반도체기판 13 : 비트라인11: semiconductor substrate 13: bit line
15 : 스페이서 17 : 층간절연막15 spacer 17 interlayer insulating film
19 : 장벽질화막 21 : 제1콘택홀19: barrier nitride film 21: the first contact hole
23 : 콘택플러그 25 : 캡산화막23 contact plug 25 cap oxide film
27 : 제2콘택홀 29 : 스토리지노드전극27: second contact hole 29: storage node electrode
31 : AlON 박막 33 : TiON 박막31: AlON thin film 33: TiON thin film
35 : TiN막 37 : 플레이트전극35 TiN film 37 plate electrode
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 캐패시터는, 반도체기판상에 형성된 스토리지노드전극; 상기 스토리지노드전극표면에 형성되고 AlON 및 TiON으로 구성된 유전체막; 상기 AlON 및 TiON으로 구성된 유전체막 상에 형성된 상부전극;을 포함하여 구성되는 것을 특징으로한다.A capacitor of a semiconductor device according to the present invention for achieving the above object, the storage node electrode formed on a semiconductor substrate; A dielectric film formed on the storage node electrode surface and composed of AlON and TiON; And an upper electrode formed on the dielectric film composed of AlON and TiON.
또한, 본 발명에 따른 반도체소자의 캐패시터 제조방법은, 반도체기판상에 스토리지노드전극을 형성하는 단계; 상기 스토리지노드전극표면에 AlON과 TiON 으로 구성된 유전체막을 형성하는 단계; 및 상기 AlON과 TiON으로 구성된 유전체막상에 상부전극을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.In addition, a method of manufacturing a capacitor of a semiconductor device according to the present invention includes the steps of forming a storage node electrode on a semiconductor substrate; Forming a dielectric film composed of AlON and TiON on the storage node electrode surface; And forming an upper electrode on the dielectric film composed of AlON and TiON.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 캐패시터 및 그 제조방법은 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a capacitor and a method of manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 11은 본 발명의 일실시예에 따른 반도체소자의 캐패시터 및 그 제조방법을 설명하기 위한 공정별 단면도이다.1 to 11 are cross-sectional views illustrating processes of a capacitor and a method of manufacturing the semiconductor device according to the embodiment of the present invention.
본 발명의 일실시예에 따른 반도체소자의 캐패시터 및 그 제조방법은, 도 1에 도시된 바와같이, 먼저 반도체기판(11)상에 비트라인(13)을 형성한후 상기 비트라인(13)측면에 스페이서(15)를 형성한다.As shown in FIG. 1, a capacitor of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention, first, the bit line 13 is formed on the semiconductor substrate 11, and then the side of the bit line 13 The spacer 15 is formed in the groove.
그다음, 도 2에 도시된 바와같이, 전체 결과물상에 층간절연막(17)과 장벽질화막(19)을 순차적으로 적층한다.Then, as shown in FIG. 2, the interlayer insulating film 17 and the barrier nitride film 19 are sequentially stacked on the entire resultant.
이어서, 도 3에 도시된 바와같이, 상기 층간절연막(17)과 장벽질화막(19)을 플러그 콘택을 형성하기 위한 마스크(미도시)를 이용하여 순차적으로 패터닝하여 상기 층간절연막(17) 및 장벽질화막(19)내에 상기 양측 스페이서(15)아래의 반도체기판(11)부분을 노출시키는 제1콘택홀(21)을 형성한다.Subsequently, as shown in FIG. 3, the interlayer insulating layer 17 and the barrier nitride layer 19 are sequentially patterned using a mask (not shown) for forming a plug contact, thereby forming the interlayer insulating layer 17 and the barrier nitride layer. A first contact hole 21 is formed in 19 to expose portions of the semiconductor substrate 11 under the spacers 15 on both sides.
그다음, 도 4에 도시된 바와같이, 상기 제1콘택홀(21)을 포함한 전체 결과물상에 제1콘택홀(21)을 매립하는 플러그 형성용 폴리실리콘층(미도시)을 증착한후 이를 과도하게 에치백하여 제1콘택홀(21)내에 콘택플러그(23a)를 형성한다.Next, as shown in FIG. 4, a polysilicon layer (not shown) for forming a plug filling the first contact hole 21 is deposited on the entire product including the first contact hole 21 and then transiently deposited. By etching back, the contact plug 23a is formed in the first contact hole 21.
이어서, 도 5에 도시된 바와같이, 상기 콘택플러그(23a)를 포함한 전체 결과물상에 실린더를 형성하기 위해 캡산화막(25)을 형성한다. 이때, 상기 캡산화막(25)은 5000 내지 20000 Å 두께로 증착한다. 또한, 상기 캡산화막(25) 증착후 ARC SiON 또는 하드마스크용 폴리실리콘을 증착할 수도 있다.Subsequently, as shown in FIG. 5, a cap oxide film 25 is formed to form a cylinder on the entire product including the contact plug 23a. At this time, the cap oxide film 25 is deposited to a thickness of 5000 to 20000 Å. In addition, ARC SiON or polysilicon for hard mask may be deposited after the cap oxide film 25 is deposited.
그다음, 도 6에 도시된 바와같이, 상기 캡산화막(25)을 스토리지노드 영역을 형성하기 위한 마스크(미도시)를 이용하여 선택적으로 패터닝하여 상기 콘택플러그(23a)상면 전체와 장벽질화막(19)의 일부분을 노출시키는 제2콘택홀(27)을 형성한다.Next, as shown in FIG. 6, the cap oxide layer 25 is selectively patterned using a mask (not shown) for forming a storage node region, so that the entire upper surface of the contact plug 23a and the barrier nitride layer 19 are formed. A second contact hole 27 exposing a portion of the second contact hole 27 is formed.
이어서, 도 7에 도시된 바와같이, 상기 제2콘택홀(27)을 포함한 전체 결과물상에 스토리지노드용 폴리실리콘층을 증착한후 상기 폴리실리콘층을 CMP 처리하여 스토리지노드(31)을 형성하고 잔류하는 캡산화막(25)을 제거한다.Subsequently, as shown in FIG. 7, after depositing the polysilicon layer for the storage node on the entire result including the second contact hole 27, the polysilicon layer is CMP-treated to form the storage node 31. The remaining cap oxide film 25 is removed.
그다음, 도 8에 도시된 바와같이, 상기 스토리지노드(31)를 포함한 전체 구조의 상면에 PECVD법으로 AlON 박막(33)을 50 내지 150 Å 두께로 증착한다.Next, as shown in FIG. 8, the AlON thin film 33 is deposited to a thickness of 50 to 150 Å on the upper surface of the entire structure including the storage node 31 by PECVD.
이때, 상기 AlON 박막(33)을 증착하는 조건에 대해 설명하면 다음과 같다.In this case, the conditions for depositing the AlON thin film 33 will be described as follows.
먼저, 웨이퍼 온도를 200 내지 450 ℃로 유지하고, 반응로의 압력을 0.1 torr 내지 1 torr 로 유지하며 R.F. 파워는 10 내지 500 W로 유지한다.First, the wafer temperature is maintained at 200 to 450 ° C., the pressure in the reactor is maintained at 0.1 torr to 1 torr, and R.F. Power is maintained at 10 to 500 W.
또한, (CH3)3Al을 소오스로 하여 기화시키고, 반응물질로는 H2O 및 NH3를 사용한다. 이때, 상기 반응물질인 H2O 및 NH3의 양은 각각 10 sccm 내지 500 sccm, 10 sccm 내지 500 sccm 으로 조절한다.In addition, (CH 3 ) 3 Al is vaporized using a source, and H 2 O and NH 3 are used as reactants. At this time, the amount of the reactant H 2 O and NH 3 is adjusted to 10 sccm to 500 sccm, 10 sccm to 500 sccm, respectively.
이어서, 도 9에 도시된 바와같이, 후속 열공정으로 탄소 및 불순물 제거와N2함량을 증가시키기 위해 N2O 플라즈마 아닐링공정을 실시한다.Subsequently, as shown in FIG. 9, a N 2 O plasma annealing process is performed in order to remove carbon and impurities and increase N 2 content in a subsequent thermal process.
이때, 상기 플라즈마 아닐링 공정은 다음과 같은 조건하에서 실시한다.At this time, the plasma annealing process is carried out under the following conditions.
먼저, RTA (rapid Thermal Anneal) 시의 온도는 700 내지 850 ℃로 유지하고, N2O 가스의 양을 1 slm 내지 10 slm으로 유지하며, 아닐링시간은 60 내지 180 초로 유지한다.First, the temperature during rapid thermal annealing (RTA) is maintained at 700 to 850 ° C., the amount of N 2 O gas is maintained at 1 slm to 10 slm, and the annealing time is maintained at 60 to 180 seconds.
그다음, 도 10에 도시된 바와같이, 추가로 PECVD법으로 TiON 박막(35)을 증착한다.Then, as shown in Fig. 10, a TiON thin film 35 is further deposited by PECVD.
이때, 상기 TiON 박막(35) 증착공정은 다음과 같은 조건하에서 실시한다.At this time, the TiON thin film 35 is deposited under the following conditions.
먼저, TiCl4소오스의 온도는 170 내지 190 ℃로 유지하고, 챔버압력는 0.1 torr 내지 1.2 torr 로 유지하며, 기판온도는 300 내지 500 ℃ 온도로 유지한다.First, the temperature of the TiCl 4 source is maintained at 170 to 190 ° C, the chamber pressure is maintained at 0.1 torr to 1.2 torr, and the substrate temperature is maintained at 300 to 500 ° C.
또한, R.F. 파워는 10 내지 500 W로 유지하고, 반응가스인 NH3가스의 양을 10 sccm 내지 100 sccm으로 하는 한편, 반응가스인 O2가스의 양은 10 내지 100 sccm으로 한다.In addition, RF power is maintained at 10 to 500 W, the amount of NH 3 gas that is the reaction gas is 10 sccm to 100 sccm, while the amount of O 2 gas that is the reaction gas is 10 to 100 sccm.
이어서, 도면에는 도시하지 않았지만, 상기 TiON 박막(35)내의 탄소(C)의 제거 및 N2함량을 증가시키기 위해 퍼니스 진공 N2아닐링공정 또는 RTP공정을 실시한다.Subsequently, although not shown in the drawing, a furnace vacuum N 2 annealing process or an RTP process is performed to remove carbon (C) in the TiON thin film 35 and increase the N 2 content.
이때, 상기 아닐링공정은 다음과 같은 공정조건하에서 실시한다.At this time, the annealing process is carried out under the following process conditions.
먼저, 퍼니스 진공 아닐링시의 온도는 500 내지 600 ℃로 유지하고, 아닐링시간은 5분 내지 60분으로 유지한다.First, the temperature during the furnace vacuum annealing is maintained at 500 to 600 ℃, the annealing time is maintained at 5 to 60 minutes.
그다음, 도 11에 도시된 바와같이, 상기 TiON 박막(35)상에 TiN 박막(37)과 플레이트전극(39)을 순차적으로 증착한다. 이때, 상기 TiN 박막(37)은 필요에 따라 선택적으로 형성 또는 생략할 수도 있다.Next, as shown in FIG. 11, the TiN thin film 37 and the plate electrode 39 are sequentially deposited on the TiON thin film 35. In this case, the TiN thin film 37 may be selectively formed or omitted as necessary.
한편, 본 발명의 다른 실시예에 따른 반도체소자의 캐패시터 및 그 제조방법에 대해 첨부된 도면을 참조하여 설명하면 다음과 같다.Meanwhile, a capacitor and a manufacturing method of a semiconductor device according to another embodiment of the present invention will be described with reference to the accompanying drawings.
도 12 내지 도 22는 본 발명의 다른 실시예에 따른 반도체소자의 캐패시터 및 그 제조방법 을 설명하기 위한 공정별 단면도이다.12 to 22 are cross-sectional views illustrating processes of a capacitor and a method of manufacturing the same according to another embodiment of the present invention.
본 발명의 다른 실시예에 따른 반도체소자의 캐패시터 및 그 제조방법은, 도 12에 도시된 바와같이, 먼저 반도체기판(51)상에 비트라인(53)을 형성한후 상기 비트라인 (53) 측면에 스페이서(55)를 형성한다.According to another embodiment of the present invention, a capacitor of a semiconductor device and a method of manufacturing the same, as shown in FIG. 12, first form a bit line 53 on a semiconductor substrate 51, and then laterally form the bit line 53. The spacer 55 is formed in the groove.
그다음, 도 13에 도시된 바와같이, 전체 결과물상에 층간절연막(57)과 장벽질화막(59)을 순차적으로 적층한다.Then, as shown in FIG. 13, the interlayer insulating film 57 and the barrier nitride film 59 are sequentially stacked on the entire resultant.
이어서, 도 14에 도시된 바와같이, 상기 층간절연막(57)과 장벽질화막(59)을 플러그 콘택을 형성하기 위한 마스크(미도시)를 이용하여 순차적으로 패터닝하여 상기 층간절연막(57) 및 장벽질화막(59)내에 상기 양측 스페이서(55)아래의 반도체기판(51)부분을 노출시키는 제1콘택홀(61)을 형성한다.Subsequently, as shown in FIG. 14, the interlayer insulating layer 57 and the barrier nitride layer 59 are sequentially patterned using a mask (not shown) for forming a plug contact, thereby forming the interlayer insulating layer 57 and the barrier nitride layer. A first contact hole 61 is formed in the 59 to expose a portion of the semiconductor substrate 51 below the spacer 55 on both sides.
그다음, 도 15에 도시된 바와같이, 상기 제1콘택홀(61)을 포함한 전체 결과물상에 제1콘택홀(61)을 매립하는 플러그 형성용 폴리실리콘층(미도시)을 증착한후 이를 과도하게 에치백하여 제1콘택홀(63)내에 콘택플러그(63)를 형성한다.Then, as illustrated in FIG. 15, a polysilicon layer (not shown) for forming a plug filling the first contact hole 61 is deposited on the entire product including the first contact hole 61 and then transiently deposited. Etch back to form a contact plug 63 in the first contact hole (63).
이어서, 도 16에 도시된 바와같이, 상기 콘택플러그(63)를 포함한 전체 결과물상에 실린더를 형성하기 위해 캡산화막(65)을 순차적으로 적층한다. 이때, 상기 캡산화막(65)은 5000 내지 20000 Å 두께로 증착한다. 또한, 상기 캡산화막(65) 증착후 ARC SiON 또는 하드마스크용 폴리실리콘을 증착할 수도 있다.Subsequently, as shown in FIG. 16, the cap oxide film 65 is sequentially stacked to form a cylinder on the entire product including the contact plug 63. At this time, the cap oxide film 65 is deposited to a thickness of 5000 to 20000 Å. In addition, after the cap oxide film 65 is deposited, ARC SiON or polysilicon for hard mask may be deposited.
그다음, 도 17에 도시된 바와같이, 상기 캡산화막(65)을 스토리지노드 영역을 형성하기 위한 마스크(미도시)를 이용하여 선택적으로 패터닝하여 상기 콘택플러그(63a)상면 전체와 장벽질화막(59)의 일부분을 노출시키는 제2콘택홀(67)을 형성한다.Next, as shown in FIG. 17, the cap oxide layer 65 is selectively patterned using a mask (not shown) for forming a storage node region, so that the entire upper surface of the contact plug 63a and the barrier nitride layer 59 are formed. A second contact hole 67 exposing a portion of the second contact hole 67 is formed.
이어서, 도 18에 도시된 바와같이, 상기 제2콘택홀(67)을 포함한 전체 결과물상에 스토리지노드용 폴리실리콘층을 증착한후 상기 폴리실리콘층을 CMP 처리하여 스토리지노드(69)을 형성하고 잔류하는 캡산화막(65)을 제거한다.18, after depositing a polysilicon layer for a storage node on the entire product including the second contact hole 67, the polysilicon layer is CMP-treated to form a storage node 69. The remaining cap oxide film 65 is removed.
그다음, 도면에는 도시하지 않았지만, 상기 스토리지노드(69)표면을 NH3플라즈마 처리하여 질화화(nitridation)시킨다.Next, although not shown, the surface of the storage node 69 is nitrided by NH 3 plasma treatment.
이때, 상기 NH3플라즈마 처리공정은 다음과 같은 공정조건하에서 진행한다.At this time, the NH 3 plasma treatment process is performed under the following process conditions.
먼저, 플라즈마 처리시 웨이퍼 온도는 저온인 300 내지 550 ℃로 유지하고, 반응챔버의 압력은 0.1 torr 내지 1.2 torr 로 유지하며, 반응가스인 NH3의 양은 각각 10 sccm 내지 500 sccm로 유지하는 한편 R.F. 파워는 10 내지 500 W로 10 내지 600 초동안 여기시킨다.First, during the plasma treatment, the wafer temperature is maintained at a low temperature of 300 to 550 ° C., the pressure of the reaction chamber is maintained at 0.1 torr to 1.2 torr, and the amount of NH 3 , which is a reaction gas, is maintained at 10 sccm to 500 sccm, respectively, while RF is applied. The power is excited at 10-500 W for 10-600 seconds.
이어서, 도 19에 도시된 바와같이, 추가로 PECVD법으로 TiON 박막(71)을 증착한다.Subsequently, as shown in FIG. 19, the TiON thin film 71 is further deposited by PECVD.
이때, 상기 TiON 박막(71) 증착공정은 다음과 같은 조건하에서 실시한다.At this time, the TiON thin film 71 is deposited under the following conditions.
먼저, TiCl4소오스의 온도는 170 내지 190 ℃로 유지하고, 챔버압력는 0.1 torr 내지 1.2 torr 로 유지하며, 기판온도는 300 내지 500 ℃ 온도로 유지한다.First, the temperature of the TiCl 4 source is maintained at 170 to 190 ° C, the chamber pressure is maintained at 0.1 torr to 1.2 torr, and the substrate temperature is maintained at 300 to 500 ° C.
또한, R.F. 파워는 10 내지 500 W로 유지하고, 반응가스인 NH3가스의 양을 10 sccm 내지 100 sccm으로 하는 한편, 반응가스인 O2가스의 양은 10 내지 100 sccm으로 한다.In addition, RF power is maintained at 10 to 500 W, the amount of NH 3 gas that is the reaction gas is 10 sccm to 100 sccm, while the amount of O 2 gas that is the reaction gas is 10 to 100 sccm.
그다음, 도 20에 도시된 바와같이, 상기 TiON 박막(71)를 포함한 전체 구조의 상면에 PECVD법으로 AlON 박막(73)을 50 내지 150 Å 두께로 증착한다.Next, as shown in FIG. 20, the AlON thin film 73 is deposited to a thickness of 50 to 150 Å on the upper surface of the entire structure including the TiON thin film 71 by PECVD.
이때, 상기 AlON 박막(73)을 증착하는 조건에 대해 설명하면 다음과 같다.In this case, the conditions for depositing the AlON thin film 73 will be described below.
먼저, 웨이퍼 온도를 200 내지 450 ℃로 유지하고, 반응로의 압력을 0.1 torr 내지 1 torr 로 유지하며 R.F. 파워는 10 내지 500 W로 유지한다.First, the wafer temperature is maintained at 200 to 450 ° C., the pressure in the reactor is maintained at 0.1 torr to 1 torr, and R.F. Power is maintained at 10 to 500 W.
또한, (CH3)3Al을 소오스로 하여 기화시키고, 반응물질로는 H2O 및 NH3를 사용한다. 이때, 상기 반응물질인 H2O 및 NH3의 양은 각각 10 sccm 내지 500 sccm, 10 sccm 내지 500 sccm 으로 조절한다.In addition, (CH 3 ) 3 Al is vaporized using a source, and H 2 O and NH 3 are used as reactants. At this time, the amount of the reactant H 2 O and NH 3 is adjusted to 10 sccm to 500 sccm, 10 sccm to 500 sccm, respectively.
이어서, 도 21에 도시된 바와같이, 후속 열공정으로 AlON 박막의 탄소 및 불순물제거 및 N2함량을 증가시키기 위해 N2O 플라즈마 아닐링공정을 실시한다.Subsequently, as shown in FIG. 21, an N 2 O plasma annealing process is performed to increase carbon and impurity removal and N 2 content of the AlON thin film in a subsequent thermal process.
이때, 상기 플라즈마 아닐링 공정은 다음과 같은 조건하에서 실시한다.At this time, the plasma annealing process is carried out under the following conditions.
먼저, RTA (rapid Thermal Anneal) 시의 온도는 700 내지 850 ℃로 유지하고, N2O 가스의 양을 1 slm 내지 10 slm으로 유지하며, 아닐링시간은 60 내지 180 초로 유지한다.First, the temperature during rapid thermal annealing (RTA) is maintained at 700 to 850 ° C., the amount of N 2 O gas is maintained at 1 slm to 10 slm, and the annealing time is maintained at 60 to 180 seconds.
그다음, 추가로 AlON 박막의 결정화 및 증가된 N2함량을 유지시키기 위해 퍼니스 진공아닐링공정을 실시한다.A furnace vacuum annealing process is then carried out to further crystallize the AlON thin film and maintain an increased N 2 content.
이때, 상기 퍼니스 진공 아닐링 공정은 다음과 같은 조건하에서 실시한다.At this time, the furnace vacuum annealing process is carried out under the following conditions.
먼저, 퍼니스 진공아닐링시의 아닐링 가스로는 N2를 사용하고, 아닐링시의 온도는 600 내지 850 ℃로 유지하며, 아닐링시간은 5분 내지 60분동안 유지한다.First, N 2 is used as the annealing gas during the furnace vacuum annealing, the temperature during the annealing is maintained at 600 to 850 ° C., and the annealing time is maintained for 5 to 60 minutes.
그다음, 도 22에 도시된 바와같이, 상기 AlON 박막(75)상에 TiN 박막(77)과 플레이트전극(79)을 순차적으로 증착한다. 이때, 상기 TiN 박막(77)은 필요에 따라 선택적으로 형성 또는 생략할 수도 있다.Next, as shown in FIG. 22, the TiN thin film 77 and the plate electrode 79 are sequentially deposited on the AlON thin film 75. In this case, the TiN thin film 77 may be selectively formed or omitted as necessary.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 캐패시터 및 그 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the capacitor and the method of manufacturing the semiconductor device according to the present invention have the following effects.
본 발명에 의하면, AlON의 우수한 누설전류 특성과 TiON의 높은 유전율을 이용하여 AlON/TiON 캐패시터를 형성하므로써 높은 정전용량과 낮은 누설전류 특성을 동시에 확보할 수 있으며, TiN 공정을 생략할 수 있으므로 공정단순화가 가능하다.According to the present invention, by forming an AlON / TiON capacitor using the excellent leakage current characteristics of AlON and the high dielectric constant of TiON, high capacitance and low leakage current characteristics can be secured simultaneously, and the TiN process can be omitted, thus simplifying the process. Is possible.
또한, 본 발명에 따른 캐패시터 제조방법은, 256 M 이상의 하부전극이 폴리실리콘을 사용한 실린더 및 오목형 구조의 캐패시터 제조방법에 적용이 가능하다.In addition, the capacitor manufacturing method according to the present invention is applicable to a capacitor manufacturing method of a cylinder and a concave structure in which a lower electrode of 256 M or more uses polysilicon.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (17)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5688724A (en) * | 1992-07-02 | 1997-11-18 | National Semiconductor Corporation | Method of providing a dielectric structure for semiconductor devices |
| KR20010004993A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Method of forming a capacitor in a semiconductor |
| KR20020049487A (en) * | 2000-12-19 | 2002-06-26 | 박종섭 | Method for forming of capacitor the cell used high-integrated DRAM |
| KR20020049488A (en) * | 2000-12-19 | 2002-06-26 | 박종섭 | Method for forming of capacitor the cell used high-integrated DRAM |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5688724A (en) * | 1992-07-02 | 1997-11-18 | National Semiconductor Corporation | Method of providing a dielectric structure for semiconductor devices |
| KR20010004993A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Method of forming a capacitor in a semiconductor |
| KR20020049487A (en) * | 2000-12-19 | 2002-06-26 | 박종섭 | Method for forming of capacitor the cell used high-integrated DRAM |
| KR20020049488A (en) * | 2000-12-19 | 2002-06-26 | 박종섭 | Method for forming of capacitor the cell used high-integrated DRAM |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100750558B1 (en) | 2004-12-31 | 2007-08-20 | 삼성전자주식회사 | Method of manufacturing a capacitor of semiconductor device |
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