KR100361763B1 - Method for manufacturing isolation layer of semiconductor device - Google Patents
Method for manufacturing isolation layer of semiconductor device Download PDFInfo
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- KR100361763B1 KR100361763B1 KR1019950054955A KR19950054955A KR100361763B1 KR 100361763 B1 KR100361763 B1 KR 100361763B1 KR 1019950054955 A KR1019950054955 A KR 1019950054955A KR 19950054955 A KR19950054955 A KR 19950054955A KR 100361763 B1 KR100361763 B1 KR 100361763B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000002955 isolation Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 35
- 125000006850 spacer group Chemical group 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000368 destabilizing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 특히 구조 공정을 응용한 소자분리막 제조방법에있어서, 활성영역과 소자분리영역이 만나는 부분의 필드산화막 끝단의 높이가 활성영역 아래쪽으로 함몰되는 것을 방지하므로써, 소자의 신뢰성을 향상할 수 있는 반도체소자의 소자분리막 제조방법을 제공함에 그목적이 있다.The present invention relates to a method of manufacturing a device isolation film of a semiconductor device, in particular, in a device isolation film manufacturing method using a structural process, the height of the end of the field oxide film at the portion where the active region and the device isolation region meet the recessed portion below the active region The purpose of the present invention is to provide a method for manufacturing a device isolation film of a semiconductor device, which can improve the reliability of the device.
일반적으로, 반도체소자는 트랜지스터나 캐패시터등과 같은 소자들이 형성되는 활성영역과, 상기 소자들의 동작을 서로 방해하지 않도록 활성영역들을 분리하는 소자분리영역으로 구성되어 있다.In general, a semiconductor device is composed of an active region where elements such as a transistor or a capacitor are formed, and an element isolation region that separates the active regions so as not to interfere with each other.
최근 반도체소자의 고집적화 추세에 따라 반도체소자에서 많은 면적을 차지하는 소자분리영역의 면적을 감소시키려는 노력이 꾸준히 진행되고 있다.Recently, with the trend toward higher integration of semiconductor devices, efforts have been made to reduce the area of device isolation regions, which occupy a large area in semiconductor devices.
이러한 소자분리영역의 제조방법으로는 질화막패턴을 마스크로 하여 실리콘 반도체기판을 열산화시키는 통상의 로코스 방법이나, 반도체기판에 트랜치를 형성하고 이를 절연물질로 메우는 트랜치(trench)분리등의 방법이 사용되고 있다.As a method of manufacturing the device isolation region, a conventional LOCOS method of thermally oxidizing a silicon semiconductor substrate using a nitride film pattern as a mask, or a trench isolation method of forming a trench in a semiconductor substrate and filling it with an insulating material is used. It is used.
PBL 공정은 LOCOS 공정의 응용 기술로 질화막과 패드산화막의 사이에 폴리실리콘층을 형성하므로써, 소자분리막의 버즈빅(bird's beak)을 감소하며, 반도체기판의 스트레스를 완화하였다.In the PBL process, a polysilicon layer is formed between the nitride film and the pad oxide film as an application technology of the LOCOS process, thereby reducing bird's beak of the device isolation film and relieving stress of the semiconductor substrate.
소자와 소자를 전기적으로 분리시키는 소자분리막은 주로 LOCOS공정으로 형성하였다. 반도체소자가 고집적화됨에 따라 상기 LOCOS를 응용하는 기술중 반도체기판의 상부에 스페이서를 형성하고, 상기 스페이서를 마스크로 반도체기판을 일정깊이로 식각하여 트렌치를 형성한 후 산화시키는 방법들이 적용되고 있다.The device isolation film that electrically separates the device from the device was mainly formed by a LOCOS process. As semiconductor devices are highly integrated, a method of forming a trench on a semiconductor substrate, etching the semiconductor substrate to a predetermined depth using the spacer as a mask, and then oxidizing the LOCOS is applied.
반도체기판을 일정깊이로 식각하면, 소자분리막이 반도체기판 아래쪽으로 더 깊이 들어가 형성되므로 전기적으로 소자분리역할을 높일 수 있으며, 소자분리공정이 끝난 후 평탄화도 양호해지는 장점이 있다.If the semiconductor substrate is etched to a certain depth, the device isolation film is formed deeper into the bottom of the semiconductor substrate, thereby increasing the device isolation role electrically, and after the device separation process is finished, the planarization is also good.
제1A도 내지 제1C도는 종래의 LOCOS 공정을 응용한 반도체소자의 소자분리막의 제조 공정도이다.1A to 1C are manufacturing process diagrams of a device isolation film of a semiconductor device using a conventional LOCOS process.
제1A도를 참조하면, 반도체기판(1)의 상부를 열산화하여 패드산화막(2)을 형성하고, 상기 패드산화막(2) 상부에 질화막(3)을 증착한다.Referring to FIG. 1A, a pad oxide film 2 is formed by thermally oxidizing an upper portion of the semiconductor substrate 1, and a nitride film 3 is deposited on the pad oxide film 2.
소자분리용 식각마스크를 사용하여 상기 반도체기판(1)에서 소자분리막영역으로 예정되어 있는 부분을 노출시키는 질화막(3)패턴 및 패드산화막(2)패턴을 형성한다.An etching mask for forming an isolation layer is used to form a nitride layer 3 pattern and a pad oxide layer 2 pattern exposing a portion of the semiconductor substrate 1 to be formed as an isolation region.
상기 구조의 전표면에 질화막을 증착한 후 전면식각하여 상기 질화막(3)패턴과 패드산화막(2)패턴의 측벽에 스페이서(6)를 형성한다.After the nitride film is deposited on the entire surface of the structure, the entire surface is etched to form spacers 6 on sidewalls of the nitride film 3 pattern and the pad oxide film 2 pattern.
이때, 상기 스페이서(6)의 역할은 버즈빅이 생기는 만큼의 공간을 보상하여 활성영역의 손실을 막기 위한 것이다.At this time, the role of the spacer 6 is to compensate for the space as much as the buzz big to prevent the loss of the active region.
제1B도를 참조하면, 상기 질화막(3)패턴과 스페이서(6)에 의해 노출된 반도체기판(1)을 식각하여 홈을 형성한다.Referring to FIG. 1B, a groove is formed by etching the semiconductor substrate 1 exposed by the nitride film 3 pattern and the spacer 6.
제1C도를 참조하면, 상기 홈에 의해 노출되어 있는 반도체기판(1)을 열산화하여 필드산화막(7)을 형성한다.Referring to FIG. 1C, the field oxide film 7 is formed by thermally oxidizing the semiconductor substrate 1 exposed by the groove.
그러나, 상기 종래기술에 따른 반도체소자의 소자분리막은 상기 질화막 스페이서의 두께가 두꺼워서 활성영역과 소자분리영역이 만나는 지점의 필드산화막이 활성영역의 아래쪽으로 함몰되어 형성되므로, 이후에 형성될 게이트산화막이 얇아지는 문제가 있으며, 이후에 형성될 트렌지스터의 문턱전압이 일정하지 않는 문제점이 있으며, 이후에 형성될 게이트 폴리실리콘을 패턴닝(patterning) 하여 식각할 때, 필드산화막의 함몰된 에지(edge) 부위에 남은 폴리실리콘으로 인하여 모스전계효과 트랜지스터의 동작을 불안정하게 하는 문제점이 있다.However, the device isolation film of the semiconductor device according to the related art has a thick thickness of the nitride spacer, so that the field oxide film at the point where the active region and the device isolation region meet is recessed below the active region, so that the gate oxide film to be formed later is There is a problem of thinning, there is a problem that the threshold voltage of the transistor to be formed later is not constant, and when etching by patterning the gate polysilicon to be formed later, the recessed edge portion of the field oxide film Due to the remaining polysilicon, there is a problem of destabilizing the operation of the MOS field effect transistor.
따라서, 본 발명의 목적은 상기 문제점을 해결하기 위한 것으로, 본 발명은 LOCOS(Local Oxidation of Silcon) 공정을 응용한 소자분리막 제조방법에있어서, 소자분리영역을 노출하는 질화막패턴과, 패드산화막제1패턴을 형성하고, 상기 패드산화막제1패턴을 측벽에서 활성영역쪽으로 일정부분식각하여 패드산화막제2패턴을 형성하고, 상기 질화막패턴과, 패드산화막제2패턴의 측벽과 ⊥자 형태의 산화질화막패턴과 스페이서 형태의 산화막으로 구성된 스페이서를 형성하므로써, 필드산화막 형성시 산화막의 측면확산을 방지하므로써, 소자의 신뢰성을 향상할 수 있는 반도체소자의 소자분리막 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to solve the above problems, and the present invention provides a nitride film pattern for exposing a device isolation region and a pad oxide film 1 in a device isolation film manufacturing method using a Local Oxidation of Silcon (LOCOS) process. A pattern is formed, and the pad oxide film first pattern is partially etched from the sidewall toward the active region to form a pad oxide film second pattern, the nitride film pattern, the sidewall of the pad oxide film second pattern, and a U-shaped oxynitride pattern It is an object of the present invention to provide a device isolation film manufacturing method of a semiconductor device that can improve the reliability of the device by forming a spacer consisting of a spacer oxide and a spacer oxide, thereby preventing side diffusion of the oxide film when forming the field oxide film.
상기 목적을 달성하기 위한 본 발명의 반도체소자의 소자분리막 제조방법은 반도체기판의 상부에 소자분리영역을 노출시키는 패드산화막패턴과 질화막패턴을 형성하는 단계와,The method of manufacturing a device isolation film of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a pad oxide film pattern and a nitride film pattern to expose the device isolation region on the semiconductor substrate;
상기 패드산화막패턴을 언더 컷하는 단계와,Undercutting the pad oxide film pattern;
상기 구조의 전 표면에 산화질화막과, 산화막을 차례로 형성하는 단계와,Sequentially forming an oxynitride film and an oxide film on the entire surface of the structure;
상기 산화막과 산화질화막을 전면식각하여 상기 질화막패턴과 패드산화막패턴의 측벽에 스페이서를 형성하는 단계와,Forming a spacer on sidewalls of the nitride layer pattern and the pad oxide layer pattern by etching the oxide layer and the oxynitride layer on the entire surface;
상기 노출된 반도체기판과 스페이서를 열산화하여 필드산화막을 형성하는 단계와,Thermally oxidizing the exposed semiconductor substrate and the spacer to form a field oxide film;
상기 질화막패턴과 패드산화막패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.And removing the nitride film pattern and the pad oxide film pattern.
이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제2A도 내지 제2H도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조 공정도이다.2A to 2H are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device according to an exemplary embodiment of the present invention.
제2A도를 참조하면, 반도체기판(1)을 열산화하여 100 내지 300 Å 두께의 패드산화막(2)을 형성하고, 상기 패드산화막(2) 상부에 화학기상증착법으로 1500 내지 2500 Å 두께의 질화막(3)을 형성한다.Referring to FIG. 2A, the semiconductor substrate 1 is thermally oxidized to form a pad oxide film 2 having a thickness of 100 to 300 m 3, and a nitride film having a thickness of 1500 to 2500 m 3 by chemical vapor deposition on the pad oxide layer 2. (3) is formed.
그 다음, 상기 구조의 전 표면에 감광막을 도포한 후 노광마스크를 이용하여 소자분리영역은 노출시키고, 활성영역은 감싸는 감광막패턴(도시안함)을 형성한다.Then, after the photoresist is coated on the entire surface of the structure, the device isolation region is exposed using an exposure mask, and a photoresist pattern (not shown) is formed to surround the active region.
제2B도를 참조하면, 상기 감광맥패턴을 마스크로 상기 질화막(3)과, 패드산화막(2)을 건식식각하여 질화막(3)패턴과, 패드산화막(2)제1패턴을 형성한다.Referring to FIG. 2B, the nitride film 3 and the pad oxide film 2 are dry-etched using the photosensitive vein pattern as a mask to form the nitride film 3 pattern and the pad oxide film 2 first pattern.
제2C도를 참조하면, 묽은 불산용액을 사용하여 상기 제1 패드산화막(2)패턴을 측벽으로 부터 활성영역쪽으로 100 내지 500 Å 정도 언더 컷(Under cut)하여 패드산화막(2)제2패턴을 형성한다.Referring to FIG. 2C, the second pattern of the pad oxide film 2 is undercut by using a thin hydrofluoric acid solution and undercutting the first pad oxide film 2 pattern from the sidewall to the active region by about 100 to 500 mm. Form.
제2D도를 참조하면, 상기 구조의 전 표면에 화학기상증착법으로 60 내지 120 Å 이하의 산화질화막(4)을 형성한다.Referring to FIG. 2D, an oxynitride film 4 of 60 to 120 kPa or less is formed on the entire surface of the structure by chemical vapor deposition.
이때, 상기 산화질화막(4)은 600 내지 750℃의 온도에서, DCS, NH3의 조성비를 1 : 3.0 내지 1 : 3.5 로 하고, 질소의 유량을 40sccm으로하고, 증착압력을 200 내지 500 m Torr 하여 증착한다.At this time, the oxynitride film 4 at a temperature of 600 to 750 ℃, the composition ratio of DCS, NH 3 is 1: 3.0 to 1: 3.5, the flow rate of nitrogen is 40 sccm, the deposition pressure is 200 to 500 m Torr By deposition.
그 다음, 상기 구조의 전 표면에 화학기상증착법으로 200 내지 1000 Å 두께의 산화막(5)을 형성한다.Then, an oxide film 5 of 200 to 1000 Å thickness is formed on the entire surface of the structure by chemical vapor deposition.
제2E도를 참조하면, 상기 질화산화막(4)과, 산화막(5)을 차례로 이방성식각하여 상기 질화막(3)패턴과, 패드산화막(2)제2패턴의 측벽에 산화질화막(4)패턴과, 산화막(5)패턴으로 형성된 스페이서(6)를 형성한다.Referring to FIG. 2E, the nitride oxide film 4 and the oxide film 5 are anisotropically etched one by one to form sidewalls of the nitride film 3 pattern and the pad oxide film 2 pattern. The spacer 6 formed of the oxide film 5 pattern is formed.
상기 산화질화막(4)패턴은 ⊥자 모양으로 상기 질화막(3)패턴, 패드산화막 (2)제2패턴, 반도체기판(1)에 접촉하고, 상기 산화막(5)패턴은 스페이서 모양으로 상기 산화질화막(4)패턴으로 접촉한다.The oxynitride layer 4 pattern has a U-shape in contact with the nitride layer 3 pattern, the pad oxide layer 2, the second pattern, and the semiconductor substrate 1, and the oxide layer 5 pattern has a spacer shape. (4) Contact with a pattern.
참고로, 상기 스페이서(6)를 형성한 후, 상기 스페이서(6)를 마스크로 반도체기판(1)을 일정깊이 식각할 수도 있다.For reference, after the spacer 6 is formed, the semiconductor substrate 1 may be etched to a certain depth using the spacer 6 as a mask.
제2F도를 참조하면, 노출된 반도체기판(1)을 1100 내지 1150℃ 온도에서 열산화하여 2500 내지 4000 Å 두께의 필드산화막(7)을 형성하되, 상기 스페이서(6)까지 열산화하여 필드산화막(7)을 형성한다.Referring to FIG. 2F, the exposed semiconductor substrate 1 is thermally oxidized at a temperature of 1100 to 1150 ° C. to form a field oxide film 7 having a thickness of 2500 to 4000 kPa, and thermally oxidized to the spacer 6 to form a field oxide film. (7) is formed.
이때, 상기 스페이서(6)는 반도체기판(1)의 산화로 인한 하부로 부터의 부피 팽창을 억제하여 필드산화막의 측면확산을 방지한다.At this time, the spacer 6 prevents the volume expansion from the lower portion due to the oxidation of the semiconductor substrate 1 to prevent the side diffusion of the field oxide film.
또, 상기 산화막(5)패턴을 통하여 상기 산화질화막(4)패턴도 동시에 산화하되, 상기 패드산화막(2)제2패턴과 접한 일부분에만 산화질화막(4)패턴이 일정량 남아 있다.In addition, the oxynitride film 4 pattern is oxidized at the same time through the oxide film 5 pattern, but a certain amount of the oxynitride film 4 pattern remains only in a portion in contact with the second pattern of the pad oxide film 2.
제2G도를 참조하면, BOE ( Buffer Oxide Etchant )나 불산용액을 사용하여 상기 필드산화막(7) 형성시 질화막(3)패턴의 표면에 얇게 형성된 산화막(도시안함)을 제거한다.Referring to FIG. 2G, an oxide film (not shown) thinly formed on the surface of the nitride film 3 pattern is removed when the field oxide film 7 is formed using a buffer oxide buffer (BOE) or hydrofluoric acid solution.
그 다음, 인산용액을 사용하여 상기 질화막(3)패턴을 제거하는 동시에 남아있는 산화질화막(4)패턴도 제거한다.Subsequently, the oxynitride film 4 pattern is also removed while the nitride film 3 pattern is removed using a phosphoric acid solution.
그 다음, BOE 나 불산용액을 사용하여 패드산화막(2)제2패턴을 제거한다.Then, the second pattern of the pad oxide film 2 is removed using BOE or hydrofluoric acid solution.
제2H도를 참조하면, 상기 구조의 전 표면에 희생산화막(도시하지 않음)을 형성한 후, 상기 희생산화막을 제거하여 필드산화막(7)을 형성한다.Referring to FIG. 2H, after the sacrificial oxide film (not shown) is formed on the entire surface of the structure, the field oxide film 7 is formed by removing the sacrificial oxide film.
따라서, 필드산화막(7)의 에지(edge)가 활성영역보다 함몰되지 않은 좋은 특성의 소자분리막을 형성한다.Thus, the device isolation film having a good characteristic is formed in which the edge of the field oxide film 7 is not recessed than the active region.
상술한 바와 같이 본 발명의 반도체소자의 소자분리막 제조방법은 LOCOS(Local Oxidation of Silcon) 공정을 응용한 소자분리막 제조방법에 있어서, 소자분리영역을 노출하는 질화막패턴과, 패드산화막제1패턴을 형성하고, 상기 패드산화막제1패턴을 측벽에서 활성영역쪽으로 일정부분 식각하여 패드산화막제2패턴을 형성하고, 상기 질화막패턴과, 패드산화막제2패턴의 측벽에 ⊥자 형태의 산화질화막패턴과, 스페이서 형태의 산화막을 형성한 후, 패드산화막을 형성하므로써, 반도체소자의 신뢰성을 향상하는 이점이 있다.As described above, in the device isolation film manufacturing method of the semiconductor device of the present invention, in the device isolation film manufacturing method using the LOCOS (Local Oxidation of Silcon) process, a nitride film pattern exposing the device isolation region and a pad oxide film first pattern are formed. The pad oxide film first pattern is partially etched from the sidewall toward the active region to form a pad oxide film second pattern. The nitride oxide pattern, the oxidized nitride film pattern having a U-shape on the sidewall of the pad oxide film second pattern, and a spacer After the oxide film is formed, the pad oxide film is formed, thereby improving the reliability of the semiconductor device.
제 1A 도 내지 제 1C 도는 종래의 실시예에 따른 반도체소자의 소자분리막 제조 공정도.1A to 1C are diagrams illustrating a device isolation film manufacturing process of a semiconductor device according to a conventional embodiment.
제 2A 도 내지 제 2H 도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조 공정도.2A through 2H are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체기판 2 : 패드산화막1 semiconductor substrate 2 pad oxide film
3 : 질화막 4 : 산화막3: nitride film 4: oxide film
5 : 산화질화막 6 : 스페이서5: oxynitride film 6: spacer
7 : 필드산화막7: field oxide film
Claims (12)
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| KR1019950054955A KR100361763B1 (en) | 1995-12-22 | 1995-12-22 | Method for manufacturing isolation layer of semiconductor device |
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| KR1019950054955A KR100361763B1 (en) | 1995-12-22 | 1995-12-22 | Method for manufacturing isolation layer of semiconductor device |
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| KR100361763B1 true KR100361763B1 (en) | 2003-02-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100872972B1 (en) * | 2007-06-08 | 2008-12-08 | 주식회사 동부하이텍 | Method of manufacturing semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4580330A (en) * | 1984-06-15 | 1986-04-08 | Texas Instruments Incorporated | Integrated circuit isolation |
| JPS6453559A (en) * | 1987-08-25 | 1989-03-01 | Sharp Kk | Manufacture of semiconductor device |
| US5393692A (en) * | 1993-07-28 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Recessed side-wall poly plugged local oxidation |
| US5453397A (en) * | 1993-12-14 | 1995-09-26 | Fujitsu Limited | Manufacture of semiconductor device with field oxide |
| JPH07263432A (en) * | 1994-03-23 | 1995-10-13 | Oki Electric Ind Co Ltd | Manufacture of field oxide film |
| KR0176154B1 (en) * | 1995-05-31 | 1999-04-15 | 김광호 | Isolation method of semiconductor device |
-
1995
- 1995-12-22 KR KR1019950054955A patent/KR100361763B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4580330A (en) * | 1984-06-15 | 1986-04-08 | Texas Instruments Incorporated | Integrated circuit isolation |
| JPS6453559A (en) * | 1987-08-25 | 1989-03-01 | Sharp Kk | Manufacture of semiconductor device |
| US5393692A (en) * | 1993-07-28 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Recessed side-wall poly plugged local oxidation |
| US5453397A (en) * | 1993-12-14 | 1995-09-26 | Fujitsu Limited | Manufacture of semiconductor device with field oxide |
| JPH07263432A (en) * | 1994-03-23 | 1995-10-13 | Oki Electric Ind Co Ltd | Manufacture of field oxide film |
| KR0176154B1 (en) * | 1995-05-31 | 1999-04-15 | 김광호 | Isolation method of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100872972B1 (en) * | 2007-06-08 | 2008-12-08 | 주식회사 동부하이텍 | Method of manufacturing semiconductor device |
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