KR100249974B1 - Semiconductor integrated circuit - Google Patents

Abstract

It is possible to make the power consumption as small as possible.

The bias circuit 1 generates a predetermined potential between the potential of the first power supply and the potential of the second power supply, and receives and biases the electrostatic and inverted input signals oscillating between the potential of the first power supply and the potential of the second power supply. A driver circuit 5 for converting a signal oscillating between the output potential of the circuit and the potential of the first power supply, and driving the transmission path with the converted signal, and a voltage divider circuit 9 for dividing the output potential of the bias circuit; And a receiver circuit 10 for detecting a signal for driving the transmission path using the output of the voltage dividing circuit as a reference potential and converting the signal to a signal oscillating between the potential of the first power supply and the potential of the second power supply. It is done.

Description

Semiconductor integrated circuit device

The present invention relates to a semiconductor integrated circuit device having a driver circuit for driving a bus, a clock line, or an input / output line of a semiconductor chip.

The power consumption P of the CM0S circuit is given by the following equation.

[Equation 1]

P = pt, f, CL, Vs, V _DD

Where Vs is the signal amplitude, V is the supply voltage, pt is the switching probability, f is the clock frequency, and CL is the load capacity.

In the conventional circuit, since the signal is amplitude between the power supply voltage,

[Equation 2]

P = pt, f, CL, V _DD ²

Becomes

Since large parasitic capacitances are usually present in buses, clock lines, and input / output lines of semiconductor chips, the driver circuits that drive these lines consume large power. This problem has become an increasingly important problem in recent years when low power consumption of semiconductor integrated circuit devices has been called for.

Therefore, one method of reducing power consumption is to reduce the signal amplitude, as can be seen from Equation (1). However, this is not easy. First, it is difficult to realize a driver circuit for outputting a small amplitude signal at low power. Alternatively, it is difficult to realize at low power a receiver circuit that receives a small amplitude signal and returns it to a normal signal.

In addition, since the noise margin becomes small when a small amplitude signal is used, it is also difficult to prevent wrong signal transmission. In particular, the input and output lines of the chip are susceptible to signal reflections. Crosstalk with signals of normal amplitude is also a problem.

Alternatively, variations in the threshold of the receiver circuit due to temperature changes and device variations are also a problem.

For the above reason, the conventional small amplitude signal is only used in a part of the circuit which can know the characteristics of the bit line signal of a memory well, and the signal which amplifies between power supply voltages is used for the general semiconductor circuit device.

For this reason, there is a problem that low power consumption of the semiconductor integrated circuit device including the driver circuit is not advanced.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor integrated circuit device having a driver circuit with as little power consumption as possible.

1 is a configuration diagram of a first embodiment of a semiconductor integrated circuit device according to the present invention.

2 is a configuration diagram of a second embodiment of a semiconductor integrated circuit device according to the present invention;

3 is a circuit diagram showing a specific example of a voltage divider circuit according to the semiconductor integrated circuit devices of the first and second embodiments.

4 is a configuration diagram of a third embodiment of a semiconductor integrated circuit device according to the present invention.

5 is a configuration diagram of a fourth embodiment of a semiconductor integrated circuit device according to the present invention.

6 is a circuit diagram for generating an input signal of a driver circuit according to the present invention.

Fig. 7 is a circuit diagram showing one specific example of the sense amplifier circuit in the receiver circuit according to the present invention.

Fig. 8 is a circuit diagram showing another embodiment of the sense amplifier circuit in the receiver circuit according to the present invention.

9 is a configuration diagram of a fifth embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 10 is a circuit diagram showing a specific example of the bus terminator circuit used in the fifth embodiment. FIG.

11 is a configuration diagram of a sixth embodiment of a semiconductor integrated circuit device according to the present invention.

12 is a configuration diagram of a seventh embodiment of a semiconductor integrated circuit device according to the present invention.

13 is a configuration diagram of an eighth embodiment of a semiconductor integrated circuit device according to the present invention.

14 is a configuration diagram of a ninth embodiment of a semiconductor integrated circuit device according to the present invention.

15A and 15B are diagrams showing the configuration of a switch circuit for a semiconductor chip according to the semiconductor integrated circuit device of the ninth embodiment.

16A to 16C are configuration diagrams of a switch circuit of the semiconductor chip shown in FIG. 15.

17 is a configuration diagram of a first modification of the ninth embodiment.

18 is a configuration diagram of a second modification example of the ninth embodiment.

19 is a configuration diagram of a tenth embodiment of a semiconductor integrated circuit device according to the present invention.

20 is a configuration diagram of an eleventh embodiment of a semiconductor integrated circuit device according to the present invention.

21 is a configuration diagram of a twelfth embodiment of a semiconductor integrated circuit device according to the present invention.

22 is a configuration diagram of a thirteenth embodiment of a semiconductor integrated circuit device according to the present invention.

23A and 23B are diagrams of the semiconductor chip according to the thirteenth embodiment.

24 is an explanatory diagram of substrate wiring;

25 is a configuration diagram of a fourteenth embodiment of a semiconductor integrated circuit device according to the present invention;

Fig. 26 is a configuration diagram of a fifteenth embodiment of a semiconductor integrated circuit device according to the present invention.

* Explanation of symbols for main parts of the drawings

1: bias circuit 2: current source

3: N-channel MOS transistor 4: capacitor

5 driver circuit 9 voltage divider circuit

10: receiver circuit 40: bus terminator

5l _A , 51 _B , 52 _A , 52 _B , 53 _A , 53 _B , 54 _A , 54 _B : Pad

61, 62, 63, 64: bonding wiring 92a, 92b: selector

92c: bus 101, l02,103: switch element

141,142,143,144: Low amplitude input / output circuit

A first aspect of a semiconductor integrated circuit device according to the present invention is a bias circuit for generating a predetermined potential between a potential of a first power source and a potential of a second power source, and between a potential of the first power source and a potential of the second power source. A driver circuit for receiving an electrostatic and inverting input signal oscillating at a signal, converting the signal into a vibration signal between an output potential of the bias circuit and a potential of the first power supply, and driving the transmission path with the converted signal; A voltage dividing circuit for dividing the output potential of the signal; and a signal for driving the transmission path by setting the output of the voltage dividing circuit as a reference potential, and oscillating between the potential of the first power supply and the potential of the second power supply. It characterized in that it comprises a receiver circuit for converting to.

Further, a second aspect of the semiconductor integrated circuit device according to the present invention is a bias circuit for generating a predetermined potential between the potential of the first power supply and the potential of the second power supply, and the potential of the first power supply and the potential of the second power supply. Receives an electrostatic and inverting input signal oscillating between and converts the signal into a signal oscillating between the output potential of the bias circuit and the potential of the first power source based on the enable signal to drive the transmission path with the converted signal. Or a signal for driving the transmission path using a driver circuit whose output is high impedance, a voltage divider circuit for dividing the output potential of the bias circuit, an output of the voltage divider circuit as a reference potential, and the first power supply. And a receiver circuit for converting a signal oscillating between the potential of and the potential of the second power supply.

Further, a third aspect of the semiconductor integrated circuit device according to the present invention is a bias circuit for generating a predetermined potential between the potential of the first power source and the potential of the second power source, the potential of the first power source and the second power source. A driver circuit for receiving an electrostatic and inverting input signal oscillating between the potentials, converting it into a differential signal oscillating between the output potential of the bias circuit and the potential of the first power supply, and driving the transmission path with the differential signal; And a receiver circuit for detecting a differential signal for driving said transmission path and converting it into a signal oscillating between the potential of said first power source and said potential of said second power source.

Further, a fourth aspect of the semiconductor integrated circuit device according to the present invention is a bias circuit for generating a predetermined potential between the potential of the first power supply and the potential of the second power supply, and the potential of the first power supply and the second power supply. Receives an electrostatic and inverting input signal oscillating between the potentials, converts the differential signal oscillating between the output potential of the bias circuit and the potential of the first power source based on the enable signal to drive the transmission path with this differential signal. Or a receiver circuit for outputting high impedance and a receiver circuit for detecting a differential signal for driving said transmission path and converting it into a signal oscillating between the potential of said first power supply and said potential of said second power source. It is characterized by being.

A fifth aspect of the semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the second or fourth aspect, wherein the potential of the transmission path is maintained at a predetermined value when the output of the driver circuit becomes high impedance. A bus terminator circuit is provided.

Further, a sixth aspect of the semiconductor integrated circuit device according to the present invention is a bias circuit for generating a predetermined potential between the potential of the first power source and the potential of the second power source, the potential of the first power source and the potential of the second power source. Receiving a first electrostatic and inverting input signal oscillating therebetween, converting the signal into an oscillating signal between the output potential of the bias circuit and the potential of the first power source based on the first enable signal, and outputting the signal; or A first semiconductor chip having a first driver circuit having an output of high impedance, a first voltage divider circuit for dividing an output potential of the bias circuit, and a first receiver circuit, and an input terminal connected to an input terminal of the first voltage divider circuit through wiring; A second voltage divider circuit connected to divide the output potential of the bias circuit, and a second vibrating between the potential of the first power supply and the potential of the second power source. Receives electrostatic and inverting input signals and converts the signals into oscillating signals between the output potential of the bias circuit and the first power supply potential based on a second enable signal to output these signals or to make the outputs high impedance And a second semiconductor chip having a second driver circuit and a second receiver circuit, the output terminal of which is connected to the output terminal of the first driver circuit through a transmission line, wherein the first receiver circuit is a portion of the first driver circuit. Operates when the output is high impedance, detects a signal from the second driver opportunity transmitted through the transmission wiring, and converts the signal into a vibrating signal between the potential of the first power source and the potential of the second power source; The second receiver circuit operates when the output of the second driver circuit is high impedance and is transmitted through the transmission wiring. Detecting a signal of the group from the first driver circuit, and is characterized in that conversion into a signal that oscillates between the first l potential of the power source and the potential of the second power source.

A seventh aspect of a semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to any one of the first and sixth aspects, wherein the bias circuit includes a plurality of the same conductivity type each gate and drain are connected to each other. Has a series circuit in which the M0S transistors are connected in series, and another MOS transistor of the same conductivity type as the conductivity type, and one end which becomes the source side of the series circuit is connected to the first power supply, and the drain side of the series circuit is provided. The other end is connected to a current source and a gate of the other M0S transistor, a drain of the other M0S transistor is connected to the second power source, and a bias potential is output from the source of the other M0S transistor.

Moreover, the 8th aspect of the semiconductor integrated circuit device by this invention is the 1st bias circuit which generate | occur | produces the predetermined electric potential between the electric potential of a 1st power supply, and the electric potential of a 2nd power supply, the electric potential of the said 1st power supply, and said 2nd power supply. Receiving a first electrostatic and inverting input signal oscillating between a potential of and converting it into a differential signal oscillating between an output potential of the first bias circuit and a potential of a first power source based on the first enable signal; An first semiconductor chip having a first driver circuit and a first receiver circuit which output a signal or whose output is high impedance; Receiving a second bias circuit for generating a predetermined voltage between the potential of the third power source and the potential of the fourth power source, a second electrostatic and inverting input signal oscillating between the potential of the third power source and the potential of the fourth power source; A second driver circuit which converts the differential signal oscillating between the output potential of the second bias circuit and the potential of the third power source based on the second enable signal and outputs the differential signal or the output becomes high impedance. And a second semiconductor chip having a second receiver circuit, wherein output terminals of the first and second driver circuits are connected by a transmission line, and the first receiver circuit has a high impedance output of the first driver circuit. Is detected when the differential signal from the second driver circuit transmitted through the transmission wiring is detected and the potential of the first power supply and the second power supply are detected. Converts into a signal oscillating between the potentials, and the second receiver circuit operates when the output of the second driver circuit is high impedance to detect a differential signal from the first driver circuit transmitted through the transmission wiring And converting the signal into a vibrating signal between the potential of the third power source and the potential of the fourth power source.

A ninth aspect of the semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the eighth aspect, wherein the first bias circuit includes a plurality of first conductive type M0S transistors having respective gates and drains connected thereto. Has a series circuit connected in series and another MOS transistor of the first conductivity type, one end serving as the source side of the series circuit is connected to the first power supply, and the other end serving as the drain side of the series circuit is a current source. And a drain of the other M0S transistor of the first conductivity type, the drain of the other M0S transistor of the first conductivity type is connected to the second power supply, and a bias potential from a source of the other MOS transistor of the first conductivity type. The second bias circuit is a series in which a plurality of M0S transistors of a second conductivity type each gate and drain are connected are connected in series. And another M0S transistor of the second conductivity type, one end of which is the source side of the series circuit is connected to the third power supply, and the other end of which is the drain side of the series circuit is a current source and the second conductivity type. Is connected to a gate of another M0S transistor of, wherein a drain of the other M0S transistor of the second conductivity type is connected to the fourth power source, and a bias potential is output from a source of the other M0S transistor of the second conductivity type. do.

Further, a tenth aspect of a semiconductor integrated circuit device according to the present invention has a plurality of semiconductor chips arranged in a matrix, each semiconductor chip has an input / output terminal for data transmission, and the other input / output terminal is adjacent to another semiconductor chip. Is connected to the input / output terminals of the input / output terminals and the transmission wirings formed of the bonding wirings or the substrate wirings. Also, a small amplitude input / output circuit is provided at the input / output terminals for data transfer of all or part of the semiconductor chip. Receive an electrostatic and inverted signal oscillating between the first potential of the first power supply and the second potential of the second power supply corresponding to the semiconductor chip provided with the small amplitude input / output circuit, and between the first potential and the second potential. The signal is converted into a small amplitude signal oscillating between the predetermined potential of the first potential and the first potential, and the converted signal is adjacent through the transmission wiring. At the same time to transmit the input and output terminals of the other semiconductor chip, characterized in that for converting a small amplitude signal transmitted through the wiring for the signal transmitted to the vibration between the first potential and the second potential.

An eleventh aspect of a semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device of the tenth aspect, wherein the small amplitude input / output circuit includes a bias for generating a predetermined potential between the first potential and the second potential. A circuit and receives an electrostatic and inverting input signal oscillating between the first potential and the second potential, and converts the signal into a signal oscillating between the output potential of the bias circuit and the first potential based on an enable signal. The driver circuit which drives the said transmission wiring with this converted signal, or the output becomes high impedance, the voltage divider circuit which divides the output potential of the said bias circuit, and the said transmission wiring using the output of the voltage divider circuit as a reference potential. The receiver circuit detects a signal transmitted through the signal and converts the signal into a vibrating signal between the first potential and the second potential. Characterized in that the offers.

A twelfth aspect of the semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device of the tenth aspect, wherein the small amplitude input / output circuit includes a bias for generating a predetermined potential between the first potential and the second potential. A differential signal receiving a circuit and an electrostatic and inverting input signal oscillating between the first potential and the second potential and oscillating between the output potential of the bias circuit and the potential of the first power source based on an enable signal Drive circuit for transmission with this differential signal, or output a high impedance, and detect a differential signal sent through the transmission wiring to oscillate between the first potential and the second potential. And a receiver circuit for converting the signal into a signal.

Further, a third aspect of the semiconductor integrated circuit device according to the present invention has first to nth semiconductor chips arranged in a row, the first semiconductor chip having first processing means having a predetermined processing function, and data transfer. The first input / output terminal and the output of the first functional means are converted into a small amplitude signal having an amplitude smaller than this output, and are sent to the adjacent second semiconductor chip through the first input / output terminal, And a first small amplitude input / output circuit for converting the small amplitude signal transmitted from the chip through the first input / output terminal into a large amplitude signal having an amplitude greater than that of the small amplitude signal and sending it to the first functional means. The semiconductor chip of i (i = 2, ..., n-1) includes an i-th functional means having a predetermined processing function, input / output terminals of the second (i-1) and second i-1 for data transfer, and the second the small amplitude input / output circuit of (i-1) and 2i-l, and a switch circuit of i-1, wherein the switch circuit of i-1 receives the output of the i-th functional means from the small amplitude input / output circuit of the second (i-1) or the small amplitude input / output of the second i-1. Send out the output based on the control signal to the circuit and send the output of the second amplitude i / o circuit or the second amplitude input / output circuit to the i < th > Selects based on the control signal to pass to the other small amplitude input / output circuit of the second (i-1) or the second amplitude input / output circuit of the second i-1, and exhausts the second (i-1) The width input / output circuit converts the output of the switch circuit of the i-1 into a small amplitude signal having an amplitude smaller than this output and sends it to the semiconductor chip of the i-1 through the input / output terminal of the second (i-1). At the same time, through the input and output terminals of the second (i-1) to the semiconductor chip of the i-1 The small amplitude signal to be transmitted is converted into a large amplitude signal having an amplitude greater than that of the small amplitude signal, and sent to the switch circuit of the i-1. The output of the switch circuit is converted into a small amplitude signal having a smaller amplitude than this output and sent to the I + 1 semiconductor chip through the input / output terminal of the second i-1, and through the input / output terminal of the second i-1. The small amplitude signal transmitted from the i + 1th semiconductor chip is converted into a large amplitude signal having an amplitude larger than that of the small amplitude signal and sent to the switch circuit of the il. The nth semiconductor chip has a predetermined processing function. The second (n-1) by converting the nth functional means, the second (n-1) input / output terminal for data transmission, and the output of the nth functional means into a small amplitude signal having an amplitude smaller than this output; Adjacent to each other through the input and output The large amplitude signal which is sent to the n-1 semiconductor chip and is transmitted from the nth-1 semiconductor chip through the second (n-1) input / output terminal has a larger amplitude than the small amplitude signal. And a second (n-1) small amplitude input / output circuit which converts the signal to the nth function means and sends it to the i < th > The input / output terminal of the second i-1 of the semiconductor chip of n-1) is connected to the input / output terminal of the second i of the semiconductor chip of the i + 1 by a transmission wiring including bonding wiring or substrate wiring. do.

A fourteenth aspect of the semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device of the thirteenth aspect, wherein the switch circuit of the i th (i = 1, ..., n-2) is exhausted in the second i. A first switch element for guiding the width input / output circuit and the function block of the i + l based on a first control signal, the function block of the i + l and the small amplitude input / output circuit of the second i + 1; A second switch element for conducting on the basis of a control signal, and a third switch element for conducting the second amplitude input / output circuit of the second i and the small amplitude input / output circuit of 2i + 1 based on a third control signal; The switch element of j (j = 1, ..., 3) is a transfer gate comprising an N-channel MOS transistor for receiving the j-th control signal at the gate and a P-channel M0S transistor for receiving an inverted signal of the j-th control signal. Has a, from the first to The third control signal is characterized in that if the value of one of the control signals is "H" level, the other two control signals are "L" level.

Further, a fifteenth aspect of a semiconductor integrated circuit device according to the present invention has first to nth semiconductor chips arranged in a row, the first semiconductor chip having first functional means having a predetermined processing function, and data transfer. The first input / output terminal and the output of the first functional means are converted into a small amplitude signal having an amplitude smaller than this output, and are sent to the adjacent second semiconductor chip through the first input / output terminal, And a first small amplitude input / output circuit for converting the small amplitude signal transmitted from the chip through the first input / output terminal into a large amplitude signal having an amplitude greater than that of the small amplitude signal and sending it to the first functional means. The semiconductor chip of i (i = 2, ..., n-1) includes an i-th functional means having a predetermined processing function, input / output terminals of the second (i-1) and second i-1 for data transfer, and the second Small amplitude input / output circuit of (i-1) and 2i-1 And a selector circuit of second (i-1) and second i-1, wherein the small amplitude input / output circuit of the second (i-1) is adjacent to the second (i-1) input / output terminal. The small amplitude signal transmitted from the semiconductor chip of i-1 is converted into a large amplitude signal having an amplitude larger than that of the small amplitude signal, and sent to the selector circuit of the second (i-1). Signal is converted into a signal having a smaller amplitude than that of this signal and sent to the semiconductor chip of the i-1 through the input / output terminal of the second (i-1), and the small amplitude of the second i-1 The input / output circuit converts the small amplitude signal transmitted from the semiconductor chip of the i + 1 adjacent through the input / output terminal of the second i-1 into a large amplitude signal having an amplitude larger than that of the small amplitude signal. The signal from the selector of the second i-1 is amplitude greater than that of the signal The signal is converted into a small signal and sent to the semiconductor chip of the i + l through the input / output terminal of the second i-1, and the selector circuit of the second (i-1) outputs the output of the i < th > The signal from the selector of 2i-1 is sent to the small amplitude input / output circuit of the second (i-1), and the signal from the small amplitude input / output circuit of the second (i-1) is based on the control signal. Selects and outputs to the i-th functional means or the selector circuit of the second i-1, wherein the selector circuit of the second i-1 outputs the output of the i-th functional means and the selector circuit of the second (i-1). Outputs a signal from the second amplitude input / output circuit to the second i-1, and simultaneously selects a signal from the second amplitude input / output circuit of the second i-1 based on the control signal; Is sent to the selector circuit of 2 (i-1), and the nth semiconductor chip is The second (n-1) input / output terminals for data transmission, the output of the nth function means and the second amplitude means having a smaller amplitude than the output to convert the second ( The small amplitude signal transmitted through the input / output terminal of n-1) to the adjacent nth-1 semiconductor chip and transmitted through the input / output terminal of the second (n-1) from the semiconductor chip of nl And a second (n-1) small amplitude input / output circuit which is converted to a large amplitude signal having an amplitude larger than that of the small amplitude signal and sent to the nth function means.

A sixteenth aspect of the semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to any one of the thirteenth to fifteenth aspects, wherein the first semiconductor chip includes a CPU, and the second to second aspects. The nth semiconductor chip is characterized by including a memory.

A seventeenth aspect of a semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to any one of the thirteenth to fifteenth aspects, wherein the semiconductor chips of the first to n-1 are each provided with a CPU. The nth semiconductor chip is characterized by including a memory.

1 shows a first embodiment of a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device of this embodiment includes a receiver circuit 10 having a small amplitude output circuit, a voltage divider circuit 9, and a sense amplifier circuit. The small amplitude output circuit includes a bias circuit 1 and a driver circuit 5.

The bias circuit 1 generates a predetermined potential, a series circuit in which a current source 2 is connected in series with _n N-channel MOS transistors M _l ,..., M _n of the same size, and an N-channel MOS. The transistor 3 and the capacitor 4 are provided. The gate terminal of each transistor M _i (i = 1, ..., n) is connected to the drain terminal, the drain terminal of the transistor M _n is connected to the output terminal of the current source 2, and the source of the transistor M ₁ is grounded. On the other hand, the drain terminal of the transistor 3 is connected to the driving power supply V _DD , the gate terminal is connected to the drain terminal of the transistor M _n , and the source terminal is grounded through the capacitor 4.

Therefore, when the threshold voltage of each transistor M _i (i = 1, ..., n) is set to V _th , the potential of the drain terminal of the transistor M _n becomes n · V _th .

In addition, since the threshold voltage of the transistor 3 can also be set to V _th , the potential of the source terminal of the transistor 3, that is, the output terminal N _v of the bias circuit 1 is constant (n-1) V _th. Becomes Moreover, the capacitor 4 is provided in order to stabilize the electric potential of the output terminal of the bias circuit 1 more, and the output transient response of the driver circuit 5 becomes favorable by this. The capacitor 4 may be omitted.

The driver circuit 5 receives an electrostatic input signal and an inverted input signal that oscillate between the driving potential V _DD and the ground potential GND and outputs a small amplitude signal that oscillates between the output potential of the bias circuit 1 and the ground potential GND. The N-channel MOS transistors 6 ₁ and 6 ₂ connected in series are provided by driving the transmission paths 100 such as buses and clock lines by the small amplitude signals. The transistor 6 ₁ has a drain connected to the output terminal N _V of the bias circuit, receives an electrostatic input signal at the gate, and a source connected to the drain of the transistor 6 ₂ . The transistor 6 ₂ also receives an inverting input signal at its gate and the source is grounded. The output signal is sent to the transmission path 100 from the connection point of the transistor 6 ₁ and the transistor 6 ₂ .

The voltage dividing circuit 9 divides the output voltage of the bias circuit 1, and is composed of, for example, a plurality of resistors R ₁ and R ₂ connected in series as shown in FIG. 3.

The receiver circuit 10 detects a small amplitude signal transmitted through the transmission path 100 in the sense amplifier circuit using the output potential of the voltage dividing circuit 9 as a reference potential and vibrates between the driving potential V _DD and the ground potential GND. To convert it into a signal.

As described above, according to the semiconductor integrated circuit device of the first embodiment, the output of the driver circuit 5 for driving the transmission path 100 such as a bus or a block line can be a small amplitude signal. In general, the power consumption of the driver circuit is proportional to the amplitude of the output signal. For this reason, the semiconductor integrated circuit device of this embodiment can reduce power consumption compared with the conventional case.

In the above embodiment, the series circuit in the bias circuit 1 is composed of N-channel MOS transistors of the same size, but may be composed of N-channel MOS transistors of different sizes.

Next, the structure of 2nd Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. In the semiconductor integrated circuit device of the present embodiment, in the semiconductor integrated circuit device of the first embodiment shown in FIG. 1, NOR gates 7 ₁ , 7 ₂ are newly provided in the driver circuit 5. The NOR gate 7 ₁ performs a NOR operation based on the electrostatic input signal and the enable signal, and sends the result of the operation to the gate of the transistor 6 ₁ . The NOR gate 7 ₂ performs a NOR operation based on the inverted input signal and the enable signal, and outputs the operation result to the gate of the transistor 6 ₂ .

Therefore, in the second embodiment, when the enable signal is at the L level, the same operation as in the first embodiment shown in FIG. 1 is performed. When the enable signal is at the H level, the output of the driver circuit 5 has a high impedance. Becomes

It goes without saying that the semiconductor integrated circuit device of the second embodiment also has the same effect as that of the first embodiment.

Next, the structure of 3rd Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. The semiconductor integrated circuit device of the present embodiment is the semiconductor integrated circuit device of the first embodiment shown in FIG. 1, in which an N-channel MOS transistor connected in series with the driver circuit 5 while removing the voltage dividing circuit 9 ( 6 ₃ , 6 ₄ ) newly installed. The transistor 6 ₃ has a drain connected to the output terminal of the bias circuit 1, receives an inverted input signal at the gate, and has a source connected to the drain of the transistor 6 ₄ . Transistor 6 ₄ receives a capacitive input signal at its gate and the source is grounded.

Then, a small amplitude electrostatic signal from the connection point of the transistor 6 ₁ and the transistor 6 ₂ is transmitted to the receiver circuit 10 through the transmission path 100 ₁ . In addition, an inverted signal that has been amplified from the connection point of the transistor 6 ₃ and the transistor 6 ₄ is transmitted to the receiver circuit 10 through the transmission path 100 ₂ .

Therefore, in the third embodiment, the driver circuit 5 drives the transmission paths 100 ₁ , 100 ₂ with a differential signal oscillating between the predetermined potential n-1 · V _th and the ground potential GND. . The receiver circuit 10 detects a differential signal transmitted through the transmission paths 100 ₁ and 100 ₂ in the sense amplifier circuit and converts the differential signal into a vibration signal between the driving power supply V _DD and the ground power supply GND.

As described above, the semiconductor integrated circuit device of the present embodiment can reduce power consumption as much as possible in the case of the first embodiment.

In the semiconductor integrated circuit device of this embodiment, although the transmission path is required twice as compared with the first embodiment, the reference potential of the sense amplifier circuit is unnecessary, and the in-phase noise also becomes stronger, thereby increasing the operation margin.

Next, the structure of 4th Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. In the semiconductor integrated circuit device of this embodiment, the NOR gates 7 ₁ , 7 ₂ are provided in the driver circuit 5 in the semiconductor integrated circuit device of the third embodiment shown in FIG. 4.

The NOR gate 7 ₁ performs an NOR operation based on the electrostatic input signal and the enable signal, and sends the result of the operation to the gates of the transistors 6 ₁ and 6 ₄ . The NOR gate 7 ₂ performs a NOR operation based on the inverted input signal and the enable signal, and sends the operation result to the gates of the transistors 6 ₂ and 6 ₃ .

Therefore, in the present embodiment, when the enable signal is at the L level, the same operation as in the third embodiment is performed. When the enable signal is at the H level, the output of the driver circuit 5 becomes high impedance.

As described above, the semiconductor integrated circuit device of this embodiment can also reduce power consumption as much as possible.

In addition, the electrostatic input signal and the inverted input signal used in the first to fourth embodiments are inverted gates 21 and 22, a transfer gate composed of a P-channel MOS transistor and an N-channel MOS transistor as shown in FIG. 23) can be generated by a circuit.

In addition, the sense amplifier circuits used in the first to fourth embodiments include a current source 25 and two P-channel MOS transistors 26 ₁ and 26 ₂ for receiving a differential input signal at the gate as shown in FIG. And two N-channel MOS transistors 27 ₁ and 27 ₂ . In addition, the output of the first and in the second embodiment the partial pressure in the gate of the transistor (26 ₂₎ circuit 9 is input.

In addition, the sensing amplifier circuit described above includes a P-channel MOS transistor 31 for receiving a control signal at a gate as shown in FIG. 8, and two P-channel MOS transistors 32 ₁ , 32 for receiving a differential input signal at a gate. ₂₎ and, at the same time connected in series to the gate it is commonly connected to the P-channel MOS transistor (33 ₁₎ and the N-channel MOS transistor (34 ₁₎ and, at the same time connected in series to the gate is commonly connected to the P-channel MOS transistor ( 33 ₂ ) and N-channel MOS transistors 34 ₂ .

Next, the structure of 5th Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. The semiconductor integrated circuit device of the present embodiment is the semiconductor integrated circuit device of the second embodiment shown in Fig. 2, wherein the bus terminator circuit 40 is disposed between the output terminal of the bias circuit 1 and the transmission path 100. New installation. This bus terminator circuit 40 is for maintaining the electric potential of the transmission path 100, such as a bus, when the output of the driver circuit 5 becomes high impedance.

This bus terminator circuit 40 is composed of two P-channel MOS transistors 41 ₁ and 41 ₂ and two N-channel MOS transistors 42 ₁ and 42 ₂ , as shown in FIG. 10. The transistor 41 _i (i = 1, 2) has a source connected to the output terminal N _V of the bias circuit 1, a gate connected to a gate of the transistor 42 _i , and a drain thereof drains the transistor 42 _i . Is connected to. Then, the source of the transistor 42 _i (i = 1, 2) is grounded. The drain of the transistor (41 _1, 42 ₁₎ is connected to a gate of the transistor (4l _2, 42 _2), the drain of the transistor (41 _2, 42 ₂₎ is connected to the gate of the transistor (41 _1, 42 _1). The drains of the transistors 41 ₁ and 42 ₁ are connected to the transmission path 100.

As described above, the semiconductor integrated circuit device of the fifth embodiment can have as little power consumption as in the second embodiment. In addition, when the output of the driver circuit 5 becomes high impedance, the potential of the transmission path 100 can be maintained at a predetermined potential.

Next, the structure of 6th Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. The semiconductor integrated circuit device of the present embodiment is a semiconductor integrated circuit device of the fourth embodiment shown in Fig. 5, wherein the bus is connected between the output terminal N _V of the bias circuit 2 and the transmission paths 100 ₁ , 100 ₂ . The terminator circuit 40 is provided. As in the case of the fifth embodiment, the bus terminator circuit 40 is adapted to maintain the potential of the transmission paths 100 ₁ , 100 ₂ at a predetermined potential when the output of the driver circuit 5 becomes high impedance. This is realized by the circuit shown in FIG. In this case, the transistor (41 _1, 42 ₁₎ are connected, _{(100: 1)} to transmit to the drain of the transistor _{(4l 2, 42 2) (} 100 2) has a transmission drain of the shown in Figure 10 is connected.

As described above, the semiconductor integrated circuit device of the sixth embodiment can reduce power consumption as much as possible in the case of the fourth embodiment. In addition, when the output of the driver circuit 5 becomes high impedance, the potentials of the transmission paths 100 ₁ , 100 ₂ can be maintained at a predetermined potential.

In the first to sixth embodiments, the driver circuit 5 and the receiver circuit 10 may be driven by the same power source, or may be driven by different power sources.

Next, the structure of 7th Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. The semiconductor integrated circuit device of this embodiment is two and a bias circuit (1 _A) on the semiconductor chip A of the semiconductor chip, the driver circuit (5 _A) and a voltage dividing circuit (9 _A) and a receiver circuit (10 _A) installation, and will have installed a capacitor (4 _B), and a driver circuit (5 _B), and a divider circuit (9 _B), and a receiver circuit (10 _B) on the semiconductor chip B.

The bias circuit 1 _A , the driver circuits 5 _A and 5 _B , and the voltage divider circuits 9 _A and 9 _B are the bias circuit 1 and the driver circuit 5 according to the second embodiment shown in FIG. And the voltage dividing circuit 9, respectively.

The output terminal N _V of the bias circuit 1 _A is connected to the input terminal of the voltage dividing circuit 9 _A and also to the pad 51 _A provided in the semiconductor chip A. In addition, one end of the input stage and the capacitor of the voltage dividing circuit (9 _B) are connected to the pad (51 _B) are set on the chip B. These chips A and B are arranged at very close distances, and the pads 51 _A and 51 _B are connected by the bonding wiring 61. Therefore, the output potential of the bias circuit 1 _A is also applied to the voltage dividing circuit 9 _B and the capacitor 4 _B through the pad 51 _A , the bonding wiring 61, and the pad 51 _B to the chip B as well. Further, the capacitor (4 _B) is set in order to stably maintain the electric potential at the input terminal of the voltage dividing circuit (9 _B). A capacitor (4 _B) may omitted.

The output end of the driver circuit 5 _A is connected to a pad 52 _A set on the chip A, and the output end of the driver circuit 5 _B is connected to a pad 52 _B set on the chip B. These pads 52 _A and 52 _B are connected by bonding wires 62. The drain of the transistor 6 ₁ constituting the driver circuit 5 _B is connected to the pad 51 _B.

On the other hand, the receiver circuit 10 _A detects the output of the driver circuit 5 _B transmitted through the bonding wiring 62 using the output potential of the voltage dividing circuit 9 _A as the reference potential, and detects the driving potential V from the driving amplifier V. Convert into a vibrating signal between _DD and ground potential. The receiver circuit (10 _B) is a divider circuit (9 _B) to the output potential to the reference potential detecting the output of the driver circuit (5 _A) to be transmitted through the bonding wire 62, the amplification is detected in a circuit driving potential V _DD of To a signal that vibrates between and ground potential.

Therefore, in the semiconductor integrated circuit device of the present embodiment, when the driver circuit 5 is operating, the receiver circuit 10 _B is also operating, but the driver circuit 5 _B and the receiver circuit 10 _A are stopped. . Further, the driver circuit (5 _B), when the operation is operating but also the receiver circuit (10 _A) a driver circuit (5 _A) and a receiver circuit (10 _B) is able to stop the operation.

As described above, in the semiconductor integrated circuit device of the present embodiment, since the signal transmitted between the chips is small amplitude, the power of the driver circuit can be reduced and the power consumption can be reduced as much as possible.

In addition, a small amplitude input consisting of In, chip A bias circuit (1 _A) and a driver circuit (5 _A) small amplitude output circuit, and a voltage dividing circuit (9 _A) and a receiver circuit (10 _A) formed of a the embodiment and the circuit is installed, the chips B, it is possible with a small amplitude output circuit comprising a driver circuit, a voltage dividing circuit (9 _B) and a receiver circuit (10 _B) a small amplitude input circuit consisting of are provided.

In this embodiment, the two chips are arranged at very close distances, and the connection capacitance is reduced by connecting them therebetween, so that the signal reflection between the chip-to-chip wiring and the driver circuit does not occur even if impedance matching is not achieved. Do not.

In the above embodiment, it is possible to provide a bias circuit on the chip B. In this case, the bonding wiring 61 becomes unnecessary. In this case, the chip A and the chip B may use the same power source or may use different power sources.

In addition, in the said embodiment, although the chip was connected by the bonding wiring, you may connect directly by the board wiring.

Next, the structure of 8th Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. In the semiconductor integrated circuit device of this embodiment, a small amplitude input circuit and a small amplitude output circuit are provided on two semiconductor chips A and B arranged at very close distances, respectively. The small amplitude output circuit of chip A consists of a bias circuit 1 _A and a driver circuit 5 _A , and the small amplitude input circuit consists of a receiver circuit 10 _A. In addition, the small amplitude output circuit of the chip B consists of a bias circuit 1 _B and a driver circuit, and the small amplitude input circuit consists of a receiver circuit 10 _B.

The bias circuits 1 _A and 1 _B and the driver circuits 5 _A and 5 _B have the same configuration as the bias circuit 1 and the driver circuit 5 of the fourth embodiment shown in FIG. 5. The two outputs of the driver circuit 5 _A are connected to the pads 53 _A and 54 _A provided on the chip A, respectively. In addition, two outputs of the driver circuit 5 _B are connected to the pads 53 _B and 54 _B provided on the chip B, respectively. In addition, the pad (53 _B) of the chip A pad (53 _A) and the chip B is connected by a bonding wire 63, the pad (54 _B) of the chip A pad (54 _A) and a chip B is a bonding wire ( 64).

On the other hand, the receiver circuit 10 _A detects in the sense amplifier circuit the small-amplified differential output of the driver circuit 5 _B transmitted through the bonding wires 63 and 64 and vibrates between the driving potential V _DD and the ground potential GND. Convert to a signal. In addition, the receiver circuit 10 _B detects in the sense amplifier circuit the small-amplified differential output of the driver circuit 5 _A transmitted through the bonding wires 63 and 64, and between the driving potential V _DD and the ground potential GND. Convert to a vibrating signal.

Therefore, the semiconductor integrated circuit device of this embodiment also operates the receiver circuit 10 _B when the driver circuit 5 _A is operating, but the driver circuit 5 _B and the receiver circuit 10 _A stop their operation. have. In addition, a driver circuit when there are (5 _B), but the operation and the operation is also the receiver circuit (10 _A) a driver circuit (5 _A) and a receiver circuit (10 _B) is to stop the operation.

As described above, in the semiconductor integrated circuit device of the present embodiment, the signal transmitted between the chips has a small amplitude, so that the power of the driver circuit can be reduced, and the power consumption can be reduced as much as possible.

In this embodiment, the two chips are arranged at very close distances and connected therebetween by bonding wiring, so that the output capacitance is reduced, and the large signal reflection does not appear even when the chip-to-chip wiring and the driver circuit do not have impedance matching. .

In addition, in the eighth embodiment, although the chip A and the chip B used the same power source, it is also possible to use different power sources.

In the semiconductor integrated circuit devices of the seventh and eighth embodiments, the semiconductor chips A and B having the bonding wirings may be resin-sealed after being placed on the same lead frame stage.

Next, a ninth embodiment of a semiconductor integrated circuit device according to the present invention will be described with reference to FIGS. 14 to 15.

The whole structure of the semiconductor integrated circuit device of this ninth embodiment is shown in FIG. In the semiconductor integrated circuit device of this embodiment, a plurality of semiconductor chips 72 ₁ ,..., 72 _n arranged in a line are connected by bonding wirings 77. The semiconductor chip 72 ₁ has a pad 74, the semiconductor chip 72i (i = 2, ..., n-1) has pads 74 and 75, and the semiconductor chip 72 _n has a pad 75. Has The adjacent semiconductor chips 72 _i (1 = 2, ..., n-1) and the semiconductor chips 72 _{i + 1} are placed at very close distances, and the pads 74 of the semiconductor chips 72 _i are separated from each other. The pads 75 of the semiconductor chip 72 _{i + 1} are connected by bonding wirings 77.

The semiconductor chips 72 ₁ and 72 _n at the end each have a structure of a semiconductor chip 85 as shown in FIG. 15A, which has a functional block 86 and a small amplitude input / output circuit. 87 and a pad 88 are provided. The small amplitude input / output circuit 87 is composed of a small amplitude input circuit and a small amplitude output circuit of the seventh or eighth embodiment shown in FIG. 12 or FIG. In addition, when the small amplitude input circuit and the small amplitude output circuit of the eighth embodiment are used, two pads 88 are required.

Each semiconductor chip 72 _i (i = 2, ..., n-1) other than the end shown in FIG. 14 has the configuration of the semiconductor chip 90 as shown in FIG. 15B, and this chip 90 ) Has a small amplitude input / output circuit 91, a switch circuit 92, a function block 93, a small amplitude input / output circuit 94, and pads 95 and 95. The small amplitude input / output circuits 91 and 94 have the same configuration as the small amplitude input / output circuit 87 shown in Fig. 15A, respectively.

Next, the structure and operation | movement of this embodiment are demonstrated. First, in the semiconductor chip 7 _{1 1} or 72 _n at the end, as shown in FIG. 15A, the output signal of the functional block 86 is converted into a small amplitude signal by the small amplitude input / output circuit 87, and the pad ( 88) is sent out to the adjacent semiconductor chip via the bonding wiring 89. FIG. In addition, the small amplitude signal transmitted from the adjacent semiconductor chip through the bonding wiring 89 is input and amplified into the small amplitude input / output circuit 87 through the pad 88 and converted into a large amplitude signal and sent to the function block 86. .

In addition, in each semiconductor chip 72 _i (i = 2, ..., n-1) other than the end portion, as shown in FIG. 15B, the small amplitude transmitted from the adjacent semiconductor chip through the pad 95, for example. The signal is amplified by the small amplitude input / output circuit 91, converted into a large amplitude signal, and transmitted to the switch circuit 92. The large amplitude signal is selected to be transmitted to the functional block 93 by the switch circuit 92 or bypassed to the small amplitude input / output circuit 94 based on a control signal (not shown). The large amplitude signal transmitted to the small amplitude input / output circuit 94 is converted into a small amplitude signal and sent to the adjacent semiconductor chip through the pad 96 and the bonding wiring 99.

The control signal is also transmitted from an external or other semiconductor chip.

When a large amplitude signal is transmitted to the function block 93, a predetermined process is performed, and when it is necessary to send a signal to another semiconductor chip based on the result of the process, the small amplitude is transmitted through the switch circuit 92. It is transmitted to the input / output circuit 91 or the small amplitude input / output circuit 94. The small amplitude input / output circuit 91 or the small amplitude input / output circuit 94 converts the signal into a small amplitude signal and outputs the result to the adjacent semiconductor chip through the bonding wiring 98 or the bonding wiring 99. The functional block corresponds to a CPU or a memory and has a predetermined processing function.

Further, the small amplitude signal transmitted from the adjacent semiconductor chip via the pad 96 is converted into a large amplitude signal by the small amplitude input / output circuit 94. The large amplitude signal is selected to be transmitted to the functional block 93 by the switch circuit 92 or bypassed to the small amplitude input / output circuit 9l based on a control signal (not shown). The large amplitude signal sent to the small amplitude input / output circuit 91 is converted into a small amplitude signal and sent to the adjacent semiconductor chip via the pad 95 and the bonding wiring 98.

As described above, according to the semiconductor integrated circuit device of the ninth embodiment, since the signal transmitted between the semiconductor chips is a small amplitude signal, it is possible to reduce the power of the driver circuit in the small amplitude input / output circuit and to reduce the power consumption as much as possible. Can be.

In the semiconductor integrated circuit device of the present embodiment, the plurality of semiconductor chips can be placed on the same lead frame stage and resin-sealed after bonding wiring has been made.

An example of the specific structure of the switch circuit 92 used for the semiconductor integrated circuit device of 9th Embodiment is shown in FIG. This switch circuit 92 is composed of three switch elements 101, 102, 103 as shown in Fig. 16A. The switch element 101 connects the node N ₁ and the node N ₂ based on the control signal S ₁₂ , and the switch element 102 connects the node N ₂ and the node N ₃ based on the control signal S ₂₃ . 103 connects the node N ₃ and the node N ₁ based on the control signal S ₃₁ .

Each switch element has an inverter circuit 105 and a transfer gate composed of a P-channel MOS transistor 106 and an N-channel MOS transistor 107 as shown in FIG. 16B. The control signal S is transmitted to the gate of the N-channel MOS transistor 107 and simultaneously through the inverter circuit 105 to the gate of the P-channel MOS transistor 106.

Therefore, in FIG. 16A, when the value of the control signal S ₁₂ is "1" and the values of the other control signals S ₂₃ and S ₃₁ are "0", the node N ₁ and the node N ₂ are connected, and the control signal S _23. When the value of "l" and the value of the other control signals S ₃₁ and S ₁₂ are "0", the node N ₂ and the node N ₃ are connected, and the value of the control signal S ₃₁ is "1" and the other control signal S is _When the values of ₁₂ and S ₂₃ are "0", the node N ₃ and the node N ₁ are connected (see FIG. 16C).

Next, FIG. 17 shows a configuration of a first modification of the semiconductor integrated circuit device of the ninth embodiment. In the semiconductor integrated circuit device of this modification, a semiconductor chip 81 made of a CPU and a plurality of memories 82 ₁ ,..., 82 _{n are} arranged in a row in close proximity and connected by bonding wiring.

In the semiconductor integrated circuit device of the first modification, the power consumption can be reduced and the CPU can access a large amount of data at high speed.

Next, FIG. 18 shows a configuration of a second modification of the semiconductor integrated circuit device of the ninth embodiment. The semiconductor integrated circuit device of this modified example is a semiconductor integrated circuit device having a multi-CPU configuration, where a plurality of CPUs 81 ₁ ,..., 81 _n and a memory 82 are closely arranged in a row and connected by bonding wiring. .

It goes without saying that the semiconductor integrated circuit device of this second modification can also reduce power consumption.

Next, a tenth embodiment of a semiconductor integrated circuit device according to the present invention will be described with reference to FIG. In the semiconductor integrated circuit device of this embodiment, in the semiconductor integrated circuit device of the ninth embodiment shown in FIG. 14, each semiconductor chip 72i (i = 2, ..., n-1) other than the end portion is shown in FIG. It is configured as shown. That is, the semiconductor chip includes the small amplitude input / output circuit 91, the selectors 92a and 92b, the bus 92c, the functional block 93, the small amplitude input / output circuit 94, and the pads 95 and 95. ).

The small amplitude input / output circuits 91 and 94 have the same configuration as the small amplitude input / output circuit 87 shown in Fig. 15A.

In Fig. 19, the small amplitude signal transmitted from the adjacent semiconductor chip via the bonding wiring 98 is detected by the small amplitude input / output circuit 91, and for example, oscillates between the driving potential V _DD and the ground potential GND. The signal is converted into an amplitude signal and transmitted to the selector 92. The large amplitude signal is transmitted to the function block 93 by the selector 92 or bypassed to a control signal (not shown) to be transmitted to the small amplitude input / output circuit 94 via the bus 92c or the selector 92b. It is selected based on. The large amplitude signal transmitted to the small amplitude input / output circuit 94 is converted into a small amplitude signal by the small amplitude input / output circuit 94 and sent to the adjacent semiconductor chip through the pad 96 and the bonding wiring 99.

Further, the small amplitude signal transmitted from the adjacent semiconductor chip through the bonding wiring 99 is detected by the small amplitude input / output circuit 94, converted into a large amplitude signal, and transmitted to the selector 92b. The large amplitude signal is sent to the function block 93 by the selector 92b or bypassed to a control signal (not shown) to be transmitted to the small amplitude input / output circuit 91 via the bus 92c or the selector 92a. It is selected based on. The large amplitude signal sent to the small amplitude input / output circuit 91 is converted into a small amplitude signal by the small amplitude input / output circuit 91 and sent to the adjacent semiconductor chip through the pad 95 and the bonding wiring 98.

According to the semiconductor integrated circuit device of the tenth embodiment, since the transmitted signal is a small amplitude signal, it is possible to reduce the power of the driver circuit in the small amplitude input / output circuit, and to reduce the power consumption as much as possible.

Next, an eleventh embodiment of a semiconductor integrated circuit device according to the present invention is shown in FIG. The semiconductor integrated circuit device of the present embodiment is the semiconductor integrated circuit device of the tenth embodiment shown in FIG. 19, in which small amplitude input / output circuits 110 and 111 are provided at both ends of the bypass bus 92c. 92c) is used when the capacity is large. Such a configuration can further reduce power consumption.

Next, the structure of 12th Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. In the semiconductor integrated circuit device of this embodiment, four semiconductor chips l20 ₁₁ , 120 ₁₂ , 120 ₂₁ , and 120 ₂₂ arranged in a matrix form are connected by bonding wiring.

Each semiconductor chip l20 _ij (i, j = 1,2) has the configuration shown in Fig. 15B, for example. That is, each semiconductor chip includes the small amplitude input / output circuits 91 and 94, the switch circuit 92, the function block 93, and the pads 95 and 96. Therefore, since the signal transmitted between the semiconductor chips is a small amplitude signal, it is possible to reduce the power of the driver circuit in the small amplitude input / output circuit and to reduce the power consumption as much as possible.

In the semiconductor integrated circuit device of the present embodiment, the plurality of semiconductor chips may be placed on the same lead frame band and resin-sealed after bonding wiring is formed.

Next, the structure of 13th Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. In the semiconductor integrated circuit device of the present embodiment, a plurality of (m · n) semiconductor chips 130 ₁₁ , l30 ₁₂ ,..., L30 _mn arranged in a matrix form are connected by bonding wiring. The semiconductor chips 130 ₁₁ , 130 _1n ,..., 130 _ml , and 130 _mn arranged in _quadrangles have the configuration shown in FIG. 15B, respectively.

In addition, adjacent semiconductor chips 130 _il (i = 2, ..., m-1), 130 _1j (j = 2, ..., n-1), 130 _mk (k = 2, ..., n-1), And 130 _gn (g = 2, ..., m-1) have the configuration shown in Fig. 23B. That is, each of the semiconductor chips has a three-amplitude input and output circuit (151 152 153), a switch circuit 155, and a function block 156, and three pads (157 _1, ..., 157 _3). Pad (157 ₁₎ is connected to the amplitude input and output circuit 151, a pad (157 ₂₎ is connected to the amplitude input and output circuit 152, a pad (157 ₃₎ is connected to the amplitude input and output circuit 153 have. These pads 157 _i (i = 1, 2, 3) are connected to adjacent semiconductor chips via bonding wiring.

The small amplitude signals transmitted from the adjacent semiconductor chips through the pads 157 ₁ , 157 ₂ , and 157 ₃ are detected by the small amplitude input / output circuits 151, 152, 153, and are oscillated between the driving potential V _DD and the ground power supply, for example. The signal is converted into a large amplitude signal and transmitted to the switch circuit 155. This large amplitude signal is selected based on a control signal (not shown) to be transmitted by the switch circuit 155 to the function block 156 or bypassed to be transmitted to another small amplitude input / output circuit. The large amplitude signal sent to the small amplitude input / output circuit is converted into the small amplitude signal by the small amplitude input / output circuit, and sent to the adjacent semiconductor chip through the corresponding pad and bonding wiring.

In addition, when a large amplitude signal is transmitted to the function block 156, predetermined processing is performed. The output of the function block 156 is transmitted to the small amplitude input / output circuit through the switch circuit 155, converted into a small amplitude signal, and sent to the adjacent semiconductor chip through the corresponding pad.

Each semiconductor chip 130ij (i = 2, ... m-1, j = 2, n-1) shown in FIG. 22 has the configuration shown in FIG. 23A. That is, each semiconductor chip includes four small amplitude input / output circuits 141, l42, l43, 144, a switch circuit 145, a function block 146, and pads 1 47 _i (1,..., 4). Equipped. The pad 147 ₁ is connected to the small amplitude input / output circuit l41 and at the same time to the adjacent semiconductor chip through a bonding wire (not shown). The pads 147 ₂ are connected to the small amplitude input / output circuit 142 and to adjacent semiconductor chips via bonding wires (not shown). Pad (147 ₃₎ is simultaneously connected to the amplitude input and output circuit 143 is connected to the semiconductor chip adjacent through bonding wires (not shown). In addition, the pad (147 ₄₎ is connected to the semiconductor chip adjacent through bonding wires (not shown) at the same time connected to the amplitude input and output circuit (l44). The small amplitude signal transmitted from the adjacent semiconductor chip through the pad is converted into a large amplitude signal by the corresponding small amplitude input / output circuit and transmitted to the switch circuit 145. This large amplitude signal is selected based on a control signal, not shown, to be sent to the function block 146 by the switch circuit 145 or bypassed to be transmitted to another small amplitude input / output circuit. The large amplitude signal transmitted to the small amplitude input / output circuit is converted into the small amplitude signal by the small amplitude input / output circuit and sent to the adjacent semiconductor chip through the corresponding pad bonding wiring.

In addition, when a large amplitude signal is transmitted to the function block 146, predetermined processing is performed. The output of the function block 146 is transmitted to the small amplitude input / output circuit through the switch circuit 145, converted into a small amplitude signal, and sent to the adjacent semiconductor chip through the corresponding pad.

In the semiconductor integrated circuit device of the thirteenth embodiment, since the signal transmitted between the chips is a small amplitude signal, the power of the driver circuit in the small amplitude input / output circuit can be reduced, and the power consumption can be reduced as much as possible.

In addition, in this thirteenth embodiment, when m = 1, it becomes the same as the case of the ninth embodiment shown in FIG.

In the semiconductor integrated circuit devices of the ninth to thirteenth embodiments, the chips are connected by bonding wiring, but as shown in FIG. That is, pads 16la, 161b, 161c and 161d are provided on the package substrate 160, and bumps 162a, 162b, 162c and 162d are provided on these pads.

The pad 161a and the pad 161c are connected by the board wiring 165a, and the pad 161b and the pad 16ld are connected by the board wiring 165b. In addition, pads 171a and 171b are formed on the surface of the semiconductor chip 171, and pads 172a and 172b are formed on the surface of the semiconductor chip 172. The pads l71a and 171b of the semiconductor chip 171 are connected to the pads l61a and 161b of the package substrate 160 through bumps 162a and 162b, respectively, and the pads 172a and 172b of the semiconductor chip 172. Is connected to the pads 161c and 16ld of the package substrate l60 via bumps 162c and 162d, respectively. In this way, the semiconductor chips can be connected to each other using the substrate wirings 165a and 165b.

Next, FIG. 25 shows a configuration of a fourth embodiment of a semiconductor integrated circuit device according to the present invention. In the semiconductor integrated circuit device of this embodiment, a plurality of semiconductor chips 180 ₁ ,..., 180 _n arranged in a line in a plane is connected via buses 186, 187. Each semiconductor chip 180 _i (i = 1, ..., n) has pads 182 _{i and} l83 _i . Each pad 182 _i (i = 1, ..., n) is connected to a bus 186, and each pad 183 _i (i = 1, ..., n) is connected to a bus 187.

At least one semiconductor chip of the plurality of semiconductor chips 180 _i ,..., 180 _n , for example, the semiconductor chip 180 ₁ has a bias circuit l _{A in the} same manner as the semiconductor chip A of the seventh embodiment shown in FIG. 12. ) And a small amplitude output circuit consisting of a driver circuit 5 _A and a small amplitude input circuit consisting of a voltage divider circuit 9 _A and a receiver circuit 10 _A , and the output terminal of the voltage divider circuit 9 _A is provided with a pad. (182 ₁₎ is connected to an output stage of the driver circuit (5 _a) it is connected to a pad (183 _1).

Also other semiconductor chip _{(180 i) (i ≠ 1} ) has, in the same way as the semiconductor chip B in a seventh embodiment shown in Figure 12, the driver circuit (5 _B) small amplitude output circuit, and a voltage dividing circuit (9 consisting of A small amplitude input circuit consisting of _B ) and a receiver circuit 10 _B is provided, the output terminal of the voltage divider circuit 9 _B is connected to a pad 182 _i , and the output terminal of the driver circuit 5 _B is a pad 183. _i ).

Similarly to the seventh embodiment, the semiconductor integrated circuit device of this embodiment also has a small amplitude, so that the power of the driver circuit can be reduced, and power consumption can be reduced as much as possible. In the semiconductor integrated circuit device of the present embodiment, since the chips are connected via a bus, signals can be transmitted quickly and with low power, and other chips simultaneously receive signals transmitted from one chip. It becomes possible.

Next, the structure of 15th Embodiment of the semiconductor integrated circuit device which concerns on this invention is shown in FIG. The semiconductor integrated circuit device of this embodiment has a configuration in which a plurality of semiconductor chips 108 ₁ ,..., 180 _n are stacked up and down in the semiconductor integrated circuit device of the fourteenth embodiment shown in FIG. 25. It is referred to as a chip semiconductor device.

It goes without saying that the semiconductor integrated circuit device of the fifteenth embodiment also has the same effect as in the fourteenth embodiment.

In addition, this [0116] In the fifteenth embodiment, the drawing On the bus (186 187), each chip (l80 _i) (i = 1, ..., n), but is provided on the outside, each of the chips (180 _i) (i = 1, ..., n can be installed to penetrate. In this case, the buses 186 and 187 are constituted by connection wirings connecting the respective chips.

In addition, in the fourteenth and fifteenth embodiment, it is possible to provide a bias circuit on the other semiconductor chip that does not have the bias circuit is provided _{(180 i) (i ≠ 1} ). In this case, the pads 182 ₁ ,..., 182 _n and the bus 186 become unnecessary. And in this case, each chip _{(180 i) (i = 1} , ..., n) above may be using the same power, it is also possible to use other power sources.

In addition, in the above first and fourth embodiments, each semiconductor chip 180 _i (i = l, ..., n) has the same small amplitude output circuit and small amplitude input circuit as in the seventh embodiment. The small amplitude output circuit and the small amplitude input circuit similar to the eighth embodiment shown in 13 may be provided. That is, each of the semiconductor chips 180 _i (i = 1, ..., n) includes a small amplitude output circuit consisting of a bias circuit 1 _A and a driver circuit 5 _A as shown in FIG. 13, and a receiver circuit ( _A small amplitude input circuit consisting of 10 _A ), wherein one of the two output ends of the driver circuit 5 _A is connected to the pad 182 _i , and the other output end is connected to the pad 183 _i . You may also do it.

In addition, in the first to ninth embodiments, the bias circuit is constituted by an N-channel MOS transistor, but it is also possible to construct a P-channel MOS transistor. In this case, it is necessary to change the driving power supply V _DD and the ground power supply GND.

As described above, according to the present invention, since a signal passing through a transmission path such as a bus is a small amplitude signal, it is possible to reduce the power of the driver circuit for driving the transmission path and to reduce the power consumption as much as possible.

Claims (31)

A bias circuit for generating a predetermined potential between the potential of the first power supply and the potential of the second power supply; Receives an electrostatic and inverting input signal oscillating between the potential of the first power supply and the potential of the second power supply, converts the signal into a signal oscillating between the output potential of the bias circuit and the potential of the first power supply, and converts this signal. A driver circuit for driving the transmission path with the received signal; A voltage divider circuit for dividing the output potential of the bias circuit; And a receiver circuit for detecting a signal for driving the transmission path using the output of the voltage dividing circuit as a reference potential, and converting the signal to a signal oscillating between the potential of the first power supply and the potential of the second power supply. A semiconductor integrated circuit device. A bias circuit for generating a predetermined potential between the potential of the first power supply and the potential of the second power supply; Receives an electrostatic and inverted input signal oscillating between the potential of the first power supply and the potential of the second power supply, and a signal that oscillates between the output potential of the bias circuit and the potential of the first power source based on an enable signal. A driver circuit for driving the transmission path with the converted signal or outputting a high impedance; A voltage divider circuit for dividing the output potential of the bias circuit; And a receiver circuit for detecting a signal for driving the transmission path using the output of the voltage dividing circuit as a reference potential, and converting the signal to a signal oscillating between the potential of the first power supply and the potential of the second power supply. A semiconductor integrated circuit device. A bias circuit for generating a predetermined potential between the potential of the first power supply and the potential of the second power supply; Receives an electrostatic and inverting input signal oscillating between the potential of the first power supply and the potential of the second power supply, converts the differential signal oscillating between the output potential of the bias circuit and the potential of the first power supply to convert the differential signal. A driver circuit for driving a transmission path with a signal; And a receiver circuit for detecting a differential signal for driving said transmission path and converting it into a signal oscillating between the potential of said first power supply and said potential of said second power supply. A bias circuit for generating a predetermined potential between the potential of the first power supply and the potential of the second power supply; A differential that receives an electrostatic and inverting input signal oscillating between the potential of the first power source and the potential of the second power source, and oscillates between the output potential of the bias circuit and the potential of the first power source based on an enable signal A driver circuit which converts the signal into a signal and drives the transmission path or the output becomes high impedance; And a receiver circuit which detects a differential signal for driving said transmission path and converts it into a signal oscillating between the potential of said first power supply and said potential of said second power supply. 3. The semiconductor integrated circuit device according to claim 2, further comprising a bus terminator circuit that maintains a potential of the transmission path at a predetermined value when the output of the driver circuit becomes high impedance. 5. The semiconductor integrated circuit device according to claim 4, further comprising a bus terminator circuit that maintains a potential of the transfer path at a predetermined value when the output of the driver circuit becomes high impedance. A bias circuit for generating a predetermined potential between the potential of the first power source and the potential of the second power source, a first electrostatic and inverted input signal oscillating between the potential of the first power source and the potential of the second power source, A first driver circuit converting a signal oscillating between an output potential of the bias circuit and a potential of the first power source based on a single enable signal and outputting the signal, or outputting a high impedance, and the bias circuit A first semiconductor chip having a first voltage dividing circuit and a first receiver circuit for dividing an output potential; A second voltage dividing circuit connected to an input terminal of the first voltage dividing circuit through a wiring to divide the output potential of the bias circuit, a second power failure oscillating between the potential of the first power supply and the potential of the second power supply; Receiving an inverted input signal and converting the signal into a vibrating signal between the output potential of the bias circuit and the first power supply potential based on a second enable signal and outputting this signal or outputting a high impedance, And an output terminal having a second semiconductor chip having a second driver circuit and a second receiver circuit connected to an output terminal of the first driver circuit through a transmission wiring, wherein the first receiver circuit has an output of the first driver circuit. Detects a signal from the second driver opportunity that is operated at a high impedance to be transmitted through the transmission wiring; Converting into a signal oscillating between the potential of the source and the potential of the second power supply, wherein the second receiver circuit operates when the output of the second driver circuit is high impedance and is transmitted through the transmission wiring line And detecting a signal from a driver circuit and converting the signal into a signal oscillating between the potential of the first power supply and the potential of the second power supply. 2. The bias circuit according to claim 1, wherein the bias circuit includes a series circuit in which a plurality of MOS transistors of the same conductivity type each gate and drain are connected are connected in series, and another MOS transistor of the same conductivity type as the conductivity type, One end, which is the source side of the series circuit, is connected to the first power supply, the other end, which is the drain side of the series circuit, is connected to a current source and a gate of the other M0S transistor, and the drain of the other MOS transistor is connected to the second. And a bias potential is output from a source of said other M0S transistor. 3. The bias circuit according to claim 2, wherein the bias circuit includes a series circuit in which a plurality of M0S transistors of the same conductivity type each gate and drain are connected are connected in series, and other M0S transistors of the same conductivity type as the conductivity type, One end, which is the source side of the series circuit, is connected to the first power supply, the other end, which is the drain side of the series circuit, is connected to a current source and a gate of the other MOS transistor, and the drain of the other MOS transistor is connected to the second. And a bias potential is output from a source of said other MOS transistor connected to a power supply. 4. The bias circuit according to claim 3, wherein the bias circuit includes a series circuit in which a plurality of M0S transistors of the same conductivity type each gate and drain are connected are connected in series, and other M0S transistors of the same conductivity type as the conductivity type, One end, which is the source side of the series circuit, is connected to the first power supply, the other end, which is the drain side of the series circuit, is connected to a current source and a gate of the other M0S transistor, and the drain of the other MOS transistor is connected to the second. And a bias potential is output from a source of the other M0S transistor connected to a power supply. 5. The bias circuit according to claim 4, wherein the bias circuit includes a series circuit in which a plurality of M0S transistors of the same conductivity type each gate and drain are connected are connected in series, and other M0S transistors of the same conductivity type as the conductivity type, One end, which is the source side of the series circuit, is connected to the first power supply, the other end, which is the drain side of the series circuit, is connected to a current source and a gate of the other MOS transistor, and the drain of the other MOS transistor is connected to the second. And a bias potential is output from a source of the other M0S transistor connected to a power supply. 8. The bias circuit according to claim 7, wherein the bias circuit includes a series circuit in which a plurality of MOS transistors of the same conductivity type each gate and drain are connected are connected in series, and another MOS transistor of the same conductivity type as the conductivity type, One end, which is the source side of the series circuit, is connected to the first power supply, the other end, which is the drain side of the series circuit, is connected to a current source and a gate of the other MOS transistor, and the drain of the other MOS transistor is connected to the second. And a bias potential is output from a source of said other MOS transistor connected to a power supply. A first bias circuit for generating a predetermined potential between a potential of a first power supply and a potential of a second power supply, and a first electrostatic and inverted input signal oscillating between the potential of the first power supply and the potential of the second power supply. And a first driver circuit converting the differential signal oscillating between the output potential of the first bias circuit and the potential of the first power source based on the first enable signal to output the differential signal, or outputting a high impedance. And a first semiconductor chip comprising a first receiver circuit; A second bias circuit for generating a predetermined voltage between the potential of the third power source and the potential of the fourth power source; receiving a second electrostatic and inverting input signal oscillating between the potential of the third power source and the potential of the fourth power source; A second driver circuit which converts the differential signal oscillating between the output potential of the second bias circuit and the potential of the third power source based on the second enable signal and outputs the differential signal or the output becomes high impedance. And a second semiconductor chip including a second receiver circuit, wherein output terminals of the first and second driver circuits are connected by a transmission line, and the first receiver circuit is connected to an output of the first driver circuit. It operates at high impedance and detects a differential signal from the second driver circuit transmitted through the transmission wiring to detect the potential of the first power supply and the second The second receiver circuit operates when the output of the second driver circuit is high impedance and converts the differential signal from the first driver circuit transmitted through the transmission wiring to be a signal oscillating between the potentials of the source. Detecting and converting the signal into a vibrating signal between the potential of the third power source and the potential of the fourth power source. 14. The circuit of claim 13, wherein the first bias circuit comprises a series circuit in which a plurality of first conductive M0S transistors connected to respective gates and drains are connected in series, and another M0S transistor of the first conductive type; One end, which is the source side of the series circuit, is connected to the first power supply, and the other end, which is the drain side of the series circuit, is connected to a current source and a gate of another MOS transistor of the first conductivity type, and the first conductivity. A drain of another M0S transistor of the type is connected to the second power supply so that a bias potential is output from a source of the other MOS transistor of the first conductivity type, and the second bias circuit has a second conductivity with each gate and drain connected thereto. A source circuit of the series circuit having a series circuit in which a plurality of M0S transistors of the type are connected in series and another MOS transistor of the second conductivity type One end is connected to the third power supply, the other end, which is the drain side of the series circuit, is connected to a current source and the gate of another M0S transistor of the second conductivity type, and the drain of the other MOS transistor of the second conductivity type is And a bias potential is output from a source of another MOS transistor of the second conductivity type connected to the fourth power source. A plurality of semiconductor chips arranged in a matrix form, each semiconductor chip has an input / output terminal for data transmission, and the input / output terminal is connected by an input / output terminal of another adjacent semiconductor chip by a transmission wiring consisting of bonding wiring or substrate wiring. In addition, a small amplitude input / output circuit is set at an input / output terminal for data transfer of all or part of the semiconductor chip, and the small amplitude input / output circuit is a first power source corresponding to a semiconductor chip provided with the small amplitude input / output circuit. Receives an electrostatic and inverted signal that vibrates between a first potential of the second power supply and a second potential of the second power supply, and converts the signal to a small amplitude signal that vibrates between a predetermined potential between the first potential and the second potential and the first potential. The converted signal is sent to the input / output terminals of other semiconductor chips adjacent to each other via the transmission wiring, A semiconductor integrated circuit device, comprising a step of converting a small amplitude signal comes transmitted as a signal that oscillates between the first potential and the second potential via. 16. The circuit of claim 15, wherein the small amplitude input / output circuit comprises: a bias circuit for generating a predetermined potential between the first potential and the second potential; Receives an electrostatic and inverting input signal oscillating between the first potential and the second potential, converts the signal into an oscillating signal between the output potential of the bias circuit and the first potential based on an enable signal, and converts this signal. A driver circuit for driving the transmission wiring with the received signal or for output having high impedance, and a voltage divider circuit for dividing the output potential of the bias circuit; And a receiver circuit which detects a signal transmitted through said transmission wiring and converts it into a signal oscillating between said first potential and said second potential using the output of said voltage divider circuit as a reference potential. Integrated circuit devices. 16. The circuit of claim 15, wherein the small amplitude input / output circuit comprises: a bias circuit for generating a predetermined potential between the first potential and the second potential; Receiving an electrostatic and inverting input signal oscillating between the first potential and the second potential and converting the signal into a differential signal oscillating between the output potential of the bias circuit and the potential of the first power source based on an enable signal A driver circuit for driving the electrical transmission wiring or for output having a high impedance; And a receiver circuit for detecting a differential signal transmitted through said transmission line and converting it into a signal oscillating between said first potential and said second potential. A first to n-th semiconductor chip arranged in a row, the first semiconductor chip comprising a first functional means having a predetermined processing function, a first input / output terminal for data transmission, and an output of the first functional means. A small amplitude signal having an amplitude smaller than this output is converted into a small amplitude signal and sent to the adjacent second semiconductor chip through the first input / output terminal, and a small amplitude signal transmitted from the second semiconductor chip through the first input / output terminal is transmitted. And a first small amplitude input / output circuit for converting into a large amplitude signal having an amplitude larger than that of the small amplitude signal and sending it to the first functional means, wherein the semiconductor chip of the i < th > Is the i-th functional means having a predetermined processing function, the input / output terminals of the second (i-1) and second i-1 for data transmission, and the small amplitude input / output circuits of the second (i-1) and second i-1. And an i-1th switch circuit, wherein the i-1th switch The furnace sends the output of the i-th functional means to the small amplitude input / output circuit of the second (i-1) or the small amplitude input / output circuit of the second i-1 based on a control signal, and the second (i-1) Outputs the output of the small amplitude input / output circuit of the second amplitude input / output circuit or the second amplitude input / output circuit of the second i-1 to the i < th > And the second amplitude (i-1) outputs the output of the switch circuit of the i-1 to a smaller amplitude than this output. The signal is converted into a small amplitude signal and sent to the semiconductor chip of the i-1 through the input / output terminal of the second (i-1), and the i-1 through the input / output terminal of the second (i-1). Small amplitude signals transmitted from the semiconductor chip of the Converts the signal into a large amplitude signal and sends it to the switch circuit of the i-1, and the small amplitude input / output circuit of the second i-1 outputs the output of the switch circuit of the i-1 to a small amplitude signal having an amplitude smaller than this output. And a small amplitude signal transmitted from the semiconductor chip of the i + 1 through the input and output terminals of the i + 1 through the in-output terminal of the second i-1, Is converted into a large amplitude signal having an amplitude larger than that of the small amplitude signal, and is sent to the switch circuit of the i-th. The n-th semiconductor chip includes n-th functional means having a predetermined processing function and a data transfer agent. 2 (n-1) input and output terminals of the nth function means are converted into a small amplitude signal having an amplitude smaller than this output and adjacent to the n-1-1 input terminal through the second (n-1) input / output terminal. The semiconductor chip of the nth-1 A second amplitude signal transmitted from the second (n-1) input / output terminal to a large amplitude signal having an amplitude larger than that of the small amplitude signal and transmitted to the nth function means; A small amplitude input / output circuit of which i < i > The input / output terminal of the second i-1 of the semiconductor chip of n-1) is connected to the input / output terminal of the second i of the semiconductor chip of the i + 1 by a transmission wiring including bonding wiring or substrate wiring. A semiconductor integrated circuit device. The switch circuit of claim 18, wherein the switch circuit of the i < th > (i = 1, ..., n-2) conducts the small amplitude input / output circuit of the second i and the function means of the i + 1 based on a first control signal. A second switch element configured to conduct electrical conduction between the first means of the i + 1 function and the small amplitude input / output circuit of the second i + 1 based on a second control signal, and the second amplitude input / output circuit And a third X switch element that conducts the small amplitude input / output circuit of second i + 1 based on the third control signal, wherein the switch element of j-th (j = 1, ..., 3) receives the j-th control signal. And a transfer gate comprising an N-channel MOS transistor received at the gate and a P-channel M0S transistor receiving the inverted signal of the j-th control signal, wherein the first to third control signals have a value of "1". H '' level, the other two control signals It is a "1" level, The semiconductor integrated circuit device characterized by the above-mentioned. A first to n-th semiconductor chip arranged in a row, the first semiconductor chip comprising a first functional means having a predetermined processing function, a first input / output terminal for data transmission, and an output of the first functional means. A small amplitude signal having an amplitude smaller than this output is converted into a small amplitude signal and sent to the adjacent second semiconductor chip through the first input / output terminal, and a small amplitude signal transmitted from the second semiconductor chip through the first input / output terminal is transmitted. And a first small amplitude input / output circuit for converting into a large amplitude signal having an amplitude larger than that of the small amplitude signal and sending it to the first functional means, wherein the semiconductor chip of the i th (i = 2, ..., n-1) Is the i-th functional means having a predetermined processing function, the input / output terminals of the second (i-1) and second i-1 for data transmission, and the small amplitude input / output circuits of the second (i-1) and second i-1. And a selector circuit of second (i-1) and second i-1, wherein the second (i The small amplitude input / output circuit of -1) transmits the small amplitude signal transmitted from the semiconductor chip of i-1 adjacent through the input / output terminal of the second (i-1) to a large amplitude signal having an amplitude larger than this small amplitude signal. Converts the signal from the selector circuit of the second (i-1) into a signal having a smaller amplitude than the signal and converts the signal from the selector circuit of the second (i-1) into the second (i-1) signal. And the small amplitude input / output circuit of the second i-1 is transmitted from the adjacent i + 1 semiconductor chip through the input / output terminal of the second i-1. The small amplitude signal is converted into a large amplitude signal having an amplitude greater than that of the small amplitude signal, and is sent to the selector circuit of the second i-1, and the signal from the select opportunity of the second i-1 is set to an amplitude larger than this signal. The signal is converted into a small signal and is transferred through the input / output terminal of the second i-1. The second (i-1) selector circuit outputs the signal of the i < th > functional means and the signal from the second < RTI ID = 0.0 > i-1 < / RTI > A signal from the second amplitude input / output circuit of the second amplitude (i-1) is selected based on a control signal, and sent to the first amplitude input / output circuit of (1); And the second i-1 selector circuit outputs the output of the i-th functional means and the signal from the second (i-1) selector. Sending to a circuit, and simultaneously selecting a signal from the second amplitude input / output circuit of the second i-1 based on the control signal and sending the signal to the i-th functional means or the selector circuit of the second (i-1), The n-th semiconductor chip includes n-th functional means having a predetermined processing function and a second (n-1) for data transfer. Is converted into a small amplitude signal having an amplitude smaller than this output and sent to the n-th semiconductor chip adjacent through the second (n-1) input / output terminal. At the same time, the small amplitude signal transmitted from the n-th semiconductor chip through the input / output terminal of the second (n-1) is converted into a large amplitude signal having an amplitude larger than the small amplitude signal to thereby convert the n-th functional means. And a second (n-1) small amplitude input / output circuit to be sent to the semiconductor integrated circuit device. 19. The semiconductor integrated circuit device according to claim 18, wherein the first semiconductor chip includes a CPU, and the second to nth semiconductor chips each include a memory. 21. The semiconductor integrated circuit device according to claim 20, wherein the first semiconductor chip includes a CPU, and the second to nth semiconductor chips each include a memory. 19. The semiconductor integrated circuit device according to claim 18, wherein the first to n-th semiconductor chips each include a CPU, and the n-th semiconductor chip includes a memory. 21. The semiconductor integrated circuit device according to claim 20, wherein each of the first to n-th semiconductor chips includes a CPU, and the n-th semiconductor chip includes a memory. 8. The semiconductor integrated circuit device according to claim 7, wherein said wiring connecting said first voltage divider circuit and said second voltage divider circuit is any one of a bonding wiring, a substrate wiring, or a bus. 8. The semiconductor integrated circuit device according to claim 7, wherein the transmission wiring connecting the first driver circuit and the second driver circuit is any one of a bonding wiring, a substrate wiring, or a bus. The semiconductor integrated circuit device according to claim 13, wherein the transmission wiring connecting the first driver circuit and the second driver circuit is any one of a bonding wiring, a substrate wiring, or a bus. 15. The semiconductor integrated circuit device according to claim 14, wherein the transmission wiring connecting the first driver circuit and the second driver circuit is any one of a bonding wiring, a substrate wiring, or a bus. 8. The circuit according to claim 7, wherein the wiring for connecting the first voltage dividing circuit and the second voltage dividing circuit and the transfer wiring for connecting the first driver circuit and the second driver circuit are buses. And the second semiconductor chip are configured to be stacked. 15. The semiconductor device according to claim 13, wherein the transfer electrode connecting the first driver circuit and the second driver circuit is a bus, and the first semiconductor chip and the second semiconductor chip are configured to be stacked. Integrated circuit devices. 15. The semiconductor device according to claim 14, wherein the transfer electrode connecting the first driver circuit and the second driver circuit is a bus, and the first semiconductor chip and the second semiconductor chip are configured to be stacked. Integrated circuit devices.

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