KR100235960B1 - Method of forming conducting line in semiconductor device - Google Patents
Method of forming conducting line in semiconductor device Download PDFInfo
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- KR100235960B1 KR100235960B1 KR1019960049391A KR19960049391A KR100235960B1 KR 100235960 B1 KR100235960 B1 KR 100235960B1 KR 1019960049391 A KR1019960049391 A KR 1019960049391A KR 19960049391 A KR19960049391 A KR 19960049391A KR 100235960 B1 KR100235960 B1 KR 100235960B1
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- forming
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- nitride
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 25
- 239000010410 layer Substances 0.000 description 11
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 도전라인 형성방법에 관한 것으로, 포토 공정상 도프 마진(DOF Margin)을 확보하기 위해 평탄화 공정도 필요한데 필요한 평탄화를 얻기 위해서는 디바이스 전체의 단차가 증가하게 된다. 이러한 디바이스 전체의 단차가 증대하는 것을 방지하기 위하여 반도체 소자에서 게이트를 형성하고, 나이트라이드를 증착하고, 도전용 폴리실리콘을 증착하며, 평탄화 공정을 거치고 희생용 폴리실리콘을 이용하여 단차증가 없이 도전라인을 형성하는 방법에 관한 것이다.The present invention relates to a method for forming a conductive line of a semiconductor device, and a flattening process is also required in order to secure a DOF margin in a photolithography process. In order to prevent the step height of the entire device from increasing, a gate is formed in a semiconductor device, a nitride is deposited, a conductive polysilicon is deposited, a planarization process is performed, and polysilicon for sacrifice is used. To a method for forming the same.
Description
본 발명은 반도체 소자의 도전라인 형성방법에 관한 것으로, 특히 반도체 메모리 소자의 게이트전극 형성후 그 상부에 형성되는 도전라인의 형성공정시 평탄화층으로인한 소자의 두께 감소를 가능하게 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a conductive line of a semiconductor device, and more particularly, to a technique for reducing a thickness of a device due to a planarization layer in a process of forming a conductive line, .
일반적으로 비트라인 등의 도전라인을 형성할때에는 이전에 형성된 도전라인 예를들어 게이트와의 층간 절연을 위해서 절연 산화막이 필요하며, 그 외에 포토 공정상의 도프 마진(DOF Margin)을 확보하기 위해서 평탄화 공정도 필요하다. 특히 디바이스가 집적화되어 선폭이 감소할수록 평탄화가 이루워지지 않으면, 포토 공정이 불가능하게 된다.In general, when a conductive line such as a bit line is formed, an insulating oxide film is required for interlayer insulation with a previously formed conductive line, for example, a gate. In addition, in order to secure a dope margin (DOF margin) Is required. Particularly, as the devices are integrated and the line width is reduced, the planarization can not be achieved, and the photolithography process becomes impossible.
평탄화를 얻기 위해서는 디바이스 전체의 단차가 증가하게 된다.In order to obtain planarization, the step height of the entire device is increased.
디바이스 전체의 단차가 증가하게 되면 후속 공정의 공정 마진을 줄이게 되는 데, 특히 메탈 콘택의 경우에는 종횡비인 에스펙트비(Aspect Ratio)가 증가하여 메탈의 피복성이 떨어지는 큰 이유가 되며, 이외에 여러 가지 이유로 디바이스 단차의 증가는 반도체소자의 생산성을 감소시키는 문제점으로 대두된다.As the step height of the entire device increases, the process margin of the subsequent process is reduced. Particularly, in the case of the metal contact, the Aspect Ratio, which is the aspect ratio, increases, For this reason, the increase in the device level difference poses a problem of reducing the productivity of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 게이트전극을 형성하고 그 표면에 절연막을 형성한 다음, 도전라인용 폴리실리콘을 증착한 다음 후속공정에서 도전배선 마스크를 이용한 사진식각공정으로 패터닝하여 소자의 두께를 감소시킴으로써 반도체소자의 고집적화를 가능하게 하는 반도체소자의 도전라인 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art described above, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a gate electrode is formed, an insulating film is formed on the gate electrode, polysilicon for a conductive line is deposited, And a method of forming a conductive line of a semiconductor device that enables high integration of a semiconductor device by reducing the thickness of the device.
제1도 내지 제7도는 본 발명의 실시예에 따른 반도체소자의 도전라인 형성방법을 도시한 단면도.1 to 7 are sectional views showing a method of forming a conductive line of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1 : 반도체기판 2 : 필드산화막1: semiconductor substrate 2: field oxide film
3 : 게이트 옥사이드 4 : 게이트3: gate oxide 4: gate
5 : 마스크 옥사이드 6 : 옥사이드 스페이서5: mask oxide 6: oxide spacer
7 : 나이트라이드 8 : 폴리실리콘7: Nitride 8: Polysilicon
9 : 절연 산화막 10, 13 : 감광막 패턴9: insulating oxide film 10, 13: photosensitive film pattern
11 : 콘택홀 12 : 희생용 폴리실리콘11: contact hole 12: sacrificial polysilicon
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 도전라인 형성방법은, 반도체소자의 도전라인 형성방법에 있어서, 게이트가 구비된 반도체기판 표면에 나이트라이드를 증착하고 그 상부에 제1도전체를 형성하는 공정과, 상기 제1도전체 상부에 평탄화절연막을 형성하는 공정과, 상기 도전라인 콘택마스크를 이용하여 상기 반도체기판을 노출시키는 도전라인 콘택홀을 형성하는 공정과, 상기 콘택홀을 매립하는 제2도전체를 형성하는 공정과, 상기 제2도전체 상부에 도전라인 마스크를 이용한 노광 및 현상공정으로 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 상기 제2도전체 및 평탄화절연막을 식각하는 공정과, 상기 감광막패턴을 제거하고, 상기 제2도전층과 제1도전체를 전면 건식식각하여 상기 평탄화절연막의 상부면을 노출시키는 공정과, 상기 평탄화절연막을 습식방법으로 제거하고 상기 식각된 제1도전체를 마스크로 하여 상기 나이트라이드를 식각해 도전라인을 형성하는 공정을 포함하는 것을 제1특징으로 한다.As described above, the method of forming a conductive line of a semiconductor device according to the present invention is a method of forming a conductive line of a semiconductor device, in which nitride is deposited on the surface of a semiconductor substrate having a gate and a first conductor is formed thereon Forming a conductive line contact hole for exposing the semiconductor substrate using the conductive line contact mask; forming a conductive line contact hole for exposing the semiconductor substrate, Forming a second conductive layer on the second conductive layer by a photolithography process; forming a second conductive layer on the second conductive layer; forming a second conductive layer on the second conductive layer by an exposure and development process using a conductive line mask; Etching the second conductive layer and the first conductor by dry etching the second conductive layer and the first conductive layer to form a top surface of the planarization insulating film, A step of removing the planarization insulating film by a wet method and etching the nitride with the etched first conductor as a mask to form a conductive line.
또한, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 도전라인 형성방법은, 반도체소자의 도전라인 형성방법에 있어서, 게이트가 구비된 반도체기판 표면에 나이트라이드를 증착하고 그 상부에 비트라인용 폴리실리콘을 형성하는 공정과, 상기 비트라인용 폴리실리콘 상부에 평탄화절연막을 형성하는 공정과, 상기 비트라인용 콘택마스크를 이용하여 상기 반도체기판을 노출시키는 비트라인 콘택홀을 형성하는 공정과, 상기 콘택홀을 매립하는 희생용 폴리실리콘을 형성하는 공정과, 사익 희생용 폴리실리콘 상부에 비트라인 마스크를 이용한 노광 및 현상공정으로 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 상기 희생용 폴리실리콘을 식각하고 상기 감광막패턴을 제거하는 공정과, 상기 식각된 희생용 폴리실리콘을 마스크로하여 상기 평탄화절연막을 식각하는 공정과, 상기 식각된 평탄화절연막을 식각장벽으로 하여 상기 희생용 폴리실리콘과 비트라인용 폴리실리콘을 전면 건식식각해 상기 평탄화절연막의 상부면을 노출시키는 공정과, 상기 평탄화절연막을 습식방법으로 제거하고 상기 식각된 비트라인용 폴리실리콘을 마스크로 하여 상기 나이트라이드를 식각해 비트라인을 형성하는 공정을 포함하는 것을 제2특징으로한다.In order to attain the above object, a method for forming a conductive line of a semiconductor device according to the present invention is a method for forming a conductive line of a semiconductor device, comprising the steps of depositing nitride on the surface of a semiconductor substrate provided with a gate, Forming a bit line contact hole for exposing the semiconductor substrate using the contact mask for a bit line; forming a bit line contact hole in the bit line contact hole, Forming a sacrificial polysilicon filling the contact hole; forming a photoresist pattern by an exposure and development process using a bit line mask on top of the sacrifice polysilicon; and using the photoresist pattern as a mask, A step of etching the polysilicon and removing the photoresist pattern; and a step of etching the etched sacrificial polysilicon Etching the planarization insulating film using the planarization insulating film as an etching barrier, exposing the upper surface of the planarization insulating film by dry etching the sacrificial polysilicon and the bit line polysilicon using the etched planarization insulating film as an etching barrier, A step of removing the planarization insulating film by a wet method, and etching the nitride using the etched bit line polysilicon as a mask to form a bit line.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도 내지 제7도는 발명의 실시예에 따른 반도체소자의 도전라인 형성방법을 도시한 단면도이다.1 to 7 are sectional views showing a method of forming a conductive line of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체 기판(1)위에 소자분리(Isolation)공정을 통해서 필드산화막(2)을 형성하고 ;게이트 옥사이드(3), 게이트용 폴리실리콘, 마스크 옥사이드(5)등을 증착한 후, 게이트 마스크를 이용한 식각공정으로 일정간격 이격된 게이트(4)를 형성하고, 게이트(4)의 측벽에 게이트 옥사이드 스페이서(6)를 형성한 다음, 반도체 기판(1)으로 불순물을 주입하여 소오스/드레인용 확산영역(도시안됨)을 형성한다.(제1도)First, a field oxide film 2 is formed on a semiconductor substrate 1 through an isolation process, a gate oxide 3, polysilicon for a gate, a mask oxide 5 and the like are deposited, A gate oxide spacer 6 is formed on the sidewall of the gate 4 and an impurity is implanted into the semiconductor substrate 1 to form a source / (Not shown). (Figure 1)
그리고, 전체적으로 나이트라이드(7), 비트라인용 폴리실리콘(8)을 증착하고, 그 상부에 평탄화절연막인 절연 산화막(9)을 형성한 다음 평탄화 식각한 후, 그 상부에 비트라인 콘택 마스크용 감광막 패턴(10)을 형성한다.Then, the nitride film 7 and the bit line polysilicon 8 are deposited as a whole, an insulating oxide film 9 as a planarization insulating film is formed thereon, and then planarization etching is performed thereon. Then, Pattern 10 is formed.
이 때, 상기 절연 산화막(9)은 BPSG(Boro Phospho Silicat Glass)를 이용할 수 있으며, 상기 나이트라이드(7)를 증착하기 전에 옥사이드(도시안됨)를 증착하여 나이트라이드(7)에 의해서 트랜지스터의 특성이 열화되는 현상을 방지할 수도 있다.In this case, the insulating oxide film 9 may be formed of borophosphosilicate glass (BPSG), and an oxide (not shown) may be deposited before the nitride 7 is deposited, It is possible to prevent the phenomenon of deterioration.
참고로, 상기한 공정에서 나이트라이드(9) 상부에 도전라인용 폴리실리콘(8)을 증착하지 않고 콘택 공정을 진행하게 되면 자기 정렬 콘택(SAC)의 일종인 나이트라이드 베리어 SAC에 적용되는 일반적인 공정단계가 된다.(제2도)When the contact process is performed without depositing the polysilicon 8 for the conductive line on the nitride 9 in the above-described process, the general process applied to the nitride barrier SAC, which is a self-aligned contact (SAC) (Fig. 2)
그 다음, 상기 감광막 패턴(10)을 마스크로 이용하여 콘택지역의 절연 산화막(9), 비트라인용 폴리실리콘(8), 나이트라이드(7)를 순차적으로 식각함으로써 반도체 기판(1)을 노출시키는 비트라인용 콘택홀(11)을 형성한 다음, 상기 감광막 패턴(10)을 제거한다.Next, the semiconductor substrate 1 is exposed by successively etching the insulating oxide film 9, the bit line polysilicon 8, and the nitride 7 using the photoresist pattern 10 as a mask After the bit line contact hole 11 is formed, the photoresist pattern 10 is removed.
이 때, 상기 나이트라이드(7) 증착전에 옥사이드(도시안됨)를 증착한 경우는 옥사이드까지 식각하면 된다.(제3도)In this case, if an oxide (not shown) is deposited before the deposition of the nitride 7, the oxide may be etched as well (FIG.
그 다음, 전체표표면상부에 희생용 폴리실리콘(12)을 증착하고, 그 상부에 감광막을 도포한 후, 도전라인용 마스크를 이용한 노광 및 현상공정으로 감강막 패턴(13)을 형성한다.(제4도)Then, a sacrificial polysilicon film 12 is deposited on the entire surface of the entire surface of the substrate, a photosensitive film is applied on the sacrificial polysilicon film 12, and a thin film pattern 13 is formed by an exposure and development process using a mask for a conductive line. 4)
그리고, 상기 감광막 패턴(13)을 마스크로 이용하여 노출된 희생용 폴리실리콘(12)을 식각하여 희생용 폴리실리콘 패턴(12')을 형성한다.(제5도)Then, the sacrificial polysilicon 12 is etched using the photoresist pattern 13 as a mask to form a sacrificial polysilicon pattern 12 '(FIG. 5).
그리고, 상기 노출된 절연산화막(9)을 식각한 상태를 도시한 것이다.In addition, the exposed insulating oxide film 9 is etched.
참고로, 상기 감광막 패턴(13)을 제거하고, 희생용 폴리실리콘 패턴(12')을 식각 장벽으로 사용하여 하부의 절연 산화막(9)을 식각하는 것도 가능하다.(제6도)For reference, it is also possible to remove the photoresist pattern 13 and use the sacrificial polysilicon pattern 12 'as an etching barrier to etch the underlying insulating oxide film 9. (FIG. 6)
제7도는 상기 감광막 패턴(13)을 제거하고, 상기 절연 산화막(9)을 식각장벽으로 하여 희생용 폴리실리콘 패턴(12')과 비트라인용 폴리실리콘(8)을 전면 건식 식각함으로써 비트라인(8')을 형성하고, 상기 절연 산화막(9)을 습식 식각으로 제거하고, 상기 비트라인(8')을 식각 장벽으로 이용하여 상기 나이트라이드(7)를 건식 식각한다.7 shows the step of removing the photoresist pattern 13 and dry-etching the sacrificial polysilicon pattern 12 'and the bit line polysilicon 8 with the insulating oxide film 9 as an etching barrier to form bit lines 8 ', the insulating oxide film 9 is removed by wet etching, and the nitride 7 is dry-etched using the bit line 8' as an etching barrier.
여기서, 상기 나이트라이드(7)는 제거하지 않아도 무방하며 제거하지 않는 경우에는 후속공정인 도전라인 콘택공정에서 나이트라이드 베리어 SAC에 이용될 수 있다.(제7도)If the nitride 7 is not removed and is not removed, the nitride 7 may be used in a nitrid barrier SAC in a subsequent process of a conductive line contact process. (FIG. 7)
아울러, 본 발명의 다른 실시예는 저장전극이나 금속배선의 형성시 실시하는 것이다.In addition, another embodiment of the present invention is carried out when the storage electrode or the metal wiring is formed.
상기한 바와 같이 본 발명에 따른 반도체소자의 도전라인 형성방법은, 평탄화층에 의한 소자의 두께 감소를 시현함으로써 후속공정에 공정마진을 용이하게 확보할 수 있으며 소자의 고집적화를 가능하게 하는 효과를 갖는다.As described above, the method of forming a conductive line of a semiconductor device according to the present invention exhibits reduction in thickness of a device by a planarizing layer, thereby easily securing a process margin in a subsequent process and enabling high integration of devices .
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960049391A KR100235960B1 (en) | 1996-10-29 | 1996-10-29 | Method of forming conducting line in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960049391A KR100235960B1 (en) | 1996-10-29 | 1996-10-29 | Method of forming conducting line in semiconductor device |
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| KR19980030041A KR19980030041A (en) | 1998-07-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100419752B1 (en) * | 1999-12-28 | 2004-02-21 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100419752B1 (en) * | 1999-12-28 | 2004-02-21 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
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